JP4159281B2 - Method, program and apparatus for designing semiconductor device - Google Patents

Description

[0001]
The present invention relates to a method of semiconductor device design relates to program and equipment.
[0002]
[Prior art]
FIG. 11 is a schematic flowchart showing a conventional semiconductor device design method. In the following, the step identification codes in the figure are shown in parentheses.
[0003]
(S1) A floor plan is performed. That is, referring to the netlist, rough wiring is performed between a plurality of functional blocks so as to minimize the value of the given evaluation function, and the functional blocks are arranged.
[0004]
FIG. 12 shows functional blocks 121 to 124 arranged on the chip area 10 by this floor plan. An I / O buffer cell 11 including a buffer circuit and a bonding pad is juxtaposed at the edge of the chip region 10.
[0005]
(S2) In order to supply a power supply voltage to each functional block, grid-like power supply wirings 13 and 14 as shown in FIG. 13 are arranged in different wiring layers. The grid power supply wires 13 and 14 are for supplying a power supply potential of, for example, 3.0V and 0V, respectively. The grid-like power supply wiring 13 has a rectangular frame, and the power supply wirings inside the rectangular frame are parallel to each other, and the pitch and wiring width are determined based on the consumption current of the chip and the allowable fluctuation range of the power supply potential. The grid power supply wiring 14 is the same as the grid power supply wiring 13 rotated by 90 °. In FIG. 13, the grid power supply wiring 14 is hatched. When the grid power supply wiring is used, the current is made more uniform than in the case of the ring power supply wiring, so that the power supply potential supplied to each functional block is more stable.
[0006]
(S3) With respect to each functional block, the cell library is referred to and rough wiring is performed between the cells so that the value of the evaluation function given in advance is minimized, and cells for forming circuit elements are arranged.
[0007]
(S4) Inter-cell wiring is performed.
[0008]
(S5) In step S4, signal wiring is performed in accordance with the design rule. At this time, the relationship with the power supply wiring in step S2 is not considered. Therefore, it is verified whether or not the cell terminal is short-circuited with the power supply wiring, and whether or not the interval between the inter-cell wiring and the power supply wiring satisfies the design rule.
[0009]
For example, as shown in FIG. 14, when the terminals 161 and 162 of the cell 15 are connected to the inter-cell wiring on the same layer as the wiring 131 of the grid power supply wiring 13 (FIG. 13), the cell terminal 162 is short-circuited with the power supply wiring 131. Therefore, it is determined to be defective. In FIG. 14, the signal line 171 is arranged in a different layer from the wiring 141 of the grid power supply wiring 14 (FIG. 13) and is connected to the cell terminal 161.
[0010]
In addition, as shown in FIG. 15, even if the cell terminal 162 is not short-circuited with the power supply wiring 131, if the distance between the signal line 172 connected to the cell terminal 162 and the power supply wiring 131 does not satisfy the design rule, It is determined.
[0011]
(S6) If a failure is determined in step S5, the process returns to step S1 to change the arrangement of functional blocks or the partition between blocks in order to eliminate the defective portion.
[0012]
[Problems to be solved by the invention]
However, even if the defect is eliminated by this change, a new defect may occur in another part. For this reason, the processes in steps S1 to S6 are repeatedly performed, which causes a longer design period. Instead of returning from step S6 to step S1, returning to step S2 to change the wiring pitch and wiring width of the grid-like power supply wires 13 and 14 or returning to step S3 to move the cell also affects other parts. So the same. In addition, if the defective power supply arrangement line is deleted in order to avoid the above-described repetitive processing, the current distribution on the power supply wiring in the vicinity of the deleted portion becomes nonuniform, and the power supply potential cannot be stably supplied to the functional block. .
[0013]
In view of such problems, an object of the present invention is to eliminate a defect without generating a new defective portion when a defective portion between the grid-like power supply wiring and the inter-cell signal wiring is detected. the method of semiconductor device design it is possible to shorten the design time, the present invention is to provide a program and equipment.
[0015]
[Means for solving the problems and their effects]
In one aspect of the semiconductor device design method of the present invention,
(A) Arrange functional blocks,
(B) arranging a grid-like power supply wiring for supplying a power supply potential to the functional block;
(C) arranging cells for constituting the functional block;
(D) Perform inter-cell wiring,
(E) It is determined whether or not the cell terminal is short-circuited with the power supply wiring and whether or not the interval between the inter-cell wiring and the power supply wiring satisfies the design rule.
[0016]
If a failure is determined in step (e),
(F1) Specify an area including a defective part,
(F2) The power supply wiring is shifted in the direction perpendicular to the longitudinal direction in the region, and the process returns to step (e).
[0017]
The power supply wiring in the region is connected to the same-potential power supply wiring of another layer through an interlayer contact, or the region includes a frame of the grid-shaped power supply wiring, and is connected to the grid-shaped power supply wiring through the frame. .
[0018]
According to this configuration, by shifting only the power supply wiring in the designated area including the defective portion, it is possible to locally solve the short circuit between the power supply wiring and the inter-cell signal wiring and the shortage of the interval, Since the influence of the power supply wiring shift does not affect the outside of the designated area, it is possible to solve the problem that the design period becomes long due to the conventional iterative process.
[0019]
In one aspect of the semiconductor device of the present invention, in each of the first and second layers, the semiconductor device having a grid-like power supply wiring arranged so as to cross over between the layers.
The power supply wiring in a partial region of the grid-like power supply wiring is shifted in a direction perpendicular to the longitudinal direction with respect to the power supply wiring outside the region and in the same layer, and the power supply wiring in the region is It is connected to the power wiring of the other layer through the contact.
[0020]
According to this configuration, since the defective portion can be eliminated without deleting the power supply arrangement line at the defective portion, it is possible to supply a more stable power supply potential to the circuit.
[0021]
Other objects, configurations and effects of the present invention will become apparent from the following description.
[0022]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings.
[0023]
[First Embodiment]
FIG. 1 is a schematic flowchart showing a semiconductor device design method according to the first embodiment of the present invention. The processing in FIG. 1 is executed by a computer system in which a general input / output device is connected to the computer main body.
[0024]
The difference from FIG. 11 is that if the defect is determined in step S6, the process returns to step S7 without returning to step S1, returns to step S5, and if good is determined in step S6, the process returns to step S9. It is a point to process.
[0025]
Further, in step S2, the grid-like wirings 13 and 14 shown in FIG. An interlayer contact hole pattern is formed so that 13 and 14 are connected to each other. The grid potential of the ground potential is the same as that of the grid lines 13 and 14. For example, 3.0V, 0V, 3.0V, and 0V grid-like power supply wiring is formed from the lower layer to the upper layer, and the contact hole pattern is generated so that the crossover points of the same potential power supply wiring are connected by contacts.
[0026]
Hereinafter, the process of the difference will be described.
[0027]
(S7) Designate a region including the defective part detected in step S5, for example, a region A as shown in FIG. This designation is performed, for example, by determining diagonal points P1 and P2 of the area A with a mouse on the display screen. In the case of FIGS. 14 and 15, the area A is designated as shown in FIGS. 5 and 6, for example. The small rectangle described at the crossover point of the two-layer grid-like power supply wiring shown in FIGS. 5 and 6 is the contact hole described above.
[0028]
(S8) The power supply wiring in the designated area A is shifted in the direction perpendicular to the longitudinal direction as shown in FIG. This shift is performed, for example, by moving the mouse pointer into the designated area A and then dragging the mouse for the length to be moved in the desired movement direction.
[0029]
As a result of the shift, as shown in FIG. 4, when the interval between the side A1 of the designated area A parallel to the power supply wiring in the designated area A and the adjacent power supply wiring 131 is longer than the pitch of the power supply wiring. Adds a new power supply wiring 132 to the designated area A, and makes the power supply wiring pitch in the designated area A constant. Thereby, since it is not necessary to add a power supply wiring at the operator's discretion, the processing is simplified. In the case of FIG. 2, the frame of the grid-like power supply wiring 13 is included in the designated area A. In this case, the power supply wiring in the designated area A is shifted so that the frame line is opposite to the designated area A. Even if it is interrupted from one side, the frame line is extended to one side as shown in FIGS. As a result, it is not necessary to extend the frame line at the operator's discretion, so the processing is simplified.
[0030]
In the case of FIG. 5, the power supply wiring in the designated area A is shifted as shown in FIG. 7, thereby separating the cell terminal 162 and the signal wiring 172 connected thereto from the power supply wiring 131A in the area A. . In the case of FIG. 6, the cell terminals 161 and the signal lines 172 connected thereto are moved from the power supply wiring 131 </ b> A in the designated area A by shifting the power supply wiring in the designated area A as shown in FIG. 8. Release.
[0031]
As described above, by shifting only the power supply wiring in the designated area A including the defective portion, the short circuit between the power supply wiring and the signal wiring and the shortage of the gap can be locally solved. Since the influence of the power supply wiring shift is not exerted on the outside, the problem that the design period becomes longer by the repetitive processing as shown in FIG. 11 can be solved.
[0032]
In FIG. 1, for simplification, steps S7 and S8 are described as being processed once. Actually, however, the processes of steps S7 and S8 are performed for all defective points detected in step S5. Do it every time.
[0033]
(S9) Since the crossover point changes due to the shift of the power supply wiring in the designated area A, the contact hole pattern is corrected accordingly. As a result, the contact hole pattern in the designated area A becomes, for example, a small rectangular group pattern in FIGS. 7 and 8, and even if the power supply wiring is not directly connected between the designated area A and the outside of the designated area A, They are connected via contacts.
[0034]
[Second Embodiment]
In the first embodiment, steps S7 and S8 in FIG. 1 are manually shifted. In the second embodiment of the present invention, these processes are automatically performed as follows. FIG. 9 is a flowchart showing a part of this semiconductor device design method.
[0035]
(S10) If the flag F is “0”, the process proceeds to step S11 , and if the flag F is “1”, the process proceeds to step S8A. The initial value of the flag F is “0”.
[0036]
(S11) The flag F is set to “1”.
(S7A) The area designation area A including the defective part detected in step S5 is changed into a signal wiring area parallel to the power wiring of the defective part (in the case of FIG. 5, of the signal wirings to be connected to the cell terminal 162). A range of a predetermined distance is designated from the upper, lower, left, and right ends of the portion parallel to the power supply wiring 131. This designation is performed for all defective portions detected in step S5.
[0038]
(S8A) When an area A as shown in FIG. 10A is designated in step S7A, for example, in step S8A, a predetermined amount of power supply wiring in the designated area A is shown as shown in FIG. 10B. Shift in a direction perpendicular to the longitudinal direction by ΔX. This shift is performed for all the areas designated in step S7A. In FIG. 10, only a part of the grid-like wiring 13 is shown for simplification.
[0039]
Next, verification is performed again in step S5, and if it is determined in step S6 that the portion where the defect has not been eliminated remains, it is determined in step S10 that F = '1' and the process proceeds to step 8A. Only the designated area A where it is determined that the defective portion remains is further shifted by ΔX, and the power supply wiring in the designated area A becomes as shown in FIG. Such a process is repeated until it is determined in step S6 that all defective portions have been eliminated. FIGS. 10D to 10F show a state further shifted by ΔX.
[0040]
According to the second embodiment, the design of the region including the defective portion and the shift process of the power supply wiring in the region are automatically performed, so that the design period can be shortened compared with the first embodiment.
[0041]
Other points are the same as those in the first embodiment.
[0042]
[Third Embodiment]
In step S6 of FIG. 1, when a defect is detected for each of the different power supply wiring layers, and these defective portions are close to each other (within a predetermined range), these defective portions are detected for both power supply wiring layers. One common area A to be included is specified at the same time, and both layers of the power supply wiring in the specified area A are shifted by the same amount at the same time, thereby eliminating the defective portion. Other points are the same as those in the first embodiment.
[0043]
Note that the present invention includes various other modifications.
[0044]
For example, if the designated region A is designated so as to include the frame of the grid-like power supply wiring as shown in FIG. 2, the interlayer contact as shown in FIGS. 7 and 8 need not be formed.
[0045]
As is clear from the above description, the present invention includes the following supplementary notes.
[0046]
(Appendix 1) (a) Arrange functional blocks,
(B) arranging a grid-like power supply wiring for supplying a power supply potential to the functional block;
(C) arranging cells for constituting the functional block;
(D) Perform inter-cell wiring,
(E) determining whether the cell terminal is not short-circuited with the power supply wiring and determining whether the interval between the inter-cell wiring and the power supply wiring satisfies the design rule;
In a semiconductor device design method having steps,
If a failure is determined in step (e),
(F1) Specify an area including a defective part,
(F2) Shifting the power supply wiring in the region in a direction perpendicular to the longitudinal direction, and returning to the step (e),
The power supply wiring in the region is connected to the same-potential power supply wiring of another layer through an interlayer contact, or the region includes a frame of the grid-shaped power supply wiring, and is connected to the grid-shaped power supply wiring through the frame. A method for designing a semiconductor device. (1)
(Appendix 2) In the step (f2), due to the shift, the interval between the side of the region parallel to the power supply wiring and the power supply wiring in the region adjacent to the side becomes longer than the power supply wiring pitch. 2. The semiconductor device design method according to appendix 1, wherein a power supply wiring is added in the region so that the pitch is constant. (2)
(Supplementary note 3) The semiconductor device design method according to supplementary note 1 or 2, wherein in step (f2), the shift amount is manually set so as to eliminate the defective portion.
[0047]
(Supplementary Note 4) In the step (f2), a predetermined shift amount is automatically set, and the defective portion is eliminated by repeating the steps (e), (f1) and (f2) by trial and error. The semiconductor device design method according to appendix 1 or 2.
[0048]
(Supplementary Note 5) The semiconductor device design method according to Supplementary Note 1 or 2, wherein, in the step (f1), the common region is specified for the plurality of layers of the power supply wiring.
[0049]
(Appendix 6)
(A) Arrange functional blocks,
(B) arranging a grid-like power supply wiring for supplying a power supply potential to the functional block;
(C) arranging cells for constituting the functional block;
(D) Perform inter-cell wiring,
(E) determining whether a cell terminal is not short-circuited with the power supply wiring and whether an interval between the inter-cell wiring and the power supply wiring satisfies a design rule;
In a semiconductor device design program having steps,
If it is determined that the computer is defective in step (e),
(F1) Let the area including the defective part be specified,
(F2) The power supply wiring is shifted in the direction perpendicular to the longitudinal direction in the region, and the process returns to step (e).
A semiconductor device design program. (3)
(Supplementary Note 7) In the step (f2), due to the shift, the interval between the side of the region parallel to the power supply wiring and the power supply wiring in the region adjacent to the side becomes longer than the power supply wiring pitch. 7. The semiconductor device design program according to appendix 6, wherein a power supply wiring is added in the region so that the pitch is constant.
[0050]
(Supplementary note 8) A semiconductor device design apparatus, comprising a computer in which the program according to supplementary note 6 or 7 is installed. (4)
(Supplementary note 9) In a semiconductor device having a grid-like power supply wiring arranged so as to cross over between the first and second layers,
The power supply wiring in a partial region of the grid-like power supply wiring is shifted in a direction perpendicular to the longitudinal direction with respect to the power supply wiring outside the region and in the same layer, and the power supply wiring in the region is A semiconductor device, wherein the semiconductor device is connected to a power supply wiring of another layer through a contact. (5)
(Supplementary Note 10) If the distance between the side parallel to the power supply wiring and the power supply wiring in the region adjacent to the side becomes longer than the power supply wiring pitch due to the shift, the pitch becomes constant. The semiconductor device according to appendix 9, wherein power supply wiring is added in the region.
[Brief description of the drawings]
FIG. 1 is a schematic flowchart showing a semiconductor device design method according to a first embodiment of the present invention.
FIG. 2 is an explanatory diagram of step S7 in FIG.
FIG. 3 is an explanatory diagram of step S8 in FIG. 1;
FIG. 4 is an explanatory diagram of step S8 of FIG. 1 and shows the addition of a power supply wiring in a designated area A.
5 is an explanatory diagram of step S7 in FIG. 1 for the defective portion in FIG. 14;
6 is an explanatory diagram of step S7 of FIG. 1 for the defective portion of FIG.
7 is an explanatory diagram of step S8 of FIG. 1 for the specified range of FIG.
8 is an explanatory diagram of step S8 of FIG. 1 for the specified range of FIG.
FIG. 9 is a schematic flowchart showing a semiconductor device design method according to a second embodiment of the present invention.
10 is an explanatory diagram of steps S7A and S7B in FIG. 9;
FIG. 11 is a schematic flowchart showing a conventional semiconductor device design method.
12 is an explanatory diagram of step S1 in FIG. 11;
FIG. 13 is an explanatory diagram of step S2 in FIG.
FIG. 14 is an explanatory diagram of step S5 of FIG.
FIG. 15 is an explanatory diagram of step S5 of FIG.
[Explanation of symbols]
10 Chip area 11 I / O buffer cells 121 to 125 Functional blocks 13, 13A, 13B, 14 Grid-like power supply wiring 131, 132 Power supply wiring 15 Cell 161, 162 Cell terminal 171, 172 Signal line 18 Contact A Designated area

Claims (3)

(A) Arrange functional blocks,
(B) arranging a grid-like power supply wiring for supplying a power supply potential to the functional block;
(C) arranging cells for constituting the functional block;
(D) Perform inter-cell wiring,
(E) determining whether the cell terminal is not short-circuited with the power supply wiring and determining whether the interval between the inter-cell wiring and the power supply wiring satisfies the design rule;
In a semiconductor device design method having steps,
If a failure is determined in step (e),
(F1) Specify an area including a defective part,
(F2) Shifting the power supply wiring in the region in a direction perpendicular to the longitudinal direction, and returning to the step (e),
In this step (f2), if the distance between the side of the region parallel to the power supply wiring and the power supply wiring in the region adjacent to the side becomes longer than the power supply wiring pitch due to the shift, the pitch Add power wiring in the area so that is constant,
The power supply wiring in the region is connected to the same-potential power supply wiring of another layer through an interlayer contact, or the region includes a frame of the grid-shaped power supply wiring, and is connected to the grid-shaped power supply wiring through the frame. A method for designing a semiconductor device. Against the computer
(A) Arrange functional blocks,
(B) arranging a grid-like power supply wiring for supplying a power supply potential to the functional block;
(C) arranging cells for constituting the functional block;
(D) Perform inter-cell wiring,
(E) determining whether a cell terminal is not short-circuited with the power supply wiring and whether an interval between the inter-cell wiring and the power supply wiring satisfies a design rule;
In a semiconductor device design program having steps,
If it is determined that the computer is defective in step (e),
(F1) Let the area including the defective part be specified,
(F2) a power source wiring within that region, is shifted in its longitudinal direction and perpendicular direction, return to the step (e),
In this step (f2), if the distance between the side of the region parallel to the power supply wiring and the power supply wiring in the region adjacent to the side becomes longer than the power supply wiring pitch due to the shift, the pitch Add power wiring in the area so that is constant,
A semiconductor device design program. A semiconductor device design apparatus comprising a computer in which the program according to claim 2 is installed.

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