JP4152636B2 - Method for forming metal contact of semiconductor device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device having a contact due to a bond of Si-Ge and cobalt silicide at a metal-semiconductor interface, and more particularly, a method of forming a low resistance contact in a DRAM (dynamic ad hoc access memory) by a mixed contact method. About.
[0002]
[Prior art]
In the semiconductor manufacturing technology, conventionally, methods for forming an MS contact (metal / semiconductor contact) include an ohmic contact method and a diffusion contact method. In the ohmic contact method, a tunnel barrier is formed by injecting impurities into the MS interface layer so that the concentration of impurities is not less than the solid solution limit (ie, N (n, p)> 10 ²⁰ cm ⁻³ ). Is. On the other hand, in the diffusion contact method, impurities are diffused into the MS boundary surface to lower SBH (Schottky barrier height).
[0003]
Silicon is a frequently used semiconductor, but its intrinsic SBH (or energy gap Eg, Eg = 1.11 eV) is high. Therefore, when using silicon, it is necessary to dope (usually using high energy implantation) at a very high doping concentration at the MS interface in order to lower SBH and obtain good contact. However, in the case of high energy implantation, the contact surface may be deeper than necessary, so that a short channel effect and punch through (leakage) occur in the semiconductor device.
[0004]
[Problems to be solved by the invention]
In order to solve the above-mentioned problems, a first object of the present invention is to provide a semiconductor device having a metal / semiconductor interface of a low resistance contact.
[0005]
A second object of the present invention is to provide a metal contact forming method capable of forming a low resistance contact at the metal / semiconductor interface with appropriate doping and protecting the semiconductor device from the short channel effect and leakage. is there.
[0006]
Furthermore, a third object of the present invention is to provide a metal contact forming method for reducing the manufacturing cost and forming a metal contact in a memory device (for example, DRAM) by a mixed contact method.
[0007]
[Means for Solving the Problems]
In order to achieve the first object, a semiconductor device of the present invention includes a semiconductor substrate, a dielectric layer formed on the semiconductor substrate and having a contact hole exposing the semiconductor substrate, and formed at the bottom of the contact hole. An Si _x Ge _l-x layer (0 <x <l), a conformable cobalt layer formed on the cobalt silicide layer and the sidewall of the contact hole, and the Si _x Ge _l-x layer, A cobalt silicide layer formed between the cobalt layer and a metal plug filling the contact hole and formed on the cobalt layer, wherein the cobalt silicide layer includes the Si _x Ge formed by a chemical reaction with _l-x layer and the cobalt layer.
[0008]
According to another aspect of the present invention, there is provided a method for forming a metal contact in a memory device, comprising: a first FET of a first conductivity type; a first FET of a second conductivity type; A peripheral circuit region having two FETs and an array region having a third FET of the second conductivity type, wherein the first, second and third FETs are respectively first, second and second Providing a conductive substrate including three source / drain regions ; forming a dielectric layer in the semiconductor substrate; and penetrating to the first, second, and third source / drain , respectively, in the dielectric layer Forming a first, second and third contact hole; and a second conductivity type doped Si _x Ge _l-x layer (0 <x in the first, second and third contact holes). Forming <l); A step of masking the serial second and third contact holes, and removing the doped Si _{x Ge} l-x layer in said first contact hole, the first conductivity type in said first source / drain A step of implanting impurities, a step of adaptively forming a cobalt layer in the semiconductor substrate, and a chemical reaction between the cobalt layer and the Si _x Ge _l-x layers in the second and third contact holes. Forming a cobalt silicide layer from the cobalt layer, and diffusing impurities in the Si _x Ge _l-x layer in the second and third contact holes into the second and third sources / drains. And filling the first, second and third contact holes with metal plugs.
[0009]
Furthermore, the metal contact formation method of the present invention for achieving the third object is a method for forming a metal contact in a DRAM, in which a peripheral circuit region having a p-type first FET and an n-type second FET is provided. And an array region having an n-type third FET, wherein the first, second and third FETs provide a semiconductor substrate including first, second and third source / drain regions, respectively. Forming a dielectric layer in the semiconductor substrate; and first, second and third contact holes penetrating to the first, second and third source / drain regions in the dielectric layer, respectively. Forming an n-doped Si _x Ge _l-x layer (0 <x <l) in the first, second and third contact holes, and the second and third Contact hole Masking; removing an n-doped Si _x Ge _l-x layer in the first contact hole; implanting p-type impurities in the first source / drain region; and in the semiconductor substrate A cobalt silicide layer is formed from the cobalt layer by a step of forming a cobalt layer adaptively and a chemical reaction between the cobalt layer and the n-doped Si _x Ge _l-x layers in the second and third contact holes. Diffusing impurities in the n-doped Si _x Ge _l-x layers in the second and third contact holes into the second and third source / drain regions; and Filling the second and third contact holes with metal plugs.
[0010]
DETAILED DESCRIPTION OF THE INVENTION
The configuration and operation of an embodiment of the present invention that accomplishes the above-described object and eliminates the drawbacks of the prior art will be described in detail with reference to the accompanying drawings.
[0011]
FIGS. 1a to 1c are views showing a manufacturing stage according to a metal contact forming method at a metal / semiconductor interface according to a first embodiment of the present invention.
[0012]
In FIG. 1 a, first, a dielectric layer 120 is formed on a semiconductor substrate 100. Then, a contact hole 140 is formed in the dielectric layer 120 so that the semiconductor substrate 100 is exposed. Thereafter, the Si _x Ge _l-x layer 200 is formed in the contact hole 140 (where 0 <x <l). Thereafter, a cobalt layer (Co layer) 220 is adaptively formed on the semiconductor substrate 100.
[0013]
Note that the Si _x Ge _l-x layer 200 is preferably doped, particularly by n doping.
[0014]
As a method of forming the Si _x Ge _l-x layer 200, MBE (molecular beam epitaxy), UHV-CVD (ultra-high vacuum chemical vapor deposition), RT-CVD (rapid heating CVD), and Examples thereof include LRP-CVD (Limited Reaction Processing CVD). For example, the Si _x Ge _l-x layer 200 is formed by selective epitaxy growth at a very low temperature (<800 ° C.).
[0015]
Further, in the Si _x Ge _l-x layer 200, the value of the proportional x is determined as an optimum value based on factors such as selection of a manufacturing process, a work stage, and each layer formed subsequently. Incidentally, the Si _x Ge _l-x layer 200 may be silicon-rich. In this case, since the properties of the Si _x Ge _l-x layer 200 are close to those of pure silicon, the occurrence of dislocation is suppressed. For example, the range of the x value includes 0.5 <x <0.95.
[0016]
According to past data, it can be seen that Si-Ge layers thinner than the critical thickness (thinned by the x value and deposition conditions) do not cause dislocations in the silicon substrate even after subsequent steps performed at high temperatures. Accordingly, the thickness of the Si _x Ge _l-x layer 200 is set to a critical thickness in order to prevent a leakage current at the bonding surface by maintaining dislocations and suppressing dislocations in the silicon substrate due to lattice mismatch between silicon and Si—Ge. However, in the present invention, since the Si _x Ge _l-x layer 200 is somewhat consumed in the subsequent silicidation step, the thickness of the Si _x Ge _l-x layer 200 depends on the consumption. It is necessary to take a value sufficient to counteract, for example, 10-30 nm.
[0017]
Examples of a method for forming (depositing) the adaptable cobalt layer 220 include a PVD method (physical vapor deposition method), a CVD method, and a non-selective deposition method. Since the cobalt layer 220 is used as an adhesion layer / diffusion barrier layer for the dielectric layer 120 (interlayer dielectric layer (ILD layer)), it is not necessary to form another adhesion layer or diffusion barrier layer.
[0018]
Next, in FIG. 1b, a cobalt silicide layer 240 is formed from the cobalt layer 220 by an annealing method. In this embodiment, since the Si _x Ge _l-x layer 200 is selectively formed at the bottom of the contact hole 140, only the portion of the cobalt layer 200 that contacts the bottom of the contact hole 140 is cobalt and the Si _x Ge _l-x layer. Although it changes to the cobalt silicide layer 240 by a chemical reaction with 200 silicon, the portion of the cobalt layer 200 that contacts the side wall of the contact hole 140 remains unchanged.
[0019]
If there is an impurity doped in the Si _x Ge _l-x layer 200, the impurity diffuses into the semiconductor substrate 100 when the annealing method is performed. Therefore, the diffusion region 300 is formed below the Si _x Ge _1-x layer 200 in the substrate 100. Therefore, contact resistance is reduced.
[0020]
Finally, in FIG. 1 c, a metal plug 400 is formed on the cobalt layer 220 so as to fill the contact hole 140. The method for forming the plug 400 includes the following steps, for example. That is, (1) a tungsten layer is formed by a selective growth method, and (2) the tungsten layer is planarized by a CMP (Chemical Mechanical Polishing) method (at the same time, the cobalt layer 220 on the dielectric layer 120 is also removed). )
[0021]
The consistency between the metal contact according to the present invention and the memory device (especially DRAM device) is very good.
[0022]
FIGS. 2a to 2g are views showing a manufacturing stage of a DRAM by a mixed contact method according to a second embodiment of the present invention. The initial state of the semiconductor substrate 10 is as shown in FIG. 2a. In FIG. 2 a, the semiconductor substrate 10 is divided into two as shown by the disconnection, and includes a peripheral circuit region S and an array region (memory region) A. In both the peripheral circuit region S and the array circuit region A, electrical isolation is performed using shallow trench isolation (STI). In the peripheral circuit region S, a p-type field effect transistor (pFET) F1 and an n-type field effect transistor (nFET) F2 are formed on the N well 12 and the P well 14, respectively. Here, the well 12 and the well 14 are electrically separated by the STI. On the other hand, in the array region A, an n-type field effect transistor F 3 is formed on the P well 16. In the vicinity of the p-type field effect transistor F1, the n-type field effect transistor F2, and the n-type field effect transistor F3, source / drain regions S / D1, S / D2, and S / D3 are formed, respectively.
[0023]
Next, as shown in FIG. 2a, after forming the dielectric layer 20 on the substrate 10, the first contact hole penetrating to S / D1 of the p-type field effect transistor region of the peripheral circuit region S in the dielectric layer 20 C1, a second contact hole C2 that penetrates to the S / D2 of the n-type field effect transistor region in the peripheral circuit region S, and a third contact that penetrates to the S / D3 of the n-type field effect transistor region in the array region A Hole C3 is formed.
[0024]
Next, as shown in FIG. 2b, n-doped Si _x Ge _l-x layers 30 are respectively formed in the contact holes C1, C2, and C3 (where 0 <x <l).
[0025]
Next, as shown in FIG. 2c, the n-type field effect transistor regions in the peripheral circuit region S and the array region A are masked (that is, the contact holes C2 and C3 are masked), and the n-doped Si _x Ge _l in the contact hole C1. A photoresist layer 40 that exposes the _-x layer 30 is formed.
[0026]
Next, an injection contact method is applied to the p-type field effect transistor region. As shown in FIG. 2d, first, the n-doped Si _x Ge _l-x layer 30 in the contact hole C1 is removed. Thereafter, implantation is performed on the substrate 10. That is, p-type impurities (for example, boron or boron fluoride) are implanted into the source / drain region S / D1 through the contact hole C1. The implantation step may be performed before removing the SiGe layer.
[0027]
When performing the implantation step, it is necessary to appropriately adjust the implantation energy and the dose so that impurities are distributed near the surface of the substrate 10. For example, implantation is performed with a low energy of 100 eV-10 KeV and a low dose of 1E14-1E15 atoms / cm ² . The implantation may be performed with a high energy of 20 K-80 KeV and a low dose of 5E14-3E15 atoms / cm ² . Further, the ion mixing method may be used. In the case of the ion mixing method, first, implantation is performed with a low energy of 100 eV-10 KeV and a high dose of 1E14-1E16 atoms / cm ² , and then a high energy of 20 KeV-80 KeV and a low dose of 5E13-5E14 atoms / cm ^2. Inject with.
[0028]
In addition, as a better injection method, an injection with an energy lower than 2 KeV and a dose lower than 1E15 atoms / cm ² may be mentioned. In this case, a PLAD (plasma doping) method or a PIII (plasma ion deposition implantation) method is used.
[0029]
Next, RTP (rapid heating process) is performed, for example, at 1050 ° C. and 10 minutes in order to anneal the implanted material and the breakage of the substrate.
[0030]
Next, as shown in FIG. 2 e, after removing the photoresist layer 40, a cobalt layer 50 is adaptively formed on the semiconductor substrate 10. Examples of the method for forming the cobalt layer 50 include a non-selective deposition method such as a PVD method and a CVD method. The cobalt layer 50 is used as an adhesion layer / diffusion barrier layer for the dielectric layer 20 (ILD layer).
[0031]
Next, as shown in FIG. 2F, a cobalt silicide layer 52 is formed from the cobalt layer 50 by subjecting the substrate 10 to a heat treatment (for example, an annealing method). In this case, the n-doped Si _x Ge _l-x layer 30 remains at the bottoms of the contact holes C2 and C3, but has already been removed from the contact holes C1, so that the portion corresponding to the bottoms of the contact holes C2 and C3 of the cobalt layer 50 Only the cobalt silicide layer 52 is converted into a cobalt silicide layer 52 by a chemical reaction between cobalt and silicon in the n-doped Si _x Ge _l-x layer 30, but the portions corresponding to the side walls of the contact holes C 2 and C 3 and the contact hole C 1 of the cobalt layer 50 are left as they are. ,does not change.
[0032]
At the same time that the cobalt silicide layer 52 is formed by heat treatment, diffusion contact is performed in the n-type field effect transistor region. That is, in the n-type field effect transistor region in the peripheral circuit region S and the array region A, the n-type impurity (As or P) in the n-doped Si _x Ge _l-x layer 30 in the contact holes C2 and C3 is being heated. Diffusion into the second and third source / drain regions (S / D2 and S / D3) (see FIG. 2f). For this reason, SBH is lowered, and an automic contact is formed in the n-type field effect transistor region.
[0033]
Finally, as shown in FIG. 2g, a metal plug 60 is formed on the cobalt layer 50 so as to fill the contact holes C1, C2, and C3. The plug 60 is formed by, for example, the following steps. That is, (1) a tungsten layer is formed by selective growth, and (2) the tungsten layer is planarized by CMP (at the same time, the cobalt layer 50 on the dielectric layer 20 is also removed).
[0034]
Although the present invention has been presented as in the foregoing embodiments, this is not intended to limit the present invention, and those skilled in the art can make variations and modifications within the spirit and scope of the present invention.
[0035]
【The invention's effect】
The present invention has the following effects.
[0036]
(1) Since the contact at the metal / semiconductor interface is formed by the combination of the low SBH Si _x Ge _l-x layer, the low resistance cobalt silicide layer, and the cobalt layer, the contact resistance is greatly reduced. Therefore, a good contact can be formed at the metal / semiconductor interface by appropriate doping, and the semiconductor device can be protected from the short channel effect and leakage.
[0037]
(2) Since the cobalt layer is used as an adhesive layer / diffusion barrier layer, it is not necessary to form another adhesive layer or diffusion barrier layer. Therefore, the manufacturing cost can be reduced.
[0038]
(3) According to the present invention, in the n-type field effect transistor region, the contact can be formed by the diffusion contact method by forming the contact of the n-type Si _x Ge _l-x layer. On the other hand, in the p-type field effect transistor region, a mixed contact method can be used by applying an injection contact method. Accordingly, in the present invention, a mixed contact method is used to form the contacts. Accordingly, the manufacturing cost can be reduced by reducing the step of forming the optical mask.
[Brief description of the drawings]
FIG. 1a is a diagram illustrating a part of a manufacturing step according to a method for forming a metal contact at a metal / semiconductor interface according to a first embodiment of the present invention;
FIG. 1b is a cross-sectional view showing a step subsequent to the step shown in FIG. 1a.
1c is a cross-sectional view showing a step subsequent to the step shown in FIG. 1b.
FIG. 2a is a diagram showing a part of a manufacturing step of a DRAM by a mixed contact method according to a second embodiment of the present invention;
2b is a cross-sectional view showing a step subsequent to the step shown in FIG. 2a.
2c is a cross-sectional view illustrating a step subsequent to the step illustrated in FIG. 2b.
2d is a cross-sectional view illustrating a step subsequent to the step illustrated in FIG. 2c.
2e is a cross-sectional view illustrating a step subsequent to the step illustrated in FIG. 2d.
2f is a cross-sectional view illustrating a step subsequent to the step illustrated in FIG. 2e.
FIG. 2g is a cross-sectional view showing a step that follows the step shown in FIG. 2f.
[Explanation of symbols]
10, 100 Semiconductor substrate 12 N well 14, 16 P well 20, 120 Dielectric layer 30 n-doped Si _x Ge _l-x layer (0 <x <l)
40 Photoresist layer 50, 220 Cobalt layer 52, 240 Cobalt silicide layer 60, 400 Metal plug 200 Si _x Ge _l-x layer 300 Diffusion region A Array region C1, C2, C3 Contact hole S Peripheral circuit region

Claims (10)

A method of forming a metal contact in a storage device, comprising:
A peripheral circuit region having a first FET of a first conductivity type and a second FET of a second conductivity type; and an array region having a third FET of a second conductivity type, the first, The second and third FETs each provide a semiconductor substrate including first, second and third source / drain regions;
Forming a dielectric layer in the semiconductor substrate;
Forming first, second and third contact holes in the dielectric layer penetrating to the first, second and third source / drain regions, respectively;
Forming a second conductivity type doped Si _x Ge _{l -x} layer (0 <x <l) in the first, second and third contact holes;
Masking the second and third contact holes;
Removing the doped Si _x Ge _{l- x} layer in the first contact hole;
Implanting a first conductivity type impurity in the first source / drain region;
Adaptively forming a cobalt layer in the semiconductor substrate;
Forming a cobalt silicide layer from the cobalt layer by a chemical reaction between the cobalt layer and the Si _x Ge _{1 -x} layers in the second and third contact holes;
Diffusing impurities in the Si _x Ge _{1 -x} layer in the second and third contact holes into the second and third source / drain regions;
Filling the first, second and third contact holes with metal plugs;
Prepare for the order,
Metal contact formation method. The first and second conductivity types are p-type and n-type, respectively.
The method for forming a metal contact according to claim 1 . In the step of implanting the first conductivity type impurity into the first source / drain region, the first conductivity type impurity is boron.
The method for forming a metal contact according to claim 1 . An energy lower than 2 KeV and a dose lower than 1 × 10 ¹⁵ atoms / cm ² are used to inject the impurities.
The metal contact formation method according to claim 3 . A PLAD method is used to inject the impurities,
The metal contact formation method of Claim 4 . PIII method is used to implant the impurities,
The metal contact formation method of Claim 4 . The Si _x Ge _{l -x} layer is an n-doped Si _x Ge _{l -x} layer;
The method for forming a metal contact according to claim 1 . The Si _x Ge _{l -x} layer is formed by selective epitaxy growth.
The method for forming a metal contact according to claim 7 . The metal plug is a tungsten plug formed by a selective growth method.
The method for forming a metal contact according to claim 1 . A method of forming a metal contact in a DRAM comprising:
a peripheral circuit region having a p-type first FET and an n-type second FET; and an array region having an n-type third FET, wherein the first, second and third FETs are respectively Providing a semiconductor substrate including first, second and third source / drain regions;
Forming a dielectric layer in the semiconductor substrate;
Forming first, second and third contact holes in the dielectric layer penetrating to the first, second and third source / drain regions, respectively;
Forming an n-doped Si _x Ge _{l -x} layer (0 <x <l) in the first, second and third contact holes;
Masking the second and third contact holes;
Removing the n-doped Si _x Ge _{l -x} layer in the first contact hole;
Implanting p-type impurities in the first source / drain region;
Adaptively forming a cobalt layer in the semiconductor substrate;
Forming a cobalt silicide layer from the cobalt layer by a chemical reaction between the cobalt layer and the n-doped Si _x Ge _{l -x} layers in the second and third contact holes;
Diffusing impurities in the n-doped Si _x Ge _{l -x} layer in the second and third contact holes into the second and third source / drain regions;
Filling the first, second and third contact holes with metal plugs;
Prepare for the order,
Metal contact formation method.

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