JP4147861B2 - Manufacturing method of solid-state imaging device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a method for manufacturing a solid-state imaging device in which an imaging device unit and a peripheral circuit unit are provided on a semiconductor chip.
[0002]
[Prior art]
Conventionally, in a pixel cell of a solid-state imaging device typified by a CMOS image sensor, wiring is usually formed using a technique similar to that used in the peripheral circuit section.
In the wiring process of the peripheral circuit portion, a chemical mechanical planarization method (CMP method) is usually used in order to realize the flatness necessary for miniaturizing the wiring and the via contact. However, in the CMP method, the flatness before flattening greatly affects the flatness after CMP.
Therefore, as a method for obtaining higher-precision flatness, dummy wiring that is not actually used for electrical connection may be provided as wiring in order to achieve good flatness to some extent before flattening by CMP. In some cases, a wide wiring is divided into stripes (for example, see Japanese Patent No. 3229278, Japanese Patent Laid-Open No. 2000-68277, etc.).
[0003]
Hereinafter, such a conventional method will be specifically described by taking a wiring forming process using copper wiring as an example.
FIG. 6 is a cross-sectional view showing each step of the damascene method that is normally used for forming copper wiring.
First, in FIG. 6A, wiring patterns 2 and 3 using trenches are formed in the insulating film 1. Thereafter, a copper barrier metal layer 5 is formed on the insulating film 1 and in the trench pattern 2. In general, tantalum (Ta), tantalum nitride (TaN), tungsten nitride (WN), or the like is formed as a copper barrier metal by sputtering.
Thereafter, copper 6 serving as a wiring material is formed to obtain a structure shown in FIG. The copper 6 is usually formed by plating after a copper seed layer is formed by sputtering.
[0004]
Next, planarization is performed using a CMP method. FIG. 6B shows a state in which copper is planarized by the CMP method.
In this example, copper is not completely removed in the wide insulating film region 4, and a state 8 in which a part of copper remains is shown. On the other hand, the wide wiring region 3 shows a state in which a recess (so-called dishing) 9 is generated on the upper surface of copper.
Thereafter, the barrier metal 5 is removed by a CMP method.
FIG. 6C shows a state 7 in which the barrier metal also remains in the region 8 where copper remains after the CMP of the barrier metal.
[0005]
As shown in the above example, problems such as the wiring material remaining after wiring formation or dishing occur due to the layout of the wiring layer, the wiring width, and the like.
Therefore, several methods for solving such problems have been proposed.
Next, an example will be described with reference to FIG.
FIG. 7A is formed by the same process as in FIG. However, in FIG. 7A, wirings that are not used for electrical connection, so-called dummy wirings 10, and insulating film regions 11 that divide wide wirings are formed in the wiring pattern.
7A. Since the flatness of copper, which is a wiring material, is significantly different from that in FIG. 6A by using the method of FIG. 7A, FIG. 7B shows the result after planarization by the CMP method. As described above, the problems of the remaining wiring material and dishing described above are solved.
[0006]
In addition, when a wiring is formed by etching a wiring material such as Al wiring which has been conventionally used without using the damascene method as described above, a method of flattening an interlayer insulating film by a CMP method (so-called etching) Method) is widely used.
In this case, dummy wiring is widely used for the purpose of improving the flatness after the interlayer insulating film is formed. FIG. 8 shows a specific example thereof. As shown in the figure, a relatively narrow wiring 13 and a relatively wide wiring 14 are arranged on the insulating film 12, and by providing a dummy wiring 15 between them, an interlayer formed on the upper layer is provided. The flatness of the insulating film 16 is ensured.
As a method for forming such a dummy wiring, a method of automatically laying out a wiring used for electrical connection and then placing it under a certain rule is used.
[0007]
[Problems to be solved by the invention]
However, even when the wiring is formed by the damascene method described above or when the wiring is formed by the etching method, when used for a solid-state imaging device, the reduction in the element formation space or the level difference caused by the lamination of the dummy wirings. In particular, there is a problem that light to the light receiving portion formed in the substrate in the image pickup device portion is significantly reduced by the dummy wiring that is a light-shielding metal film.
In particular, in the configuration using copper wiring in the wiring layer, in order to prevent the copper film remaining in the peripheral circuit portion, it is necessary to form dummy wiring on the imaging pixel portion at the wiring forming stage, and the pattern of the dummy wiring is increased. Therefore, the existence of such dummy wirings may be a major factor that degrades the characteristics of the solid-state imaging device.
[0008]
In view of such a situation, the present invention provides a configuration in which an imaging element unit having a plurality of light receiving units arranged on the same semiconductor substrate and a peripheral circuit unit thereof are configured to prevent planarization and remaining wiring material. and to provide a method for manufacturing a solid-state imaging device capable of suppressing a reduction in light-receiving efficiency and sensitivity of the imaging device section by the dummy wiring.
[0009]
[Means for Solving the Problems]
In order to achieve the above object, the present invention is configured by arranging a plurality of unit pixels close to each other, and is arranged in a peripheral region on the same chip as the image sensor unit, which outputs an image signal from the unit pixel. a solid-state imaging to chromatic and the peripheral circuit section, a plurality of layers formed in the upper region spanning the imaging element part and the peripheral circuit portion and a wiring layer including a signal processing circuit of the driver circuit and the imaging signal of the imaging element unit A method for manufacturing an element, comprising: a first step of forming an upper layer wiring including a dummy wiring and an interlayer insulating film in an upper layer region extending over the peripheral circuit unit and the image sensor unit; and an interlayer insulating film on the image sensor unit; And a second step of removing the dummy wiring .
[0010]
In the solid-state imaging device manufacturing method of the present invention, after forming the upper layer wiring and the interlayer insulating film including the dummy wiring in the upper layer region extending from the peripheral circuit portion and the imaging device portion, the interlayer insulating film and the dummy wiring on the imaging device portion are formed. By removing the light, the dummy wiring on the imaging element unit does not hinder the incidence of light to the light receiving unit of the imaging element unit, and the light receiving efficiency and sensitivity of the imaging element unit due to the dummy wiring can be suppressed. it can. In addition, since the dummy wiring can be formed on the image sensor section at the stage of manufacturing the upper layer wiring in the peripheral circuit section, it is possible to obtain effective flatness from the peripheral circuit section to the image sensor section. Problems such as material residue can be effectively prevented, and a solid-state imaging device with excellent characteristics can be formed.
[0011]
DETAILED DESCRIPTION OF THE INVENTION
The following describes embodiments of implementation of the method for manufacturing a solid-state imaging device according to the present invention.
FIG. 1 is a sectional view showing a first embodiment of the present invention.
The solid-state image sensor of this example is formed as a CMOS image sensor, for example, and is obtained by forming an image sensor section 129 shown on the left side of FIG. 1 and a peripheral circuit section 130 shown on the left side on the same semiconductor chip.
The imaging element unit 129 is a unit in which a plurality of unit pixels are arranged in a two-dimensional array in the semiconductor substrate 100. The incident light quantity is detected by the photoelectric conversion unit 118 provided for each unit pixel, and is output as a pixel signal. Is.
A plurality of layers (three layers in the illustrated example) of wirings 120, 122, and 124 are formed on the upper layer of the imaging element portion 129 via interlayer insulating films 119, 121, 123, 125, and 127. These wirings 120, 122, and 124 are arranged so as to avoid the light receiving path of each photoelectric conversion unit 118. In this example, copper wiring using the damascene method described above is used.
[0012]
Further, the peripheral circuit unit 130 is provided with a drive circuit for driving each unit pixel of the image sensor unit 129, a signal processing circuit for processing an image signal output from the image sensor unit 129, and the like.
A plurality of layers (four layers in the illustrated example) of wirings 120, 122, 124, 126 are also formed on the peripheral circuit portion 130 via interlayer insulating films 119, 121, 123, 125, 127. Yes. That is, the lower three-layer wirings 120, 122, and 124 are common to the peripheral circuit unit 130 and the imaging element unit 129, and the uppermost layer wiring 126 is formed only in the peripheral circuit unit 130. It is not formed in the element portion 129.
The uppermost wiring 126 includes, for example, a dummy wiring for flattening. In particular, when a copper wiring is used, a dummy wiring is also formed on the image pickup element portion 129 due to manufacturing restrictions. There is a need to.
However, as shown in FIG. 3, if the dummy wiring 126A is provided in the uppermost layer of the image sensor section 129, the light receiving path to the photoelectric conversion unit 118 is blocked by the dummy wiring 126A, and the light receiving efficiency is reduced. Will be invited.
Therefore, in the example illustrated in FIG. 1, the dummy wiring 126 </ b> A is removed from the uppermost layer of the imaging element unit 129.
[0013]
In particular, when copper wiring is used, it may be necessary to set a dummy wiring on the image pickup element portion 129 and form a wiring pattern in order to properly form the wiring on the peripheral circuit portion 130 side. .
Therefore, in this example, as will be described later in the manufacturing method, in the uppermost wiring formation step, the dummy wiring 126A and the upper interlayer insulating film 127 are also formed on the upper layer of the image pickup device portion 129. By removing the dummy wiring 126A and the upper interlayer insulating film 127, a layer structure in which no dummy wiring exists in the upper layer of the imaging element portion 129 is obtained. The removal of the dummy wiring 126A and the interlayer insulating film 127 is performed by combining various types of etching, but either isotropic etching or anisotropic etching may be used. Further, as a method for removing the copper wiring, the copper film may be removed by forming an opening and performing liquid chemical etching.
[0014]
The state shown in FIG. 1 is a state in which, after removing the dummy wiring 126A and the interlayer insulating film 127 on the imaging element portion 129, a planarizing film is entirely laminated, and the upper surface thereof is planarized by CMP or the like. .
In such a method, a step is actually generated between the peripheral circuit unit 130 and the image pickup device unit 129, but it is only necessary to have a step within an allowable range due to characteristics.
In addition, when it is desired to eliminate the step between the peripheral circuit unit 130 and the image sensor unit 129, the portion from which the dummy wiring 126A and the interlayer insulating film 127 on the image sensor unit 129 are removed is filled with a partial planarization film. Then, a method of laminating and planarizing the entire planarization film can also be adopted.
[0015]
FIG. 2 is a sectional view showing a second embodiment of the present invention. In addition, the same code | symbol is used about the same structure as FIG.
The solid-state imaging device of this example is provided with a dummy wiring 126B in the uppermost layer of the imaging device unit 129. The difference from the example of FIG. 3 is that the dummy wiring 126B is connected to the lower wirings 120, 122, and 124. The pattern is the same.
As a result, the amount of incident light blocked by the dummy wiring 126B is minimized, and good light receiving efficiency in the photoelectric conversion unit 118 is ensured.
In particular, when the number of wiring layers in the peripheral circuit unit 130 is larger than the number of wiring layers in the imaging element unit 129, there are cases where it is necessary to provide dummy wiring on the imaging element unit 129. Therefore, even in such a case, it is possible to minimize the light loss due to the dummy wiring by making the dummy wiring 126B substantially the same pattern as the lower wirings 120, 122, 124 as in this example. It becomes.
[0016]
Others are the same as the example shown in FIG.
Further, in this example, the dummy wiring 126B has almost the same pattern as the lower layer wirings 120, 122, and 124. However, if the dummy wiring has a pattern that does not affect the incident efficiency of the photoelectric conversion unit, the lower layer wiring is forcibly reduced. It is not necessary to match the wiring pattern, and it is needless to say that the pattern can be formed so that the effect of the dummy wiring can be maximized within a range that does not affect the incident efficiency.
[0017]
3 and 4 are sectional views showing a third embodiment of the present invention. In addition, the same code | symbol is used about the same structure as FIG.1 and FIG.2.
This third embodiment particularly corresponds to a manufacturing method for manufacturing the solid-state imaging device of the first embodiment shown in FIG.
First, in FIG. 3, the wiring layers 120, 122, 124, and 126 and the interlayer insulating films 119, 121, 123, 125, and 127 of the peripheral circuit unit 130 and the image pickup device unit 129 are sequentially formed in the same process. The stage in which the dummy wiring 126A is also formed in the uppermost layer of the imaging element portion 129 is shown. In this state, as described in the first embodiment, the incident light in the image sensor section 129 is hindered by the dummy wiring 126A.
[0018]
Therefore, as shown in FIG. 4, the uppermost interlayer insulating film 127 of the image pickup element portion 129 is removed by etching or the like (recessed portion 128), and the dummy wiring 126A is further removed.
Thereby, the upper layer dummy wiring 126 </ b> A of the imaging element unit 129 can be eliminated, and a layer structure in which the incident efficiency with respect to each photoelectric conversion unit 118 is improved can be obtained.
In the state shown in FIG. 4, when the dummy wiring 126A is removed, an uneven shape corresponding to the pattern of the dummy wiring 126A remains in that portion, and the uppermost interlayer insulating film 127 as the entire image pickup device portion 129 also remains. However, as long as these shapes do not affect the characteristics of the image sensor, the entire planarization film may be laminated and planarized as it is.
[0019]
Further, when unevenness becomes a problem, for example, the portion from which the dummy wiring 126A is removed is further flattened by etching or the like, and a filler is injected thereon to align the height with the peripheral circuit portion 130. Flattening may be performed. In this way, the arrangement of the on-chip color filter and the on-chip microlens arranged on the chip is also improved, and it is possible to easily cope with the high accuracy of the solid-state imaging device.
In this example, the case of removing one layer of dummy wiring has been described, but a plurality of layers of dummy wiring may be removed as necessary.
[0020]
FIG. 5 is a plan view showing an example of a dummy wiring pattern in the fourth embodiment of the present invention.
As an example of the dummy wiring pattern, as shown in FIG. 5, there is a method of forming the insulating film pattern 141 in the wiring 140 arranged in the entire image pickup device portion. This is a method used for the purpose of reducing the difference in wiring occupancy between the peripheral circuit section and the image sensor section and ensuring better flatness.
Therefore, similar to the embodiment described above, the dummy wiring is also removed for such a dummy wiring pattern. In this case, a small opening is formed in a part of the dummy wiring, By injecting the liquid chemical, the copper wiring can be etched away isotropically.
When such a method is used, an opening necessary for etching can be reduced, and there is an advantage that a problem that a step is generated between the imaging element portion and the peripheral circuit portion can be solved.
[0021]
In each of the above-described embodiments, the case where the present invention is formed using the damascene method typified by copper wiring has been described. However, the present invention is formed using an etching method typified by aluminum wiring. The same can be applied to the wiring.
Further, in each of the above-described embodiments, the case where the present invention is applied to a CMOS image sensor has been described. However, various types of solid-state devices in which an imaging element unit having a photoelectric conversion unit and a peripheral circuit unit are mounted on the same chip. it is capable widely applied to the manufacturing method of the imaging device.
[0022]
【The invention's effect】
As described above , according to the method for manufacturing a solid-state imaging device of the present invention, after forming the upper layer wiring including the dummy wiring and the interlayer insulating film in the upper layer region extending over the peripheral circuit portion and the imaging device portion, By removing the interlayer insulating film and the dummy wiring, the dummy wiring on the imaging element unit does not hinder the incidence of light to the light receiving part of the imaging element unit, and the light receiving efficiency and sensitivity of the imaging element unit by the dummy wiring are eliminated. There is an effect that can suppress the decrease of.
According to the method for manufacturing a solid-state imaging device of the present invention, dummy wiring can also be formed on the imaging device portion at the stage of manufacturing the upper layer wiring in the peripheral circuit portion, so that an effective flatness from the peripheral circuit portion to the imaging device portion can be achieved. Therefore, it is possible to effectively prevent problems such as remaining wiring material in the peripheral circuit portion, and to form a solid-state imaging device having excellent characteristics.
[Brief description of the drawings]
FIG. 1 is a cross-sectional view showing a solid-state imaging device according to a first embodiment of the present invention.
FIG. 2 is a cross-sectional view showing a solid-state imaging device according to a second embodiment of the present invention.
FIG. 3 is a cross-sectional view showing a manufacturing process of a solid-state imaging device according to a third embodiment of the present invention.
FIG. 4 is a cross-sectional view showing a manufacturing process of a solid-state imaging device according to a third embodiment of the present invention.
FIG. 5 is a plan view showing a dummy wiring pattern example in a fourth embodiment of the present invention;
FIG. 6 is a cross-sectional view showing a first example of a manufacturing process of a conventional solid-state imaging device.
FIG. 7 is a cross-sectional view showing a second example of a manufacturing process of a conventional solid-state imaging device.
FIG. 8 is a cross-sectional view showing an example of conventional dummy wiring.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 100 ... Semiconductor substrate, 118 ... Photoelectric conversion part, 119, 121, 123, 125, 127 ... Interlayer insulation film, 120, 122, 124, 126 ... Wiring, 126A, 126B ... Dummy wiring, 129 ... Image sensor unit, 130... Peripheral circuit unit.

Claims (5)

An image sensor unit that is configured by arranging a plurality of unit pixels close to each other, outputs an image pickup signal from the unit pixel, and is disposed in a peripheral area on the same chip as the image sensor unit, and the drive circuit of the image sensor unit and the A manufacturing method of a solid-state imaging device having a peripheral circuit unit including a signal processing circuit for an imaging signal, and a plurality of wiring layers formed in an upper layer region extending over the imaging device unit and the peripheral circuit unit,
A first step of forming an upper layer wiring including a dummy wiring and an interlayer insulating film in an upper layer region extending from the peripheral circuit unit and the image sensor unit;
A second step of removing the interlayer insulating film and the dummy wiring on the image sensor unit;
A method for manufacturing a solid-state imaging device, comprising: In the first step, a method for manufacturing a solid-state imaging device according to claim 1, wherein the forming the wiring layer by copper wiring. 3. The method of manufacturing a solid-state imaging device according to claim 2, wherein in the first step, copper wiring is formed by a damascene method. In the second step, the manufacturing method of the solid-state imaging device according to claim 2, wherein the removing the dummy wiring by a liquid drug etching. After removal of the interlayer insulating film and the dummy wiring on the image pickup device unit, according to claim 1, characterized in that it comprises a third step of forming a planarizing film in the region over the peripheral circuit portion and the image pickup device unit Manufacturing method of solid-state image sensor.

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