JP4146170B2 - Magnetic random access memory - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
  The present invention provides a magnetoresistive effect.UseThe present invention relates to a magnetic random access memory (MRAM).
[0002]
[Prior art]
  In recent years, many memories for storing data based on a new principle have been proposed. One of them is a tunneling magnetoresistive effect (hereinafter referred to as TMR).UseThere is a magnetic random access memory.
[0003]
As a proposal of magnetic random access memory, for example, ISSCC2000 Technical Digest p.128 `` A 10ns Read and Write Non-Volatile Memory Array Using a Magnetic Tunnel Junction and FET Switch in each Cell '' by Roy Scheuerlein et.al is known. ing.
[0004]
The magnetic random access memory stores “1”, “0” -data by the TMR element. The basic structure of a TMR element is a structure in which an insulating layer (tunnel barrier) is sandwiched between two magnetic layers (ferromagnetic layers). However, as for the structure of the TMR element, various structures have been proposed for the purpose of optimizing the MR (Magneto Resistive) ratio (for example, regarding the MR ratio and the structure of the TMR element, see Japanese Patent Application No. 2000-296082, (See Japanese Patent Application No. 2001-37140).
[0005]
The data stored in the TMR element is determined by whether the magnetization states of the two magnetic layers are parallel or antiparallel. Here, “parallel” means that the magnetization directions of the two magnetic layers are the same, and “anti-parallel” means that the magnetization directions of the two magnetic layers are opposite.
[0006]
Usually, one of the two magnetic layers (pinned layer) is provided with an antiferromagnetic layer. The antiferromagnetic layer is a member for fixing the magnetization direction of the fixed layer. Therefore, actually, data (“1” or “0”) stored in the TMR element is determined by the magnetization direction of the other one (free layer) of the two magnetic layers.
[0007]
When the magnetization state of the TMR element is parallel, the tunnel resistance of the insulating layer (tunnel barrier) sandwiched between the two magnetic layers constituting the TMR element is the lowest. For example, this state is set to “1” -state. Further, when the magnetization state of the TMR element becomes antiparallel, the tunnel resistance of the insulating layer (tunnel barrier) sandwiched between two magnetic layers constituting the TMR element becomes the highest. For example, this state is set to “0” -state.
[0008]
[Problems to be solved by the invention]
Regarding the cell array structure of the magnetic random access memory, various structures are currently being studied from the viewpoint of increasing the memory capacity and stabilizing the write / read operation.
[0009]
For example, at present, a cell array structure in which one memory cell includes one MOS transistor and one TMR element (or MTJ (Magnetic Tunnel Junction) element) is known. A magnetic random access memory having such a cell array structure for storing 1-bit data using two memory cell arrays is also known in order to realize a stable read operation.
[0010]
However, it is difficult to increase the memory capacity in these magnetic random access memories. This is because, in these cell array structures, one MOS transistor corresponds to one TMR element.
[0011]
For example, Japanese Patent Application No. 2000-296082 proposes an array structure in which a plurality of TMR elements are connected in parallel. According to this cell array structure, since one MOS transistor corresponds to a plurality of TMR elements, the memory capacity is larger than that of a cell array structure in which one memory cell is composed of one TMR element and one MOS transistor. Can be increased.
[0012]
However, even in the technique disclosed in Japanese Patent Application No. 2000-296082, the TMR elements are two-dimensionally arranged in one plane, so that the TMR elements cannot be sufficiently integrated at a high density.
[0013]
An object of the present invention is to propose a magnetic random access memory having a novel cell array structure suitable for increasing the memory capacity and a manufacturing method thereof, and to propose a novel read operation principle suitable for the novel cell array structure, Another object is to propose a read circuit for realizing the novel read operation principle.
[0014]
[Means for Solving the Problems]
  The magnetic random access memory of the present invention is stacked on a semiconductor substrate and is connected in series with a magnetoresistive effectUseA plurality of memory cells, and a plurality of memory cellsAll furtheraboveArrangementAnd connected to one end of the plurality of memory cells.readingA bit line;readingA read circuit connected to a bit line and used to write data to one of the plurality of memory cells;A plurality of write word lines extending in the X direction and stacked in the Z direction perpendicular to the X directionAnd used to write data to one of the plurality of memory cells,A write bit line that intersects the X direction and extends in the Y direction perpendicular to the X direction and the Z directionWith.Each of the plurality of memory cells is sandwiched between an upper electrode and a lower electrode, and the plurality of memory cells are connected in series with each other by a contact plug that contacts the upper electrode or the lower electrode. The write word line is disposed above or below the memory cell, and the write bit line is disposed below or above the memory cell opposite to the side on which the write word line is disposed. The write word line and the write bit line disposed between the memory cells are shared by the memory cells disposed above and below the write word line and the write bit line.
[0016]
  The magnetic random access memory of the present invention is stacked on a semiconductor substrate, and is configured by a combination of series connection and parallel connection.UseA plurality of memory cells, and a plurality of memory cellsAll furtheraboveArrangementAnd connected to one end of the plurality of memory cells.readingA bit line and saidreadingA read circuit connected to a bit line and used to write data to one of the plurality of memory cells;A plurality of write word lines extending in the X direction and stacked in the Z direction perpendicular to the X directionAnd used to write data to one of the plurality of memory cells,A write bit line that intersects the X direction and extends in the Y direction perpendicular to the X direction and the Z directionWith.Each of the plurality of memory cells is sandwiched between an upper electrode and a lower electrode, and the plurality of memory cells are connected to each other by a combination of series connection and parallel connection by contact plugs that contact the upper electrode or the lower electrode. The The write word line is disposed above or below the memory cell, and the write bit line is disposed below or above the memory cell opposite to the side on which the write word line is disposed. The write word line and the write bit line disposed between the memory cells are shared by the memory cells disposed above and below the write word line and the write bit line.
[0045]
  The manufacturing method of the magnetic random access memory of the present invention is as follows:A plurality of memory cells that are stacked on a semiconductor substrate and that use the magnetoresistive effect connected in series, and are arranged above all of the plurality of memory cells and connected to one end of the plurality of memory cells. A read bit line, a read circuit connected to the read bit line, and used to write data to one of the plurality of memory cells, extend in the X direction, and extend in the Z direction perpendicular to the X direction. A plurality of write word lines stacked and a write used to write data to one of the plurality of memory cells, intersecting the X direction and extending in the Y direction perpendicular to the X direction and the Z direction Each of the plurality of memory cells is sandwiched between an upper electrode and a lower electrode, and the plurality of memory cells are contoured to the upper electrode or the lower electrode. Connected to each other in series by contact plugs, the write word lines are arranged at the top or bottom of the memory cell, and the write bit lines are opposite to the side on which the write word lines are arranged, A magnetic random access memory that is disposed below or above the memory cell and is shared by the memory cells disposed above and below the write word line and the write bit line disposed between the memory cells. Applies to The manufacturing method is as described above.Forming a read selection switch on a surface region of the semiconductor substrate; and on the read selection switchFirst write word lines extending in the X direction and stacked in the Z directionForming the step, andFirst write word lineDirectly aboveFirst memory cellForming the step, andFirst memory cellDirectly aboveIntersects the X direction and the Y directionExtend toFirst write bit lineForming the step, andFirst write bit lineDirectly aboveFirst write bit lineAgainstFirst memory cellSymmetric withSecond memory cellForming the step, andSecond memory cellDirectly aboveSecond write word line extending in the X direction and stacked in the Z directionForming the step, andSecond write word lineDirectly aboveSecond write word lineAgainstSecond memory cellSymmetric withThird memory cellForming the step, andThird memory cellDirectly aboveCross in the X direction and in the Y directionExtendSecond write bit lineForming the step, andSecond write bit lineDirectly aboveSecond write bit lineAgainstThird memory cellSymmetric withFourth memory cellForming the step, andFourth memory cellDirectly aboveThird write word line extending in the X direction and stacked in the Z directionForming the step, andThird write word lineabove,Intersects the X direction and the Y directionForming the read bit line extending in the step.
[0046]
  A method of manufacturing a magnetic random access memory according to the present invention includes a plurality of memory cells stacked on a semiconductor substrate and using a magnetoresistive effect configured by a combination of series connection and parallel connection, and the plurality of memory cells. Data is written to one of the plurality of memory cells, a read bit line that is arranged further above and connected to one end of the plurality of memory cells, a read circuit connected to the read bit line, and one of the plurality of memory cells. A plurality of write word lines extending in the X direction and stacked in a Z direction perpendicular to the X direction; and used to write data to one of the plurality of memory cells, the X direction And a write bit line extending in the Y direction perpendicular to the X direction and the Z direction, and each of the plurality of memory cells includes an upper electrode The plurality of memory cells sandwiched between lower electrodes are connected to each other by a combination of series connection and parallel connection by contact plugs that contact the upper electrode or the lower electrode, and the write word line is connected to the upper part of the memory cell. Alternatively, the write bit line is disposed below or above the memory cell on the opposite side of the write word line and disposed between the memory cells. The word line and the write bit line are applied to a magnetic random access memory shared by the memory cells disposed above and below the word line and the write bit line. The manufacturing method includes a step of forming a read selection switch in a surface region of the semiconductor substrate, and a step of forming a first write word line extending in the X direction and stacked in the Z direction on the read selection switch. Forming a first memory cell directly above the first write word line; and a first write bit extending directly in the X direction and extending in the Y direction immediately above the first memory cell. Forming a line; forming a second memory cell directly above the first write bit line and symmetric with the first memory cell with respect to the first write bit line; Forming a second write word line extending in the X direction and stacked in the Z direction immediately above the second memory cell; and the second write word Forming a third memory cell that is symmetrical to the second memory cell with respect to the second write word line directly above the line; and in the X direction directly above the third memory cell. Forming a second write bit line that intersects and extends in the Y direction; and symmetrically with the third memory cell with respect to the second write bit line immediately above the second write bit line Forming a fourth memory cell; forming a third write word line extending directly in the X direction and stacked in the Z direction immediately above the fourth memory cell; and Forming on the write word line the read bit line that intersects the X direction and extends in the Y direction.
[0052]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, the magnetic random access memory of the present invention will be described in detail with reference to the drawings.
[0053]
1. Overview
The first feature of the magnetic random access memory of the present invention is the cell array structure of the memory cell array.
[0054]
As a structure for achieving high integration of memory cells of the magnetic random access memory, for example, there are memory cell array structures disclosed in Japanese Patent Application Nos. 2001-350013 and 2001-365236.
[0055]
The present invention proposes a memory cell array structure obtained by modifying the memory cell array structure disclosed in these documents. That is, in the magnetic random access memory of the present invention, a read block is constituted by a plurality of TMR elements (or MTJ elements), and the read block is connected between the read bit line and the source line.
[0056]
The second feature of the magnetic random access memory of the present invention is the read operation principle.
[0057]
When the cell array structure related to the first feature described above is adopted, it is necessary to devise the read operation principle.
[0058]
The read operation principle is disclosed in detail in Japanese Patent Application No. 2000-296082, Japanese Patent Application No. 2001-350013, Japanese Patent Application No. 2001-365236, and the like. In the present application, the case where these read operation principles are applied to the memory cell array structure which is the first feature of the present invention will be described.
[0059]
The third feature of the magnetic random access memory of the present invention is the structure of the TMR element.
[0060]
When applying the new read operation principle related to the second feature described above, the structure of the plurality of TMR elements in the read block may have to be devised. Therefore, in the present invention, the structure of the TMR element when the memory cell array structure which is the second feature of the present invention is adopted will be described.
[0061]
The fourth feature of the magnetic random access memory of the present invention is the configuration of the read circuit.
[0062]
In the present invention, a novel read circuit is required to execute the read operation principle realized by the second and third features described above. Therefore, a specific example of the read circuit of the magnetic random access memory of the present invention is proposed.
[0063]
A fifth feature of the magnetic random access memory of the present invention is a method for manufacturing the magnetic random access memory.
[0064]
In the present invention, a novel reading method is required to realize the cell array structure related to the first feature described above. Therefore, the present invention proposes a manufacturing method for realizing the memory cell array structure related to the first feature described above.
[0065]
2. Cell array structure
First, the cell array structure of the magnetic random access memory of the present invention will be described. The cell array structure according to the present invention is characterized in that a plurality of TMR elements (or MTJ elements) are stacked in a plurality of stages in a direction (longitudinal direction) perpendicular to the surface of the semiconductor substrate. That is, in the cell array structure of the present invention, the plurality of TMR elements are three-dimensionally arranged on the semiconductor substrate.
[0066]
The plurality of TMR elements stacked in a plurality of stages are connected in series, in parallel, or a combination thereof (series-parallel) between the read bit line and the source line.
[0067]
With such a cell array structure, the TMR elements are three-dimensionally arranged on the semiconductor substrate, and one MOS transistor (read selection switch) may be associated with the plurality of TMR elements. This can contribute to an increase in memory capacity.
[0068]
(1) Structural example 1
Structural example 1 relates to a cell array structure in which a plurality of TMR elements stacked in a plurality of stages are connected in series.
[0069]
(1) Circuit structure
First, the circuit structure will be described.
FIG. 1 shows a main part of a magnetic random access memory as Structural Example 1 of the present invention.
[0070]
The memory cell array 11 includes a plurality of TMR elements 12 arranged in an array in the X direction, the Y direction, and the Z direction. Here, the Z direction means a direction perpendicular to the paper surface orthogonal to the X direction and the Y direction.
[0071]
In this example, the memory cell array 11 includes j + 1 TMR elements 12 arranged in the X direction, n + 1 TMR elements 12 arranged in the Y direction, and four TMR elements 12 stacked in the Z direction. The cell array structure is as follows. Although the number of TMR elements 12 stacked in the Z direction is four in this example, the number may be any number as long as it is plural.
[0072]
The four TMR elements 12 stacked in the Z direction are connected in series to each other to form one block BKik (i = 0, 1,... J, k = 0, 1,... N). Yes. The four TMR elements 12 in the block BKik actually overlap each other in the direction (Z direction) perpendicular to the paper surface.
[0073]
One ends of the four TMR elements 12 in the block BKik are connected to a ground point via a read selection switch (MOS transistor) RSW.
[0074]
In this example, one row is composed of j + 1 blocks BKik arranged in the X direction. The memory cell array 11 has n + 1 rows. Further, one column is constituted by n + 1 blocks BKik arranged in the Y direction. The memory cell array 11 has j + 1 columns.
[0075]
Near the four TMR elements 12 constituting the block BKik, a plurality (three in this example) of write word lines WWL3n, WWL3n + 1, and WWL3n + 2 extending in the X direction and stacked in the Z direction are arranged. Here, n is a row number, and n = 0, 1, 2,.
[0076]
With respect to the write word line extending in the X direction, for example, as shown in FIG. 217, one write word line can be arranged in one stage in one row. In this case, the number of write word lines in one row extending in the X direction is four (WWL4n, WWL4n + 1, WWL4n + 2, WWL4n + 3), that is, the number of stages where the TMR elements 12 are stacked.
[0077]
As for the write bit line extending in the Y direction, for example, as shown in FIG. 217, one write bit line can be arranged in one stage in one column. In this case, the number of write bit lines in one column extending in the Y direction is four (BLj0, BLj1, BLj2, BLj3), that is, the same as the number of stages where the TMR elements 12 are stacked.
[0078]
However, in this example, at least one write word line in one row extending in the X direction is shared by two TMR elements (upper TMR element and lower TMR element). Specifically, in this example, the write word line WWL3n + 1 is shared by the second and third TMR elements. In this case, the number of write word lines in one row extending in the X direction is reduced, and planarization of the insulating film immediately below the TMR element 12 and reduction in manufacturing cost can be realized.
[0079]
Considering the block structure, for example, as shown in FIG. 218, one write word line is shared by the first and second TMR elements, and one write word line is written by the third and fourth TMR elements. Word lines can also be shared. In this case, the number of write word lines in one row extending in the X direction can be two (WWL2n, WWL2n + 1).
[0080]
Nevertheless, in this example, the number of write word lines in one row extending in the X direction is set to three because the positions of the write bit lines in one column extending in the Y direction are taken into consideration.
[0081]
That is, in this example, one write bit line BLj0 extending in the Y direction is arranged between the first stage TMR element 12 and the second stage TMR element 12, and the third stage TMR element 12 and the fourth stage TMR element 12 are connected. One write bit line BLj1 extending in the Y direction is arranged between the TMR elements 12.
[0082]
As a result, with respect to the write bit lines in one column extending in the Y direction, one write bit line is shared by the first and second TMR elements, and one write bit line is shared by the third and fourth TMR elements. Write bit lines are shared. In this case, the number of write bit lines in one column extending in the Y direction is two.
[0083]
In FIG. 1, the two write bit lines BLj0 and BLj1 are drawn so as to sandwich the four TMR elements 12 in the block BKjn because the TMR element 12 cannot be drawn in three dimensions. As described above, one write bit line BLj0 is disposed between the first stage TMR element and the second stage TMR element, and one line is provided between the third stage TMR element and the fourth stage TMR element. Write word line BLj1 is arranged.
[0084]
The specific structure of the TMR element in the block and its vicinity will be clarified in the description of the device structure described later.
[0085]
One end of the write word lines WWL3n, WWL3n + 1, WWL3n + 2 extending in the X direction is connected to the write word line driver 23A-n, and the other end is connected to the write word line sinker 24-n.
[0086]
The gate of the read selection switch RSW is connected to a read word line RWLn (n = 0, 1, 2,...). One read word line RWLn corresponds to one block BKjk in one column and is common to a plurality of blocks BKjk arranged in the X direction.
[0087]
For example, when one column is composed of four blocks, the number of read word lines RWLn is four. The read word line RWLn extends in the X direction, and one end thereof is connected to the read word line driver 23B-n.
[0088]
The row decoder 25-n selects one of the write word lines WWL3n, WWL3n + 1, and WWL3n + 2 based on the row address signal during the write operation. The write word line driver 23A-n supplies a write current to the selected write word line. The write current flows through the selected word line and is absorbed by the write word line sinker 24-n.
[0089]
The row decoder 25-n selects a block in one row based on, for example, an upper row address signal during a read operation. The read word line driver 23B-n supplies a read word line voltage to the read word line RWLn connected to the selected block BK. In the selected block BK, since the read selection switch RSW is turned on, the read current flows toward the ground point via the plurality of TMR elements in the selected block BK.
[0090]
The other ends of the four TMR elements 12 in the block BKik are connected to the read bit line BLj. One end of the read bit line BLj is connected to the common data line 28 via a column selection switch (MOS transistor) SWA. The common data line 28 is connected to a read circuit (including a sense amplifier) 29B.
[0091]
One ends of the write bit lines BLj0 and BLj1 are connected to a circuit block 29A including a write bit line driver and a write bit line sinker.
[0092]
The other ends of the write bit lines BLj0 and BLj1 are connected to a circuit block 31 including a write bit line driver and a write bit line sinker.
[0093]
A column selection line signal CSLj (j = 0, 1,...) Is input to the gate of the column selection switch SWA. The column decoder 32 outputs a column selection line signal CSLj.
[0094]
In the magnetic random access memory of this example, one column is composed of a plurality of blocks, and reading is performed in units of blocks. One block is composed of a plurality of TMR elements stacked in a plurality of stages and connected in series to each other.
[0095]
With such a cell array structure, the TMR elements are three-dimensionally arranged on the semiconductor substrate, and one MOS transistor (read selection switch) may be associated with the plurality of TMR elements. This can contribute to an increase in memory capacity.
[0096]
(2) Device structure
Next, the device structure will be described.
2 and 3 show a device structure for one block of a magnetic random access memory as Structural Example 1 of the present invention.
[0097]
2 represents a cross section in the Y direction for one block of the magnetic random access memory, and FIG. 3 represents a cross section in the X direction for one block of the magnetic random access memory. The elements shown in FIGS. 2 and 3 are given the same reference numerals as those in FIG. 1 so as to correspond to the elements of the circuit in FIG.
[0098]
A read selection switch (MOS transistor) RSW is disposed on the surface region of the semiconductor substrate 41. The source of the read selection switch RSW is connected to the ground point via the source line SL. The source line SL extends, for example, in a straight line in the X direction.
[0099]
The gate of the read selection switch (MOS transistor) RSW is a read word line RWLn. The read word line RWLn extends in the X direction. On the read selection switch RSW, four TMR elements (MTJ (Magnetic Tunnel Junction) elements) MTJ1, MTJ2, MTJ3, and MTJ4 are stacked.
[0100]
Each of the TMR elements MTJ1, MTJ2, MTJ3, MTJ4 is disposed between the lower electrodes 41A1, 41A2, 41A3, 41A4 and the upper electrodes 41B1, 41B2, 41B3, 41B4. The contact plugs 42B, 42C, 42D, 42E, and 42F connect the four TMR elements MTJ1, MTJ2, MTJ3, and MTJ4 to each other in series.
[0101]
The lower electrode 41A1 of the lowermost TMR element MTJ1 is connected to the drain of the read selection switch (MOS transistor) RSW via the contact plugs 42A and 42B and the intermediate layer 43. The upper electrode 41B4 of the uppermost TMR element MTJ4 is connected to the read bit line BLj extending in the Y direction via the contact plug 42F.
[0102]
Write word line WWL3n is disposed immediately below TMR element MTJ1, write word line WWL3n + 1 is disposed between TMR element MTJ2 and TMR element MTJ3, and write word line WWL3n + 2 is disposed immediately above TMR element MTJ4. . The write word lines WWL3n, WWL3n + 1, and WWL3n + 2 extend in the X direction.
[0103]
The write bit line BLj0 is disposed between the TMR element MTJ1 and the TMR element MTJ2, and the write bit line BLj1 is disposed between the TMR element MTJ3 and the TMR element MTJ4. The write bit lines BLj0 and BLj1 extend in the Y direction.
[0104]
According to such a device structure, a plurality of (in this example, four) TMR elements MTJ1, MTJ2, MTJ3, and MTJ4 are provided for one read selection switch RSW. These TMR elements MTJ1, MTJ2, MTJ3, and MTJ4 are stacked on the read selection switch RSW and connected in series with each other.
[0105]
In this case, for example, only one read bit line BLj may be provided in the uppermost layer. Further, at least one of the write word lines WWL3n, WWL3n + 1, WWL3n + 2 and the write bit lines BLj0, BLj1 can be shared by two TMR elements.
[0106]
Therefore, according to such a device structure, the TMR elements can be arranged on the semiconductor substrate at a high density, which can contribute to an increase in memory capacity. In addition, since the number of wirings (write word line, write bit line, read bit line, etc.) arranged in the array of TMR elements can be reduced, the planarization of the insulating film directly under the TMR element can be realized. The characteristics of the element can be improved.
[0107]
(3) Modification
A modification of Structural Example 1 will be described.
[0108]
4 and 5 show a first modification of the first structural example.
The circuit diagram of FIG. 4 corresponds to the circuit diagram of FIG. 1, and the cross-sectional view of the device structure of FIG. 5 corresponds to the cross-sectional view of the device structure of FIG. The structure of this example is different from the structure of FIGS. 1 to 3 in an element that realizes a read selection switch.
[0109]
That is, in the structure of FIGS. 1 to 3, the read selection switch is composed of a MOS transistor. On the other hand, in the structure of this example, the read selection switch is composed of a diode DI. Accordingly, read word lines RWL0,... RWLn are connected to the cathode of diode DI.
[0110]
When the structure of this example is employed, the read word line RWLi of the selected row is set to “L”, that is, the ground potential during the read operation. At this time, a read current can be supplied to a plurality of TMR elements connected in series constituting the selected row block.
[0111]
6 and 7 show a second modification of the first structural example.
The circuit diagram of FIG. 6 corresponds to the circuit diagram of FIG. 1, and the cross-sectional view of the device structure of FIG. 7 corresponds to the cross-sectional view of the device structure of FIG. The structure of this example is different from the structure shown in FIGS. 1 to 3 in the types of transistors constituting the memory cell array 11 and its peripheral circuits.
[0112]
That is, in the structure of FIGS. 1 to 3, the transistors constituting the memory cell array 11 and its peripheral circuits are MOS transistors. On the other hand, in the structure of this example, the transistors constituting the memory cell array 11 and its peripheral circuits are bipolar transistors.
[0113]
In the case of the structure of this example, all of the transistors constituting the memory cell array 11 and its peripheral circuits may be bipolar transistors, or some of them may be bipolar transistors.
[0114]
(2) Structure example 2
Structural example 2 relates to a cell array structure in which a plurality of TMR elements stacked in a plurality of stages are connected in parallel.
[0115]
(1) Circuit structure
First, the circuit structure will be described.
FIG. 8 shows the main part of a magnetic random access memory as Structural Example 2 of the present invention.
[0116]
The memory cell array 11 includes a plurality of TMR elements 12 arranged in an array in the X direction, the Y direction, and the Z direction. The Z direction refers to a direction perpendicular to the paper surface orthogonal to the X direction and the Y direction.
[0117]
The memory cell array 11 has a cell array structure including j + 1 TMR elements 12 arranged in the X direction, n + 1 TMR elements 12 arranged in the Y direction, and four TMR elements 12 stacked in the Z direction. Have. Although the number of TMR elements 12 stacked in the Z direction is four in this example, the number may be any number as long as it is plural.
[0118]
The four TMR elements 12 stacked in the Z direction are connected in parallel to each other to form one block BKik (i = 0, 1,... J, k = 0, 1,... N). Yes. The four TMR elements 12 in the block BKik actually overlap each other in the direction (Z direction) perpendicular to the paper surface.
[0119]
One ends of the four TMR elements 12 in the block BKik are connected to a ground point via a read selection switch (MOS transistor) RSW.
[0120]
In this example, one row is composed of j + 1 blocks BKik arranged in the X direction. The memory cell array 11 has n + 1 rows. Further, one column is constituted by n + 1 blocks BKik arranged in the Y direction. The memory cell array 11 has j + 1 columns.
[0121]
Near the four TMR elements 12 constituting the block BKik, a plurality (three in this example) of write word lines WWL3n, WWL3n + 1, and WWL3n + 2 extending in the X direction and stacked in the Z direction are arranged. Here, n is a row number, and n = 0, 1, 2,.
[0122]
With respect to the write word line extending in the X direction, for example, as shown in FIG. 219, one write word line can be arranged in one stage in one row. In this case, the number of write word lines in one row extending in the X direction is four (WWL4n, WWL4n + 1, WWL4n + 2, WWL4n + 3), that is, the number of stages where the TMR elements 12 are stacked.
[0123]
As for the write bit line extending in the Y direction, for example, as shown in FIG. 219, one write bit line can be arranged in one stage in one column. In this case, the number of write bit lines in one column extending in the Y direction is four (BLj0, BLj1, BLj2, BLj3), that is, the same as the number of stages where the TMR elements 12 are stacked.
[0124]
However, in this example, at least one write word line in one row extending in the X direction is shared by two TMR elements (upper TMR element and lower TMR element). Specifically, in this example, the write word line WWL3n + 1 is shared by the second-stage TMR element and the third-stage TMR element. In this case, the number of write word lines in one row extending in the X direction is reduced, and planarization of the insulating film immediately below the TMR element 12 and reduction in manufacturing cost can be realized.
[0125]
Considering the block structure, for example, as shown in FIG. 220, one write word line is shared by the first and second TMR elements, and one write is written by the third and fourth TMR elements. Word lines can also be shared. In this case, the number of write word lines in one row extending in the X direction can be two (WWL2n, WWL2n + 1).
[0126]
Nevertheless, in this example, the number of write word lines in one row extending in the X direction is set to three because the positions of the write bit lines in one column extending in the Y direction are taken into consideration.
[0127]
That is, in this example, one write bit line BLj0 extending in the Y direction is arranged between the first stage TMR element 12 and the second stage TMR element 12, and the third stage TMR element 12 and the fourth stage TMR element 12 are connected. One write bit line BLj1 extending in the Y direction is arranged between the TMR elements 12.
[0128]
As a result, with respect to the write bit lines in one column extending in the Y direction, one write bit line is shared by the first and second TMR elements, and one write bit line is shared by the third and fourth TMR elements. Write bit lines are shared. In this case, the number of write bit lines in one column extending in the Y direction is two.
[0129]
In FIG. 8, the two write bit lines Bj0 and BLj1 are drawn so as to intersect the four TMR elements 12 in the block Bjn because the TMR element 12 cannot be drawn in three dimensions. Actually, as described above, one write bit line BLj0 is arranged between the first-stage TMR element and the second-stage TMR element, and 1 between the third-stage TMR element and the fourth-stage TMR element. Two write word lines BLj1 are arranged.
[0130]
The specific structure of the TMR element in the block and its vicinity will be clarified in the description of the device structure described later.
[0131]
One end of the write word lines WWL3n, WWL3n + 1, WWL3n + 2 extending in the X direction is connected to the write word line driver 23A-n, and the other end is connected to the write word line sinker 24-n.
[0132]
The gate of the read selection switch RSW is connected to a read word line RWLn (n = 0, 1, 2,...). One read word line RWLn corresponds to one block BKjk in one column and is common to a plurality of blocks BKjk arranged in the X direction.
[0133]
For example, when one column is composed of four blocks, the number of read word lines RWLn is four. The read word line RWLn extends in the X direction, and one end thereof is connected to the read word line driver 23B-n.
[0134]
The row decoder 25-n selects one of the write word lines WWL3n, WWL3n + 1, and WWL3n + 2 based on the row address signal during the write operation. The write word line driver 23A-n supplies a write current to the selected write word line. The write current flows through the selected word line and is absorbed by the write word line sinker 24-n.
[0135]
The row decoder 25-n selects a block in one row based on, for example, an upper row address signal during a read operation. The read word line driver 23B-n supplies a read word line voltage to the read word line RWLn connected to the selected block BK. In the selected block BK, since the read selection switch RSW is turned on, the read current flows toward the ground point via the plurality of TMR elements in the selected block BK.
[0136]
The other ends of the four TMR elements 12 in the block BKik are connected to the read bit line BLj. One end of the read bit line BLj is connected to the common data line 28 via a column selection switch (MOS transistor) SWA. The common data line 28 is connected to a read circuit (including a sense amplifier) 29B.
[0137]
One ends of the write bit lines BLj0 and BLj1 are connected to a circuit block 29A including a write bit line driver and a write bit line sinker.
[0138]
The other ends of the write bit lines BLj0 and BLj1 are connected to a circuit block 31 including a write bit line driver and a write bit line sinker.
[0139]
A column selection line signal CSLj (j = 0, 1,...) Is input to the gate of the column selection switch SWA. The column decoder 32 outputs a column selection line signal CSLj.
[0140]
In the magnetic random access memory of this example, one column is composed of a plurality of blocks, and reading is performed in units of blocks. One block is composed of a plurality of TMR elements stacked in a plurality of stages and connected in parallel to each other.
[0141]
With such a cell array structure, the TMR elements are three-dimensionally arranged on the semiconductor substrate, and one MOS transistor (read selection switch) may be associated with the plurality of TMR elements. This can contribute to an increase in memory capacity.
[0142]
(2) Device structure
Next, the device structure will be described.
9 and 10 show the device structure of one block of the magnetic random access memory as Structural Example 2 of the present invention.
[0143]
9 represents a cross section in the Y direction for one block of the magnetic random access memory, and FIG. 10 represents a cross section in the X direction for one block of the magnetic random access memory. The elements shown in FIGS. 9 and 10 are given the same reference numerals as those in FIG. 8 so as to correspond to the elements of the circuit in FIG.
[0144]
A read selection switch (MOS transistor) RSW is disposed on the surface region of the semiconductor substrate 41. The source of the read selection switch RSW is connected to the ground point via the source line SL. The source line SL extends, for example, in a straight line in the X direction.
[0145]
The gate of the read selection switch (MOS transistor) RSW is a read word line RWLn. The read word line RWLn extends in the X direction. On the read selection switch RSW, four TMR elements (MTJ (Magnetic Tunnel Junction) elements) MTJ1, MTJ2, MTJ3, and MTJ4 are stacked.
[0146]
Each of the TMR elements MTJ1, MTJ2, MTJ3, MTJ4 is disposed between the lower electrodes 41A1, 41A2, 41A3, 41A4 and the upper electrodes 41B1, 41B2, 41B3, 41B4. The contact plugs 42C1, 42C2, 42D1, 42D2, 42E1, and 42E2 connect the four TMR elements MTJ1, MTJ2, MTJ3, and MTJ4 to each other in parallel.
[0147]
The lower electrode 41A1 of the lowermost TMR element MTJ1 is connected to the drain of the read selection switch (MOS transistor) RSW via the contact plugs 42A and 42B and the intermediate layer 43. The upper electrode 41B4 of the uppermost TMR element MTJ4 is connected to the read bit line BLj extending in the Y direction via the contact plug 42F.
[0148]
Write word line WWL3n is disposed immediately below TMR element MTJ1, write word line WWL3n + 1 is disposed between TMR element MTJ2 and TMR element MTJ3, and write word line WWL3n + 2 is disposed immediately above TMR element MTJ4. . The write word lines WWL3n, WWL3n + 1, and WWL3n + 2 extend in the X direction.
[0149]
The write bit line BLj0 is disposed between the TMR element MTJ1 and the TMR element MTJ2, and the write bit line BLj1 is disposed between the TMR element MTJ3 and the TMR element MTJ4. The write bit lines BLj0 and BLj1 extend in the Y direction.
[0150]
According to such a device structure, a plurality of (in this example, four) TMR elements MTJ1, MTJ2, MTJ3, and MTJ4 are provided for one read selection switch RSW. These TMR elements MTJ1, MTJ2, MTJ3, and MTJ4 are stacked on the read selection switch RSW and connected in parallel to each other.
[0151]
In this case, for example, only one read bit line BLj may be provided in the uppermost layer. Further, at least one of the write word lines WWL3n, WWL3n + 1, WWL3n + 2 and the write bit lines BLj0, BLj1 can be shared by two TMR elements.
[0152]
Therefore, according to such a device structure, the TMR elements can be arranged on the semiconductor substrate at a high density, which can contribute to an increase in memory capacity. In addition, since the number of wirings (write word line, write bit line, read bit line, etc.) arranged in the array of TMR elements can be reduced, the planarization of the insulating film directly under the TMR element can be realized. The characteristics of the element can be improved.
[0153]
(3) Modification
A modification of Structural Example 2 will be described.
[0154]
FIG. 11 shows a first modification of the structural example 2.
This figure corresponds to FIG. The device structure of this example is different from the device structure of FIG. 9 in that the TMR elements MTJ1, MTJ2, MTJ3, and MTJ4 are stacked.
[0155]
That is, in the device structure of FIG. 9, the TMR elements MTJ1, MTJ2, MTJ3, and MTJ4 are stacked on the gate electrode of the read selection switch (MOS transistor) RSW, that is, immediately above the read word line RWLn.
[0156]
In this case, the lower electrodes 41A1, 41A3 and the upper electrodes 41B2, 41B4 extend from the TMR element to one side, and the lower electrodes 41A2, 41A4 and the upper electrodes 41B1, 41B3 extend from the TMR element to the other side. In addition, contact portions for the lower electrode and the upper electrode are provided on both sides of the TMR element.
[0157]
On the other hand, in the device structure of this example, the TMR elements MTJ1, MTJ2, MTJ3, MTJ4 are stacked immediately above the source line SL connected to the source of the read selection switch (MOS transistor) RSW.
[0158]
In this case, the lower electrodes 41A1, 41A2, 41A3, 41A4 and the upper electrodes 41B1, 41B2, 41B3, 41B4 all spread from the TMR element to one side. Further, contact portions for the lower electrode and the upper electrode are provided only on one side of the TMR element.
[0159]
FIG. 12 is a plan view showing the positional relationship between the TMR element, the lower electrode, and the upper electrode in the device structure of FIG.
In this example, the shapes of the lower electrodes 41A1, 41A3 and the upper electrodes 41B2, 41B4 are different from the shapes of the lower electrodes 41A2, 41A4 and the upper electrodes 41B1, 41B3. Further, parts of the lower electrodes 41A1, 41A3 and the upper electrodes 41B2, 41B4, that is, portions overlapping the lower electrodes 41A2, 41A4 and the upper electrodes 41B1, 41B3 are removed.
[0160]
13 and 14 show a second modification of the second structural example.
The circuit diagram of FIG. 13 corresponds to the circuit diagram of FIG. 8, and the cross-sectional view of the device structure of FIG. 14 corresponds to the cross-sectional view of the device structure of FIG. The structure of this example is different from the structure of FIGS. 8 to 10 in an element that realizes a read selection switch.
[0161]
That is, in the structure of FIGS. 8 to 10, the read selection switch is composed of a MOS transistor. On the other hand, in the structure of this example, the read selection switch is composed of a diode DI. Accordingly, read word lines RWL0,... RWLn are connected to the cathode of diode DI.
[0162]
When the structure of this example is employed, the read word line RWLi of the selected row is set to “L”, that is, the ground potential during the read operation. At this time, a read current can be supplied to a plurality of TMR elements connected in series constituting the selected row block.
[0163]
15 and 16 show a third modification of the second structural example.
The circuit diagram of FIG. 15 corresponds to the circuit diagram of FIG. 8, and the cross-sectional view of the device structure of FIG. 16 corresponds to the cross-sectional view of the device structure of FIG. The structure of this example is different from the structure of FIGS. 8 to 10 in the types of transistors constituting the memory cell array 11 and its peripheral circuits.
[0164]
That is, in the structures of FIGS. 8 to 10, the transistors constituting the memory cell array 11 and its peripheral circuits are MOS transistors. On the other hand, in the structure of this example, the transistors constituting the memory cell array 11 and its peripheral circuits are bipolar transistors.
[0165]
In the case of the structure of this example, all of the transistors constituting the memory cell array 11 and its peripheral circuits may be bipolar transistors, or some of them may be bipolar transistors.
[0166]
(3) Structural example 3
Structural example 3 relates to a cell array structure in which a plurality of TMR elements stacked in a plurality of stages are connected in series and parallel.
[0167]
(1) Circuit structure
First, the circuit structure will be described.
FIG. 17 shows a main part of a magnetic random access memory as Structural Example 3 of the present invention.
[0168]
The memory cell array 11 includes a plurality of TMR elements 12 arranged in an array in the X direction, the Y direction, and the Z direction. The Z direction refers to a direction perpendicular to the paper surface orthogonal to the X direction and the Y direction.
[0169]
The memory cell array 11 has a cell array structure including j + 1 TMR elements 12 arranged in the X direction, n + 1 TMR elements 12 arranged in the Y direction, and four TMR elements 12 stacked in the Z direction. Have. Although the number of TMR elements 12 stacked in the Z direction is four in this example, the number may be any number as long as it is plural.
[0170]
The four TMR elements 12 stacked in the Z direction are connected in series and in parallel to form one block BKik (i = 0, 1,... J, k = 0, 1,... N). ing. The four TMR elements 12 in the block BKik actually overlap each other in the direction (Z direction) perpendicular to the paper surface.
[0171]
Here, in this example, when the four TMR elements 12 in the block BKik are first to fourth TMR elements, the first and second TMR elements are connected in parallel, and the third and fourth TMR elements are connected in parallel. The first and second TMR elements connected in parallel with the first and second TMR elements connected in parallel are connected in series with each other.
[0172]
One ends of the four TMR elements 12 in the block BKik are connected to a ground point via a read selection switch (MOS transistor) RSW.
[0173]
In this example, one row is composed of j + 1 blocks BKik arranged in the X direction. The memory cell array 11 has n + 1 rows. Further, one column is constituted by n + 1 blocks BKik arranged in the Y direction. The memory cell array 11 has j + 1 columns.
[0174]
Near the four TMR elements 12 constituting the block BKik, a plurality (three in this example) of write word lines WWL3n, WWL3n + 1, and WWL3n + 2 extending in the X direction and stacked in the Z direction are arranged. Here, n is a row number, and n = 0, 1, 2,.
[0175]
With respect to the write word line extending in the X direction, for example, as shown in FIG. 221, one write word line can be arranged in one stage in one row. In this case, the number of write word lines in one row extending in the X direction is four (WWL4n, WWL4n + 1, WWL4n + 2, WWL4n + 3), that is, the number of stages where the TMR elements 12 are stacked.
[0176]
As for the write bit line extending in the Y direction, for example, as shown in FIG. 221, one write bit line can be arranged in one stage in one column. In this case, the number of write bit lines in one column extending in the Y direction is four (BLj0, BLj1, BLj2, BLj3), that is, the same as the number of stages where the TMR elements 12 are stacked.
[0177]
However, in this example, at least one write word line in one row extending in the X direction is shared by two TMR elements (upper TMR element and lower TMR element). Specifically, in this example, the write word line WWL3n + 1 is shared by the second-stage TMR element and the third-stage TMR element. In this case, the number of write word lines in one row extending in the X direction is reduced, and planarization of the insulating film immediately below the TMR element 12 and reduction in manufacturing cost can be realized.
[0178]
Considering the block structure, for example, as shown in FIG. 222, the first and second TMR elements share one write word line, and the third and fourth TMR elements share one write. Word lines can also be shared. In this case, the number of write word lines in one row extending in the X direction can be two (WWL2n, WWL2n + 1).
[0179]
Nevertheless, in this example, the number of write word lines in one row extending in the X direction is set to three because the positions of the write bit lines in one column extending in the Y direction are taken into consideration.
[0180]
That is, in this example, one write bit line BLj0 extending in the Y direction is arranged between the first stage TMR element 12 and the second stage TMR element 12, and the third stage TMR element 12 and the fourth stage TMR element 12 are connected. One write bit line BLj1 extending in the Y direction is arranged between the TMR elements 12.
[0181]
As a result, with respect to the write bit lines in one column extending in the Y direction, one write bit line is shared by the first and second TMR elements, and one write bit line is shared by the third and fourth TMR elements. Write bit lines are shared. In this case, the number of write bit lines in one column extending in the Y direction is two.
[0182]
In FIG. 17, the two write bit lines Bj0 and BLj1 are drawn so as to intersect the four TMR elements 12 in the block Bjn because the TMR element 12 cannot be drawn in three dimensions. Actually, as described above, one write bit line BLj0 is arranged between the first-stage TMR element and the second-stage TMR element, and 1 between the third-stage TMR element and the fourth-stage TMR element. Two write word lines BLj1 are arranged.
[0183]
The specific structure of the TMR element in the block and its vicinity will be clarified in the description of the device structure described later.
[0184]
One end of the write word lines WWL3n, WWL3n + 1, WWL3n + 2 extending in the X direction is connected to the write word line driver 23A-n, and the other end is connected to the write word line sinker 24-n.
[0185]
The gate of the read selection switch RSW is connected to a read word line RWLn (n = 0, 1, 2,...). One read word line RWLn corresponds to one block BKjk in one column and is common to a plurality of blocks BKjk arranged in the X direction.
[0186]
For example, when one column is composed of four blocks, the number of read word lines RWLn is four. The read word line RWLn extends in the X direction, and one end thereof is connected to the read word line driver 23B-n.
[0187]
The row decoder 25-n selects one of the write word lines WWL3n, WWL3n + 1, and WWL3n + 2 based on the row address signal during the write operation. The write word line driver 23A-n supplies a write current to the selected write word line. The write current flows through the selected word line and is absorbed by the write word line sinker 24-n.
[0188]
The row decoder 25-n selects a block in one row based on, for example, an upper row address signal during a read operation. The read word line driver 23B-n supplies a read word line voltage to the read word line RWLn connected to the selected block BK. In the selected block BK, since the read selection switch RSW is turned on, the read current flows toward the ground point via the plurality of TMR elements in the selected block BK.
[0189]
The other ends of the four TMR elements 12 in the block BKik are connected to the read bit line BLj. One end of the read bit line BLj is connected to the common data line 28 via a column selection switch (MOS transistor) SWA. The common data line 28 is connected to a read circuit (including a sense amplifier) 29B.
[0190]
One ends of the write bit lines BLj0 and BLj1 are connected to a circuit block 29A including a write bit line driver and a write bit line sinker.
[0191]
The other ends of the write bit lines BLj0 and BLj1 are connected to a circuit block 31 including a write bit line driver and a write bit line sinker.
[0192]
A column selection line signal CSLj (j = 0, 1,...) Is input to the gate of the column selection switch SWA. The column decoder 32 outputs a column selection line signal CSLj.
[0193]
In the magnetic random access memory of this example, one column is composed of a plurality of blocks, and reading is performed in units of blocks. One block is composed of a plurality of TMR elements stacked in a plurality of stages and connected in series and parallel to each other.
[0194]
With such a cell array structure, the TMR elements are three-dimensionally arranged on the semiconductor substrate, and one MOS transistor (read selection switch) may be associated with the plurality of TMR elements. This can contribute to an increase in memory capacity.
[0195]
(2) Device structure
Next, the device structure will be described.
FIG. 18 shows a device structure for one block of a magnetic random access memory as Structural Example 3 of the present invention.
[0196]
FIG. 18 shows a cross section in the Y direction for one block of the magnetic random access memory. Elements shown in FIG. 18 are denoted by the same reference numerals as those in FIG. 17 so as to correspond to the elements of the circuit in FIG.
[0197]
A read selection switch (MOS transistor) RSW is disposed on the surface region of the semiconductor substrate 41. The source of the read selection switch RSW is connected to the ground point via the source line SL. The source line SL extends, for example, in a straight line in the X direction.
[0198]
The gate of the read selection switch (MOS transistor) RSW is a read word line RWLn. The read word line RWLn extends in the X direction. On the read selection switch RSW, four TMR elements (MTJ (Magnetic Tunnel Junction) elements) MTJ1, MTJ2, MTJ3, and MTJ4 are stacked.
[0199]
Each of the TMR elements MTJ1, MTJ2, MTJ3, MTJ4 is disposed between the lower electrodes 41A1, 41A2, 41A3, 41A4 and the upper electrodes 41B1, 41B2, 41B3, 41B4. The contact plugs 42C1, 42C2, 42D1, 42E1, and 42E2 connect the four TMR elements MTJ1, MTJ2, MTJ3, and MTJ4 in series and parallel to each other.
[0200]
The lower electrode 41A1 of the lowermost TMR element MTJ1 is connected to the drain of the read selection switch (MOS transistor) RSW via the contact plugs 42A and 42B and the intermediate layer 43. The upper electrode 41B4 of the uppermost TMR element MTJ4 is connected to the read bit line BLj extending in the Y direction via the contact plug 42F.
[0201]
Write word line WWL3n is disposed immediately below TMR element MTJ1, write word line WWL3n + 1 is disposed between TMR element MTJ2 and TMR element MTJ3, and write word line WWL3n + 2 is disposed immediately above TMR element MTJ4. . The write word lines WWL3n, WWL3n + 1, and WWL3n + 2 extend in the X direction.
[0202]
The write bit line BLj0 is disposed between the TMR element MTJ1 and the TMR element MTJ2, and the write bit line BLj1 is disposed between the TMR element MTJ3 and the TMR element MTJ4. The write bit lines BLj0 and BLj1 extend in the Y direction.
[0203]
According to such a device structure, a plurality of (in this example, four) TMR elements MTJ1, MTJ2, MTJ3, and MTJ4 are provided for one read selection switch RSW. These TMR elements MTJ1, MTJ2, MTJ3, and MTJ4 are stacked on the read selection switch RSW and are connected in series and parallel to each other.
[0204]
In this case, for example, only one read bit line BLj may be provided in the uppermost layer. Further, at least one of the write word lines WWL3n, WWL3n + 1, WWL3n + 2 and the write bit lines BLj0, BLj1 can be shared by two TMR elements.
[0205]
Therefore, according to such a device structure, the TMR elements can be arranged on the semiconductor substrate at a high density, which can contribute to an increase in memory capacity. In addition, since the number of wirings (write word line, write bit line, read bit line, etc.) arranged in the array of TMR elements can be reduced, the planarization of the insulating film directly under the TMR element can be realized. The characteristics of the element can be improved.
[0206]
(3) Modification
A modification of Structural Example 3 will be described.
[0207]
19 and 20 show a first modification of the structure example 3. FIG.
The circuit diagram of FIG. 19 corresponds to the circuit diagram of FIG. 17, and the cross-sectional view of the device structure of FIG. 20 corresponds to the cross-sectional view of the device structure of FIG. The structure of this example is different from the structure of FIGS. 17 and 18 in an element that realizes a read selection switch.
[0208]
That is, in the structure of FIGS. 17 and 18, the read selection switch is composed of a MOS transistor. On the other hand, in the structure of this example, the read selection switch is composed of a diode DI. Accordingly, read word lines RWL0,... RWLn are connected to the cathode of diode DI.
[0209]
When the structure of this example is employed, the read word line RWLi of the selected row is set to “L”, that is, the ground potential during the read operation. At this time, a read current can be supplied to a plurality of TMR elements connected in series constituting the selected row block.
[0210]
21 and 22 show a second modification of the third structural example.
The circuit diagram of FIG. 21 corresponds to the circuit diagram of FIG. 17, and the cross-sectional view of the device structure of FIG. 22 corresponds to the cross-sectional view of the device structure of FIG. The structure of this example is different from the structures of FIGS. 17 and 18 in the types of transistors constituting the memory cell array 11 and its peripheral circuits.
[0211]
That is, in the structures of FIGS. 17 and 18, the transistors constituting the memory cell array 11 and its peripheral circuits are MOS transistors. On the other hand, in the structure of this example, the transistors constituting the memory cell array 11 and its peripheral circuits are bipolar transistors.
[0212]
In the case of the structure of this example, all of the transistors constituting the memory cell array 11 and its peripheral circuits may be bipolar transistors, or some of them may be bipolar transistors.
[0213]
(4) Structural example 4
Structure example 4 is an improved example of structure examples 1 to 3. Structural Example 4 can be used in combination with Structural Examples 1 to 3.
[0214]
In Structure Example 4, the write lines in one row extending in the Y direction of the memory cell array have a folded structure (meander structure) or a parallel connection structure, so that the number of write lines in one row is substantially one. It has the feature in the point.
[0215]
According to such a structure, the number of write drivers / sinkers connected to the write lines in one row can be reduced, so that the manufacturing cost can be reduced by reducing the chip area.
[0216]
(1) Circuit structure
First, the circuit structure will be described.
23 to 25 show the main part of a magnetic random access memory as Structural Example 4 of the present invention.
23 is an example in which the structural example 4 is applied to the structural example 1 in FIG. 1, FIG. 24 is an example in which the structural example 4 is applied to the structural example 2 in FIG. 8, and FIG. It is an example applied to the structural example 3 of FIG.
[0217]
The memory cell array 11 includes a plurality of TMR elements 12 arranged in an array in the X direction, the Y direction, and the Z direction. The Z direction refers to a direction perpendicular to the paper surface orthogonal to the X direction and the Y direction.
[0218]
The memory cell array 11 has a cell array structure including j + 1 TMR elements 12 arranged in the X direction, n + 1 TMR elements 12 arranged in the Y direction, and four TMR elements 12 stacked in the Z direction. Have. Although the number of TMR elements 12 stacked in the Z direction is four in this example, the number may be any number as long as it is plural.
[0219]
The four TMR elements 12 stacked in the Z direction are connected to each other in series (FIG. 23), parallel (FIG. 24), or series-parallel (FIG. 25), and one block BKik (i = 0, 1,... J, k = 0, 1,... N). The four TMR elements 12 in the block BKik actually overlap each other in the direction (Z direction) perpendicular to the paper surface.
[0220]
One ends of the four TMR elements 12 in the block BKik are connected to a ground point via a read selection switch (MOS transistor) RSW.
[0221]
In this example, one row is composed of j + 1 blocks BKik arranged in the X direction. The memory cell array 11 has n + 1 rows. Further, one column is constituted by n + 1 blocks BKik arranged in the Y direction. The memory cell array 11 has j + 1 columns.
[0222]
In the vicinity of the four TMR elements 12 constituting the block BKik, a plurality of write word lines extending in the X direction and stacked in the Z direction are arranged. The plurality of write word lines are connected in series to each other at the end of the memory cell array 11 to form one write word line WWLn. Overall, the write word line WWLn is arranged in a winding manner so as to sew the inside of the memory cell array 11.
[0223]
Such a structure of the write word line is called a folded structure (or a meander structure).
[0224]
According to the folded structure (or meandering structure), substantially only one write word line WWLn is arranged in one row, so that the write driver / connected to the write word line WWLn in one row The number of elements constituting the sinkers 23A-n and 24-n can be reduced. Therefore, the manufacturing cost can be reduced by reducing the chip area.
[0225]
Considering the block structure, as shown in FIGS. 223 to 225, the write word lines WWLn are respectively provided between the first and second TMR elements and between the third and fourth TMR elements. , The length of the write word line WWLn can be shortened.
[0226]
However, in this example, the write word line WWLn having the folded structure is directly below the bottom TMR element, between the second stage TMR element and the third stage TMR element, and immediately above the top stage TMR element. , Respectively.
[0227]
The reason for this structure is that the position of the write bit line in one column extending in the Y direction is taken into consideration.
[0228]
That is, one write bit line BLj0 extending in the Y direction is arranged between the first-stage TMR element 12 and the second-stage TMR element 12, and the third-stage TMR element 12 and the fourth-stage TMR element 12 One write bit line BLj1 extending in the Y direction is arranged therebetween.
[0229]
As a result, with respect to the write bit lines in one column extending in the Y direction, one write bit line is shared by the first and second TMR elements, and one write bit line is shared by the third and fourth TMR elements. Write bit lines are shared. In this case, the number of write bit lines in one column extending in the Y direction is two.
[0230]
23 to 25, the two write bit lines Bj0 and BLj1 are drawn so as to be parallel or intersecting with the four TMR elements 12 in the block Bjn because the TMR element 12 cannot be drawn three-dimensionally. In reality, however, as described above, one write bit line BLj0 is arranged between the first-stage TMR element and the second-stage TMR element, and the third-stage TMR element and the fourth-stage TMR element. One write word line BLj1 is arranged between the elements.
[0231]
One end of the write word line WWLn extending in the X direction is connected to the write word line driver 23A-n, and the other end is connected to the write word line sinker 24-n.
[0232]
The gate of the read selection switch RSW is connected to a read word line RWLn (n = 0, 1, 2,...). One read word line RWLn corresponds to one block BKjk in one column and is common to a plurality of blocks BKjk arranged in the X direction.
[0233]
For example, when one column is composed of four blocks, the number of read word lines RWLn is four. The read word line RWLn extends in the X direction, and one end thereof is connected to the read word line driver 23B-n.
[0234]
The row decoder 25-n selects one of the write word lines WWL0,... WWLn based on the row address signal during the write operation. The write word line driver 23A-n supplies a write current to the selected write word line. The write current flows through the selected word line and is absorbed by the write word line sinker 24-n.
[0235]
The row decoder 25-n selects a block in one row based on, for example, an upper row address signal during a read operation. The read word line driver 23B-n supplies a read word line voltage to the read word line RWLn connected to the selected block BK. In the selected block BK, since the read selection switch RSW is turned on, the read current flows toward the ground point via the plurality of TMR elements in the selected block BK.
[0236]
The other ends of the four TMR elements 12 in the block BKik are connected to the read bit line BLj. One end of the read bit line BLj is connected to the common data line 28 via a column selection switch (MOS transistor) SWA. The common data line 28 is connected to a read circuit (including a sense amplifier) 29B.
[0237]
One ends of the write bit lines BLj0 and BLj1 are connected to a circuit block 29A including a write bit line driver and a write bit line sinker.
[0238]
The other ends of the write bit lines BLj0 and BLj1 are connected to a circuit block 31 including a write bit line driver and a write bit line sinker.
[0239]
A column selection line signal CSLj (j = 0, 1,...) Is input to the gate of the column selection switch SWA. The column decoder 32 outputs a column selection line signal CSLj.
[0240]
In the magnetic random access memory of this example, one column is composed of a plurality of blocks, and reading is performed in units of blocks. One block is composed of a plurality of TMR elements stacked in a plurality of stages and connected in series, parallel, or series-parallel to each other.
[0241]
With such a cell array structure, the TMR elements 12 are three-dimensionally arranged on the semiconductor substrate, and one MOS transistor (read selection switch) RSW may correspond to the plurality of TMR elements 12. As a result, the memory capacity can be increased.
[0242]
In the magnetic random access memory of this example, since the write word line WWLn has a folded structure (or a meandering structure), substantially only one write word line WWLn is arranged in one row. The
[0243]
Therefore, the number of elements constituting the write driver / sinkers 23A-n and 24-n connected to the write word line WWLn in one row can be reduced, and the manufacturing cost can be reduced by reducing the chip area. .
[0244]
(2) Device structure
Next, the device structure will be described.
FIG. 26 shows a device structure for one block of the magnetic random access memory as Structural Example 4 of the present invention.
[0245]
FIG. 26 shows a Y-direction cross section of one block of the magnetic random access memory. Elements shown in FIG. 26 are denoted by the same reference numerals as those in FIGS. 23 to 25 so as to correspond to the elements of the circuits in FIGS.
[0246]
In the figure, in order to clarify the characteristics of the structural example 4, all members other than the write word line WWLn are omitted in the memory cell array 11.
[0247]
On the memory cell array 11, wirings constituting the write word line WWLn are stacked in three stages. These wirings are connected to each other by contact plugs at the end of the memory cell array 11. As a result, the write word line WWLn has a folded structure (or a meandering structure) on the memory cell array 11.
[0248]
One end of the write word line WWLn is connected to the write word line driver 23A-n, and the other end is connected to the write word line sinker 24-n.
[0249]
In this example, since the wirings constituting the write word line WWLn are stacked in three stages (odd stages), the position of the write word line driver 23A-n and the position of the write word line sinker 24-n are in the memory cell array 11. The positions are opposite to each other.
[0250]
If the wirings constituting the write word line WWLn are stacked in four stages (a plurality of stages), the write word line driver 23A-n and the write word line sinker 24-n are in the same direction with respect to the memory cell array 11. Placed in.
[0251]
According to such a device structure, since the write word line WWLn has a folded structure (or a meandering structure), substantially only one write word line WWLn is arranged in one row.
[0252]
Accordingly, the number of elements constituting the write word line drivers / sinkers 23A-n and 24-n connected to the write word line WWLn in one row can be reduced, and the manufacturing cost can be reduced by reducing the chip area. Can do.
[0253]
(3) Modification
A modification of the device structure of Structural Example 4 will be described.
[0254]
FIG. 27 shows a device structure for one block of a magnetic random access memory as Structural Example 4 of the present invention.
[0255]
FIG. 27 shows a cross section in the Y direction for one block of the magnetic random access memory. The elements shown in FIG. 27 are given the same reference numerals as those in FIGS. 23 to 25 so as to correspond to the elements of the circuits in FIGS.
[0256]
In the figure, in order to clarify the characteristics of the structural example 4, all members other than the write word line WWLn are omitted in the memory cell array 11.
[0257]
On the memory cell array 11, wirings constituting the write word line WWLn are stacked in three stages. These wirings are connected to each other by contact plugs at the end of the memory cell array 11. As a result, the write word line WWLn has a structure (parallel connection structure) connected in parallel on the memory cell array 11.
[0258]
One end of the write word line WWLn is connected to the write word line driver 23A-n, and the other end is connected to the write word line sinker 24-n.
[0259]
In this example, the wirings constituting the write word line WWLn are stacked in three stages, but if there are a plurality of stages (two or more stages), how many stages the wirings constituting the write word line WWLn are stacked. But it doesn't matter at all.
[0260]
According to such a device structure, since the write word line WWLn has a parallel connection structure, substantially only one write word line WWLn is arranged in one row.
[0261]
Accordingly, the number of elements constituting the write word line drivers / sinkers 23A-n and 24-n connected to the write word line WWLn in one row can be reduced, and the manufacturing cost can be reduced by reducing the chip area. Can do.
[0262]
(4) Structural example 5
Structure example 5 is an improved example of structure examples 1 to 3. Structure Example 5 can be used in combination with Structure Examples 1 to 3.
[0263]
In Structural Example 5, the write lines in one column extending in the X direction of the memory cell array have a folded structure (meander structure) or a parallel connection structure, so that the number of write lines in one column is substantially one. It has the feature in the point.
[0264]
According to such a structure, the number of write drivers / sinkers connected to the write lines in one column can be reduced, so that the manufacturing cost can be reduced by reducing the chip area.
[0265]
(1) Circuit structure
First, the circuit structure will be described.
28 to 30 show the main part of a magnetic random access memory as Structural Example 5 of the present invention.
FIG. 28 is an example in which the structural example 5 is applied to the structural example 1 in FIG. 1, FIG. 29 is an example in which the structural example 5 is applied to the structural example 2 in FIG. 8, and FIG. It is an example applied to the structural example 3 of FIG.
[0266]
The memory cell array 11 includes a plurality of TMR elements 12 arranged in an array in the X direction, the Y direction, and the Z direction. The Z direction refers to a direction perpendicular to the paper surface orthogonal to the X direction and the Y direction.
[0267]
The memory cell array 11 has a cell array structure including j + 1 TMR elements 12 arranged in the X direction, n + 1 TMR elements 12 arranged in the Y direction, and four TMR elements 12 stacked in the Z direction. Have. Although the number of TMR elements 12 stacked in the Z direction is four in this example, the number may be any number as long as it is plural.
[0268]
The four TMR elements 12 stacked in the Z direction are connected to each other in series (FIG. 28), in parallel (FIG. 29), or in series parallel (FIG. 30), and one block BKik (i = 0, 1,... J, k = 0, 1,... N). The four TMR elements 12 in the block BKik actually overlap each other in the direction (Z direction) perpendicular to the paper surface.
[0269]
One ends of the four TMR elements 12 in the block BKik are connected to a ground point via a read selection switch (MOS transistor) RSW.
[0270]
In this example, one row is composed of j + 1 blocks BKik arranged in the X direction. The memory cell array 11 has n + 1 rows. Further, one column is constituted by n + 1 blocks BKik arranged in the Y direction. The memory cell array 11 has j + 1 columns.
[0271]
In the vicinity of the four TMR elements 12 constituting the block BKik, a plurality of write word lines WWL3n, WWL3n + 1, WWL3n + 2 extending in the X direction and stacked in the Z direction are arranged.
[0272]
The write word lines WWL3n, WWL3n + 1, and WWL3n + 2 are arranged immediately below the bottom TMR element, between the second stage TMR element and the third stage TMR element, and directly above the top stage TMR element, respectively.
[0273]
In view of the block structure, as shown in FIGS. 226 to 228, write word lines are respectively provided between the first and second TMR elements and between the third and fourth TMR elements. If arranged, the length of the write word line can be shortened.
[0274]
However, in this example, the write word lines WWL3n, WWL3n + 1, and WWL3n + 2 are directly below the bottom TMR element, between the second stage TMR element and the third stage TMR element, and immediately above the top stage TMR element. , Respectively.
[0275]
The reason for this structure is that the position of the write bit line in one column extending in the Y direction is taken into consideration.
[0276]
That is, a write bit line extending in the Y direction is disposed between the first stage TMR element 12 and the second stage TMR element 12, and the Y direction is provided between the third stage TMR element 12 and the fourth stage TMR element 12. A write bit line extending to is arranged.
[0277]
The plurality of write bit lines are connected in series at the end of the memory cell array 11 to form one write bit line BLj1. Overall, the write bit line BLj1 is arranged to be bent so as to sew the inside of the memory cell array 11.
[0278]
Such a structure of the write bit line is referred to as a folded structure (or a meander structure).
[0279]
According to the folded structure (or the meandering structure), substantially only one write bit line BLj1 is arranged in one column, so that the write driver / connected to the write bit line BLj1 in one column The number of elements constituting the sinker 31 can be reduced. Therefore, the manufacturing cost can be reduced by reducing the chip area.
[0280]
In FIG. 28 to FIG. 30, the write bit line Bj1 having the folded structure is drawn so as to be parallel or intersecting with the four TMR elements 12 in the block Bjn because the TMR element 12 cannot be drawn three-dimensionally. Actually, however, as described above, the write bit line BLj1 is arranged between the first-stage TMR element and the second-stage TMR element, and between the third-stage TMR element and the fourth-stage TMR element. Is done.
[0281]
One end of the write word lines WWL3n, WWL3n + 1, WWL3n + 2 extending in the X direction is connected to the write word line driver 23A-n, and the other end is connected to the write word line sinker 24-n.
[0282]
The gate of the read selection switch RSW is connected to a read word line RWLn (n = 0, 1, 2,...). One read word line RWLn corresponds to one block BKjk in one column and is common to a plurality of blocks BKjk arranged in the X direction.
[0283]
For example, when one column is composed of four blocks, the number of read word lines RWLn is four. The read word line RWLn extends in the X direction, and one end thereof is connected to the read word line driver 23B-n.
[0284]
The row decoder 25-n selects one of the write word lines WWL3n, WWL3n + 1, and WWL3n + 2 based on the row address signal during the write operation. The write word line driver 23A-n supplies a write current to the selected write word line. The write current flows through the selected word line and is absorbed by the write word line sinker 24-n.
[0285]
The row decoder 25-n selects a block in one row based on, for example, an upper row address signal during a read operation. The read word line driver 23B-n supplies a read word line voltage to the read word line RWLn connected to the selected block BK. In the selected block BK, since the read selection switch RSW is turned on, the read current flows toward the ground point via the plurality of TMR elements in the selected block BK.
[0286]
The other ends of the four TMR elements 12 in the block BKik are connected to the read bit line BLj. One end of the read bit line BLj is connected to the common data line 28 via a column selection switch (MOS transistor) SWA. The common data line 28 is connected to a read circuit (including a sense amplifier) 29B.
[0287]
One end and the other end of the write bit line BLj1 are connected to a circuit block 31 including a write bit line driver and a write bit line sinker.
[0288]
A column selection line signal CSLj (j = 0, 1,...) Is input to the gate of the column selection switch SWA. The column decoder 32 outputs a column selection line signal CSLj.
[0289]
In the magnetic random access memory of this example, one column is composed of a plurality of blocks, and reading is performed in units of blocks. One block is composed of a plurality of TMR elements stacked in a plurality of stages and connected in series, parallel, or series-parallel to each other.
[0290]
With such a cell array structure, the TMR elements 12 are three-dimensionally arranged on the semiconductor substrate, and one MOS transistor (read selection switch) RSW may correspond to the plurality of TMR elements 12. As a result, the memory capacity can be increased.
[0291]
In the magnetic random access memory of this example, since the write bit line BLj1 has a folded structure (or a meandering structure), substantially only one write bit line BLj1 is arranged in one column. The
[0292]
Therefore, the number of elements constituting the write driver / sinker 31 connected to the write bit BLj1 in one column can be reduced, and the manufacturing cost can be reduced by reducing the chip area.
[0293]
(2) Device structure
Next, the device structure will be described.
FIG. 31 shows a device structure for one block of a magnetic random access memory as Structural Example 5 of the present invention.
[0294]
FIG. 31 shows a cross section in the Y direction for one block of the magnetic random access memory. Elements shown in FIG. 31 are denoted by the same reference numerals as those in FIGS. 28 to 30 so as to correspond to the elements of the circuits in FIGS.
[0295]
In the figure, in order to clarify the characteristics of the structural example 5, all members other than the write bit line BLj1 and the read bit line BLj are omitted in the memory cell array 11.
[0296]
On the memory cell array 11, wirings constituting the write bit line BLj1 are stacked in two stages. These wirings are connected to each other by contact plugs at the end of the memory cell array 11. As a result, the write bit line BLj1 has a folded structure (or a meandering structure) on the memory cell array 11.
[0297]
One end and the other end of the write bit line BLj1 are connected to the write bit line driver / sinker 31, respectively.
[0298]
In this example, since the wirings constituting the write bit line BLj1 are stacked in two stages (even stages), the write bit line driver / sinker is disposed only on one end side of the memory cell array 11.
[0299]
Assuming that the wirings constituting the write bit line BLj1 are stacked in three stages (odd stages), the write bit line drivers / sinkers are arranged on both ends of the memory cell array 11, respectively.
[0300]
According to such a device structure, since the write bit line BLj1 has a folded structure (or a meandering structure), substantially only one write bit line BLj1 is arranged in one column.
[0301]
Therefore, the number of elements constituting the write bit line driver / sinker 31 connected to the write bit line BLj1 in one column can be reduced, and the manufacturing cost can be reduced by reducing the chip area.
[0302]
(3) Modification
A modified example of the device structure of Structural Example 5 will be described.
[0303]
FIG. 32 shows the device structure of one block of the magnetic random access memory as Structural Example 5 of the present invention.
[0304]
FIG. 32 shows a cross section in the Y direction for one block of the magnetic random access memory. Elements shown in FIG. 32 are denoted by the same reference numerals as those in FIGS. 28 to 30 so as to correspond to the elements of the circuits in FIGS.
[0305]
In the figure, all members other than the write bit line BLj1 are omitted in the memory cell array 11 in order to clarify the characteristics of the structural example 5.
[0306]
On the memory cell array 11, wirings constituting the write bit line BLj1 are stacked in two stages. These wirings are connected to each other by contact plugs at the end of the memory cell array 11. As a result, the write bit line BLj1 has a structure (parallel connection structure) connected in parallel on the memory cell array 11.
[0307]
One end and the other end of the write bit line BLj1 are both connected to the write bit line driver / sinker 31.
[0308]
In this example, the wirings constituting the write bit line BLj1 are stacked in two stages, but if there are a plurality of stages (two or more stages), how many stages the wirings constituting the write bit line BLj1 are stacked. But it doesn't matter at all.
[0309]
According to such a device structure, since the write bit line BLj1 has a parallel connection structure, substantially only one write bit line BLj1 is arranged in one column.
[0310]
Therefore, the number of elements constituting the write bit line driver / sinker 31 connected to the write bit line BLj1 in one column can be reduced, and the manufacturing cost can be reduced by reducing the chip area.
[0311]
3. Structure of TMR element
In the cell array structure described above, a plurality of TMR elements in one block are connected in series, parallel, or series-parallel.
[0312]
When such a cell array structure is assumed, it is necessary to adopt a read operation principle such as a destructive read operation principle when the structures of a plurality of TMR elements in one block are the same (for example, Japanese Patent Application No. 2001-350013). issue). It is also possible to adopt a collective read operation principle that does not depend on the destructive read operation principle by making the structures of a plurality of TMR elements in one block different (for example, Japanese Patent Application No. 2001-365236).
[0313]
These read operation principles will be described in detail later, and here, a structural example of a TMR element for realizing these read operation principles will be described.
[0314]
(1) Equivalent circuit during read operation
First, an equivalent circuit of a TMR element (memory cell) in one block during a read operation will be described.
[0315]
33 to 35 show equivalent circuits during a read operation in the first structural example of the cell array structure.
[0316]
The four TMR elements MTJ1, MTJ2, MTJ3, MTJ4 are connected in series with each other, and one end thereof is connected to the read bit line BLj. The potential of the read bit line BLj is set to the power supply potential VDD, for example. A read selection switch (MOS transistor) RSW is connected between the other end of the TMR elements MTJ1, MTJ2, MTJ3, MTJ4 connected in series and the source line SL.
[0317]
When the read selection switch RSW is a MOS transistor (FIG. 33), its gate, that is, the potential of the read word line RWLn is set to “H”. For this reason, the read selection switch RSW is turned on. For example, the source line SL is set to the ground potential VSS.
[0318]
When the read selection switch RSW is a diode (FIG. 34), its cathode, that is, the potential of the read word line RWLn is set to “L (= VSS)”. For this reason, the read selection switch RSW is turned on.
[0319]
When the read selection switch RSW is a bipolar transistor (FIG. 35), its base, that is, the potential of the read word line RWLn is set to “H”. For this reason, the read selection switch RSW is turned on. For example, the source line SL is set to the ground potential VSS.
[0320]
36 to 38 show equivalent circuits at the time of a read operation in the structural example 2 of the cell array structure.
[0321]
The four TMR elements MTJ1, MTJ2, MTJ3, and MTJ4 are connected in parallel to each other, and one end thereof is connected to the read bit line BLj. The potential of the read bit line BLj is set to the power supply potential VDD, for example. A read selection switch (MOS transistor) RSW is connected between the other end of the TMR elements MTJ1, MTJ2, MTJ3, MTJ4 connected in parallel and the source line SL.
[0322]
When the read selection switch RSW is a MOS transistor (FIG. 36), its gate, that is, the potential of the read word line RWLn is set to “H”. For this reason, the read selection switch RSW is turned on. For example, the source line SL is set to the ground potential VSS.
[0323]
When the read selection switch RSW is a diode (FIG. 37), the cathode, that is, the potential of the read word line RWLn is set to “L (= VSS)”. For this reason, the read selection switch RSW is turned on.
[0324]
When the read selection switch RSW is a bipolar transistor (FIG. 38), its base, that is, the potential of the read word line RWLn is set to “H”. For this reason, the read selection switch RSW is turned on. For example, the source line SL is set to the ground potential VSS.
[0325]
39 to 41 show equivalent circuits at the time of a read operation in the third structural example of the cell array structure.
[0326]
The four TMR elements MTJ1, MTJ2, MTJ3, MTJ4 are connected in series and parallel, and one end thereof is connected to the read bit line BLj. The potential of the read bit line BLj is set to the power supply potential VDD, for example. A read selection switch (MOS transistor) RSW is connected between the other end of the TMR elements MTJ1, MTJ2, MTJ3, MTJ4 connected in series and parallel and the source line SL.
[0327]
When the read selection switch RSW is a MOS transistor (FIG. 39), its gate, that is, the potential of the read word line RWLn is set to “H”. For this reason, the read selection switch RSW is turned on. For example, the source line SL is set to the ground potential VSS.
[0328]
When the read selection switch RSW is a diode (FIG. 40), the cathode, that is, the potential of the read word line RWLn is set to “L (= VSS)”. For this reason, the read selection switch RSW is turned on.
[0329]
When the read selection switch RSW is a bipolar transistor (FIG. 41), its base, that is, the potential of the read word line RWLn is set to “H”. For this reason, the read selection switch RSW is turned on. For example, the source line SL is set to the ground potential VSS.
[0330]
(2) Structure of TMR element
(1) When applying the destructive read operation principle
In this case, the structures of the plurality of TMR elements MTJ1, MTJ2, MTJ3, and MTJ4 in the block BKjn may all be the same.
[0331]
42 to 44 show structural examples of the TMR element.
The TMR element shown in the example of FIG. 42 has the most basic structure, and has two ferromagnetic layers and a tunnel barrier layer sandwiched between them.
[0332]
Of the two ferromagnetic layers, an antiferromagnetic layer for fixing the magnetization direction is added to the fixed layer (pinned layer) in which the magnetization direction is fixed. Of the two ferromagnetic layers, the magnetization direction of the free layer (storage layer) that can freely change the magnetization direction is determined by the combined magnetic field formed by the write word line and the write bit line.
[0333]
The TMR element shown in the example of FIG. 43 is provided with two tunnel barrier layers in the TMR element for the purpose of increasing the bias voltage as compared with the TMR element of the example of FIG.
[0334]
It can also be said that the TMR element in FIG. 43 has a structure (double junction structure) in which two TMR elements in FIG. 42 are connected in series.
[0335]
In this example, the TMR element has three ferromagnetic layers, and a tunnel barrier layer is disposed between them. An antiferromagnetic layer is added to each of the two ferromagnetic layers (pinned layers) at both ends. Of the three ferromagnetic layers, the free layer (memory layer) that can freely change the direction of magnetization is the middle ferromagnetic layer.
[0336]
The TMR element shown in the example of FIG. 44 is configured so that the memory retention characteristic is not deteriorated while reducing the write reversal magnetic field as compared with the TMR element of the example of FIG.
[0337]
The TMR element of this example is obtained by replacing the storage layer of the TMR element of FIG. 42 with a storage layer composed of two ferromagnetic layers and a nonmagnetic metal layer (for example, aluminum) sandwiched between them. I can say that.
[0338]
The memory layer of the TMR element has a three-layer structure including two ferromagnetic layers and a nonmagnetic metal layer sandwiched between them, so that the reversal magnetic field is reduced and the memory retention characteristic is not deteriorated. It becomes possible to. That is, the write reversal magnetic field can be lowered by reducing the thickness of the two ferromagnetic layers constituting the storage layer.
[0339]
In the case of a single layer structure, it becomes vulnerable to thermal fluctuations, and erroneous writing is likely to occur. In the case of a three-layer structure, thermal fluctuations occur due to the magnetic coupling of two ferromagnetic layers sandwiching a nonmagnetic metal. Therefore, it is possible to realize a TMR structure with excellent memory retention characteristics that is unlikely to cause erroneous writing.
[0340]
(2) When applying the batch read operation principle
In this case, the structures of the plurality of TMR elements connected in series, parallel, or series-parallel in the block are different from each other.
[0341]
Specifically, the resistance values of the respective TMR elements when the magnetization states of the plurality of TMR elements in the block are all parallel (for the definition of parallel and antiparallel, see the column of the prior art) are different from each other. Thus, the structure of a plurality of TMR elements is determined.
[0342]
・ Structural example 1
FIG. 45 shows an example of the TMR element MTJ1.
The TMR element MTJ1 is composed of a basic unit. The basic unit is a unit comprising a tunnel barrier, a ferromagnetic layer (memory layer) disposed on one side of the tunnel barrier, and a ferromagnetic layer and an antiferromagnetic layer disposed on the other side of the tunnel barrier. It is.
[0343]
Since the ferromagnetic layer disposed on the other side of the tunnel barrier is in contact with the antiferromagnetic layer, its magnetization direction is fixed. The ferromagnetic layer disposed on the other side of the tunnel barrier and the antiferromagnetic layer in contact therewith constitute a pinned layer.
[0344]
The resistance value of the TMR element MTJ1 realized by this structure is R.
[0345]
FIG. 46 shows an example of the TMR element MTJ2.
The TMR element MTJ2 is composed of two basic units. However, one ferromagnetic layer (memory layer) is shared between the two basic units. That is, a pinned layer composed of a ferromagnetic layer and an antiferromagnetic layer is disposed on one side of a ferromagnetic layer as a storage layer via a tunnel barrier, and also on the other side of the ferromagnetic layer as a storage layer. A pinned layer including a ferromagnetic layer and an antiferromagnetic layer is disposed via the tunnel barrier.
[0346]
The TMR element MTJ2 has a structure in which a tunnel barrier and a pinned layer (a ferromagnetic layer and an antiferromagnetic layer) are symmetrically arranged with respect to a ferromagnetic layer as a storage layer.
[0347]
The resistance value of the TMR element MTJ2 realized by this structure is 2 × R.
[0348]
FIG. 47 shows an example of the TMR element MTJ3.
The TMR element MTJ3 is composed of four basic units. In addition, it can be said that the TMR element MTJ3 includes two TMR elements MTJ2 connected in series. That is, the TMR element MTJ3 has a structure in which two TMR elements MTJ2 are connected in series and an antiferromagnetic layer at the connection portion is shared by the two TMR elements MTJ2.
[0349]
In the TMR element MTJ3, there are two storage layers, but the same data is naturally stored in these two storage layers. That is, 1-bit data is stored in the TMR element MTJ3 by two storage layers.
[0350]
The resistance value of the TMR element MTJ3 realized by this structure is 4 × R.
[0351]
FIG. 48 shows an example of the TMR element MTJ4.
The TMR element MTJ4 is composed of eight basic units. In addition, it can be said that the TMR element MTJ4 has two TMR elements MTJ3 connected in series. That is, the TMR element MTJ4 has a structure in which two TMR elements MTJ3 are connected in series and an antiferromagnetic layer at the connection portion is shared by the two TMR elements MTJ3.
[0352]
In the TMR element MTJ4, there are four storage layers, but the same data is naturally stored in these four storage layers. That is, 1-bit data is stored in the TMR element MTJ4 by the four storage layers.
[0353]
The resistance value of the TMR element MTJ4 realized by this structure is 8 × R.
[0354]
・ Structural example 2
In Structural Example 1, the technology for changing the resistance value of the TMR element by changing the number of tunnel barriers according to the number of basic units (MTJ elements) has been described. However, in this case, since the number of basic units is different for each TMR element in one block, the thickness varies.
[0355]
Therefore, in Structural Example 2, in order to solve the problem that the thickness of each TMR element in one block is different, all the TMR elements in one block are composed of the same number of units, and the thicknesses are the same. To.
[0356]
For example, when one block is composed of four TMR elements, each TMR element is composed of eight units.
[0357]
The resistance value of the TMR element is adjusted by making some of the plurality of units constituting the TMR element dummy units. The dummy unit is a unit in which the tunnel barrier of the basic unit is changed to a nonmagnetic metal.
[0358]
In this way, for example, when the resistance value of one basic unit is R, the resistance value of the TMR element composed of eight basic units is 8 × R (eight tunnel barriers). In addition, the resistance value of the TMR element in which four of the eight units are basic units and the other four are dummy units is 4 × R (four tunnel barriers).
[0359]
Furthermore, the resistance value of the TMR element, in which two of the eight units are basic units and the other six are dummy units, is 2 × R (two tunnel barriers), and one of the eight units is a basic unit. Thus, the resistance value of the TMR element in which the other seven are dummy units is R (one tunnel barrier).
[0360]
The resistance value between the two ferromagnetic layers sandwiching the nonmagnetic metal is sufficiently smaller than the resistance value between the two ferromagnetic layers sandwiching the tunnel barrier. For this reason, the number of units (total of the basic unit and dummy unit) constituting the TMR element is made the same, the thicknesses of all the TMR elements are made the same, and the ratio of the resistance values of the TMR elements in one block is set. For example, it can be set to 1: 2: 4: 8.
[0361]
The tunnel barrier of the basic unit is made of alumina, for example. Alumina is formed by oxidizing aluminum.
[0362]
Therefore, after forming aluminum, if the unit is formed without oxidizing the aluminum, the unit becomes a dummy unit. Further, if aluminum is formed and then oxidized to alumina, the finally completed unit becomes a basic unit of resistance value R.
[0363]
FIG. 49 shows an example of the TMR element MTJ1.
The TMR element MTJ1 is composed of eight units. One of the eight units is a basic unit having a tunnel barrier, and the remaining seven are dummy units having no tunnel barrier (having a nonmagnetic metal).
[0364]
Therefore, the resistance value of the TMR element MTJ1 realized by this structure is the resistance value R for one unit (or tunnel barrier).
[0365]
FIG. 50 shows an example of the TMR element MTJ2.
The TMR element MTJ2 is composed of eight units. Two of the eight units are basic units having a tunnel barrier, and the remaining six are dummy units having a tunnel barrier (having a nonmagnetic metal).
[0366]
Therefore, the resistance value of the TMR element MTJ2 realized by this structure is the resistance value 2 × R for two units (or tunnel barriers).
[0367]
FIG. 51 shows an example of the TMR element MTJ3.
The TMR element MTJ3 is composed of eight units. Four of the eight units are basic units having a tunnel barrier, and the remaining four are dummy units having a tunnel barrier (having a nonmagnetic metal).
[0368]
Therefore, the resistance value of the TMR element MTJ3 realized by this structure is the resistance value 4 × R for four units (or tunnel barriers).
[0369]
FIG. 52 shows an example of the TMR element MTJ4.
The TMR element MTJ4 is composed of eight units. All eight units are basic units with tunnel barriers.
[0370]
Therefore, the resistance value of the TMR element MTJ4 realized by this structure is the resistance value 8 × R for eight units (or tunnel barriers).
[0371]
・ Other
In this example, when the magnetization states of the plurality of TMR elements in the block are all the same, the resistance values of the plurality of TMR elements in the block are made different from each other by changing the number of tunnel barriers.
[0372]
However, this structure is only an example, and various changes can be made. For example, regarding the TMR elements MTJ1, MTJ2, and MTJ3 in FIGS. 49 to 52, the position of the basic unit having the tunnel barrier and the position of the dummy unit having the nonmagnetic metal are arbitrarily changed unless the number of tunnel barriers is changed. be able to.
[0373]
(3) Summary
The structure example of the TMR element has been described above. However, the structure of the TMR element is not particularly limited with respect to the present invention (circuit structure, device structure, read operation principle, read circuit, and manufacturing method). The structural example described above is merely shown as a representative example of the structure of the TMR element.
[0374]
4). Read operation principle
In the magnetic random access memory, when only the data of the selected TMR element can be read, (1) the normal read operation principle in which the read data is detected by the sense amplifier is applied. When the data of all TMR elements in the block are read in a mixed form (when the read bit line is shared), (2) the so-called destructive read operation principle or (3) the collective read operation principle Applied.
[0375]
A magnetic random access memory to which the destructive read operation principle can be applied is described in detail, for example, in Japanese Patent Application No. 2001-350013. A magnetic random access memory to which the collective reading operation principle can be applied is described in detail in, for example, Japanese Patent Application No. 2001-365236.
[0376]
5. Read circuit
A circuit example of a read circuit for realizing the read operation principle of the present invention will be described.
[0377]
(1) When applying the destructive read operation principle
(1) Circuit example 1
FIG. 53 shows Circuit Example 1 of the read circuit of the magnetic random access memory.
The plurality of TMR elements are connected in parallel to each other, one end of which is connected to a ground point, and the other end is connected to a node n1 via an N-channel MOS transistor N7 (SW) as a column selection switch. The TMR element group shown corresponds to one column in the reference examples and the improved examples 1, 2 and 5, and corresponds to one block in one column in the improved examples 3, 4 and 6.
[0378]
The potential of the node n1 is set to the clamp potential Vclamp by the clamp circuit. The clamp circuit is composed of an operational amplifier OP1 and an N-channel MOS transistor N8.
[0379]
N channel MOS transistor N8 is arranged between node n1 and current mirror circuit M1. For example, the operational amplifier OP1 controls the gate potential of the N-channel MOS transistor N8 so that the potential of the node n1 becomes equal to the clamp potential Vclamp.
[0380]
The role of the clamp circuit is to adjust the voltage across the TMR elements in one column or one block.
[0381]
That is, for example, when the ground potential is applied to one end of the TMR element, if the potential at the other end of the TMR element becomes too large, the MR ratio of the TMR element becomes small. The small MR ratio of the TMR element means that the difference between the resistance value of the TMR element in the “1” state and the resistance value of the TMR element in the “0” state is small. That is, the margin for determining “1” and “0” at the time of reading is reduced.
[0382]
In order to prevent this, in this example, the clamp circuit is used to adjust the potential at the other end of the TMR element, that is, the voltage across the TMR element, so that the MR ratio of the TMR element does not become small.
[0383]
The current mirror circuit M1 plays a role of causing a current equal to the total value of read currents flowing through the plurality of TMR elements to flow through the N-channel MOS transistor N9. At this time, the potential of the node n2 (for example, initial data) is stored in the storage circuit 43 by the transfer gate circuit TG1.
[0384]
ON / OFF of the transfer gate circuit TG1 is controlled by control signals READ1S and bREAD1S. The control signal READ1S is a signal that becomes “H” during the first read operation (when initial data is read). The control signal bREAD1S is an inverted signal having a value opposite to the value of the control signal READ1S.
[0385]
When the control signal READ1S is “H” (during the first read operation), the potential of the node n2 is input to the inverter circuit I7 via the transfer gate circuit TG1. The output signal of the inverter circuit I7 is input to the negative input terminal of the operational amplifier OP2. The output signal of the operational amplifier OP2 is input to the inverter circuit I8, and the output signal of the inverter circuit I8 is input to the plus side input terminal of the operational amplifier OP2.
[0386]
For example, the operational amplifier OP2 sets the gate potential of the N-channel MOS transistor in the inverter circuit I8 so that the input potential input to the negative input terminal and the input potential input to the positive input terminal are equal to each other. Control. Therefore, as a result, the current flowing through the inverter circuit I8 that receives the output signal of the operational amplifier OP2 becomes initial data (cell data).
[0387]
The transfer gate circuit TG2 is connected between the output terminal of the operational amplifier OP2 and the input terminal of the inverter circuit I7. When the first read operation is finished, the control signal READ1S becomes “L”, and the control signal bREAD1S becomes “H”. As a result, the initial data is latched in the storage circuit 43.
[0388]
The positive input terminal of the sense amplifier SA is connected to the node n2, and the negative input terminal is connected to the output terminal n3 of the operational amplifier OP2. When determining the data of the selected TMR element, the sense amplifier SA compares the potential of the node n2 with the potential of the output terminal n3 of the operational amplifier OP2.
[0389]
That is, the potential of the node n1 represents the second read result (comparison data), and the potential of the output terminal n3 of the operational amplifier OP2 represents the first read result (initial data).
[0390]
By the way, when the number of TMR elements connected in parallel in one column or one block increases, the value of the signal current with respect to the value of the read current becomes very small, and this minute signal current can be detected by the sense amplifier. It becomes difficult.
[0390]
Therefore, in this example, an additional current generation unit 42 is provided.
[0392]
The additional current generator 42 has a current source Is. The constant current generated by the current source Is is supplied to the TMR element by the current mirror circuit M2.
[0393]
That is, in the circuit example 6, if the cell current flowing through the TMR elements connected in parallel in one column or one block is Icell, the current flowing through the current mirror circuit M1, that is, the current Isense flowing through the N-channel MOS transistor N9 is , Isense = Icell-Is.
[0394]
Thereby, since the value of the signal current with respect to the value of the read current can be increased, the detection sensitivity of the signal current by the sense amplifier can be improved.
[0395]
(2) Circuit example 2
FIG. 54 shows Circuit Example 2 of the read circuit of the magnetic random access memory.
This circuit example 2 is a modification of the circuit example 1. The circuit example 2 is characterized by the memory circuit 43 as compared to the circuit example 1. That is, in the circuit example 1, the memory circuit 43 has the two inverter circuits I7 and I8 and the operational amplifier OP2. However, in the circuit example 2, the memory circuit 43 does not have the operational amplifier and has four stages. Current mirror circuits I9, I9 ', I10 and I11 are provided.
[0396]
That is, in the circuit example 2, the initial data is latched in the memory circuit 43 using the current mirror circuit without using the operational amplifier.
[0397]
For example, during the first read operation (when initial data is read), the control signal READ1S is “H”, so that the potential (initial data) of the node n1 is four-stage current mirror circuits I9, I9 ′, I10. , I11.
[0398]
That is, since I9, I9 ', I10, and I11 constitute a current mirror circuit, the currents flowing from the power supply terminal to the ground terminal in each stage have the same value. Therefore, if the MOS transistors constituting the current mirror circuits I9, I9 ′, I10, I11 are designed to operate in the saturation region, the gate potential of the N-channel MOS transistor in the current mirror circuit I9, that is, the potential of the node n1. Is transferred to node n3.
[0399]
When the first read operation ends, the control signal READ1S becomes “L” and the control signal bREAD1S becomes “H”, so that the initial data transferred to the node n3 is latched in the storage circuit 43.
[0400]
(3) Circuit example 3
FIG. 55 shows Circuit Example 3 of the read circuit of the magnetic random access memory.
This circuit example 3 is also a modification of the circuit example 1 and is characterized by the memory circuit 43 as compared with the circuit example 1. That is, in the circuit example 3, the storage circuit 43 is configured by the capacitor C1.
[0401]
In this example, for example, the potential (initial data) of the node n2 is dynamically stored in the capacitor C1. For this reason, for example, the period from the first reading to the second reading needs to be shorter than the period during which the capacitor C1 continues to hold data.
[0402]
The period during which the capacitor C1 continues to hold data is, for example, several milliseconds, as well studied in the field of DRAM (Dynamic Random Access Memory). Therefore, the capacitor C1 can be used for the memory circuit 43 if the period from the first reading to the second reading is shorter than several milliseconds.
[0403]
(4) Specific examples of sense amplifiers
A specific example of the sense amplifier SA used in the circuit examples 1, 2, and 3 will be described. The configuration of the sense amplifier SA is determined by the value of trial data to be written to the selected TMR element during the destructive read operation.
[0404]
・ When trial data is “1”
FIG. 56 shows an example of the sense amplifier when the trial data is “1”. The sense amplifier SA includes, for example, three differential amplifiers DI1, DI2, DI3 and a NAND circuit ND5.
[0405]
The first-stage differential amplifier DI1 compares the potential of the node n2 (for example, comparison data) in FIGS. 53 to 55 with the potential of the node n3 (for example, initial data). The differential amplifier DI1 outputs two output potentials based on the two input potentials. The difference between the two output potentials of the differential amplifier DI1 is determined based on the difference between the two input potentials.
[0406]
A potential based on the potential of the node n2 is input to the plus side input terminal of the differential amplifier DI2, and the reference potential VrefH is input to the minus side input terminal. The differential amplifier DI2 outputs “H” when the potential input to the plus side input terminal is higher than the reference potential VrefH, and outputs “L” when the potential is lower than the reference potential VrefH.
[0407]
A potential based on the potential of the node n3 is input to the minus side input terminal of the differential amplifier DI3, and a reference potential VrefL is input to the plus side input terminal. The differential amplifier DI3 outputs “H” when the potential input to the negative input terminal is smaller than the reference potential VrefL, and outputs “L” when larger than that.
[0408]
For example, when the data of the selected TMR element is “0” and the trial data is “1”, the comparison data read in the second read operation, that is, the potential of the node n2 is changed in the first read operation. The read initial data, that is, the potential of the node n3 becomes higher.
[0409]
At this time, the potential input to the plus side input terminal of the differential amplifier DI2 is higher than the reference potential VrefH input to the minus side input terminal, so that the output signal of the differential amplifier DI2 is “H”. Become. In addition, since the potential input to the negative input terminal of the differential amplifier DI3 is lower than the reference potential VrefL input to the positive input terminal, the output signal of the differential amplifier DI3 is also “H”. .
[0410]
Therefore, the output signal of the NAND circuit ND5 is “L”, that is, the output signal of the sense amplifier SA is “0” (“L” = “0”). That is, it is determined that the data of the selected TMR element is “0”.
[0411]
For example, when the data of the selected TMR element is “1” and the trial data is “1”, the comparison data read in the second read operation, that is, the potential of the node n2 and the first read The initial data read by the operation, that is, the potential of the node n3 is substantially the same.
[0412]
At this time, the differential amplifier DI1 outputs two output potentials based on a small potential difference between the nodes n2 and n3.
[0413]
However, since the potential input to the positive input terminal of the differential amplifier DI2 does not become higher than the reference potential VrefH input to the negative input terminal, the output signal of the differential amplifier DI2 is “L”. " Further, since the potential input to the negative input terminal of the differential amplifier DI3 does not become lower than the reference potential VrefL input to the positive input terminal, the output signal of the differential amplifier DI3 is also “L”. "
[0414]
Therefore, the output signal of the NAND circuit ND5 is “H”, that is, the output signal of the sense amplifier SA is “1” (“H” = “1”). That is, it is determined that the data of the selected TMR element is “1”.
[0415]
FIG. 57 shows an example of the first-stage differential amplifier of the sense amplifier of FIG.
[0416]
This differential amplifier DI1 is characterized in that a resistor Rr having an appropriate resistance value is connected between two output terminals.
[0417]
In this way, by connecting a resistor between the two output terminals of the differential amplifier DI1, when the data of the selected TMR element and the trial data are the same, that is, there is almost no difference between the two input potentials. If not, the differential amplifier DI1 amplifies the difference and does not output it. The differential amplifier DI1 amplifies and outputs the difference only when there is a clear difference between the two input potentials.
[0418]
58 shows another example of the first-stage differential amplifier of the sense amplifier of FIG.
[0419]
This differential amplifier DI1 is characterized in that a depletion type MOS transistor QD is connected between two output terminals.
[0420]
The depletion type MOS transistor QD has the same function as the resistor Rr in FIG. That is, when the data of the selected TMR element and the trial data are the same, that is, when there is almost no difference between the two input potentials, the differential amplifier DI1 amplifies the difference and does not output it. . The differential amplifier DI1 amplifies and outputs the difference only when there is a clear difference between the two input potentials.
[0421]
・ When trial data is “0”
FIG. 59 shows an example of the sense amplifier when the trial data is “0”. The sense amplifier SA includes, for example, three differential amplifiers DI1, DI2, DI3 and a NOR circuit NR3.
[0422]
The first-stage differential amplifier DI1 compares the potential of the node n2 (for example, comparison data) in FIGS. 53 to 55 with the potential of the node n3 (for example, initial data). The differential amplifier DI1 outputs two output potentials based on the two input potentials. The difference between the two output potentials of the differential amplifier DI1 is determined based on the difference between the two input potentials.
[0423]
A potential based on the potential of the node n2 is input to the plus side input terminal of the differential amplifier DI2, and the reference potential VrefL is input to the minus side input terminal. The differential amplifier DI2 outputs “L” when the potential input to the plus side input terminal is smaller than the reference potential VrefL, and outputs “H” when larger than that.
[0424]
A potential based on the potential of the node n3 is input to the minus side input terminal of the differential amplifier DI3, and a reference potential VrefH is input to the plus side input terminal. The differential amplifier DI3 outputs “L” when the potential input to the negative input terminal is higher than the reference potential VrefH, and outputs “H” when it is lower than the reference potential VrefH.
[0425]
For example, when the data of the selected TMR element is “1” and the trial data is “0”, the comparison data read in the second read operation, that is, the potential of the node n2 is changed in the first read operation. The read initial data, that is, the potential of the node n3 becomes lower.
[0426]
At this time, since the potential input to the positive input terminal of the differential amplifier DI2 is lower than the reference potential VrefL input to the negative input terminal, the output signal of the differential amplifier DI2 is “L”. Become. Further, since the potential input to the negative input terminal of the differential amplifier DI3 is higher than the reference potential VrefH input to the positive input terminal, the output signal of the differential amplifier DI3 is also “L”. .
[0427]
Accordingly, the output signal of the NOR circuit NR3 is “H”, that is, the output signal of the sense amplifier SA is “1” (“H” = “1”). That is, it is determined that the data of the selected TMR element is “1”.
[0428]
For example, when the data of the selected TMR element is “0” and the trial data is “0”, the comparison data read in the second read operation, that is, the potential of the node n2 and the first read The initial data read by the operation, that is, the potential of the node n3 is substantially the same.
[0429]
At this time, the differential amplifier DI1 outputs two output potentials based on a small potential difference between the nodes n2 and n3.
[0430]
However, since the potential input to the positive input terminal of the differential amplifier DI2 does not become lower than the reference potential VrefL input to the negative input terminal, the output signal of the differential amplifier DI2 is “H " Further, since the potential input to the negative input terminal of the differential amplifier DI3 does not become higher than the reference potential VrefH input to the positive input terminal, the output signal of the differential amplifier DI3 is also “H”. "
[0431]
Therefore, the output signal of the NAND circuit ND5 is “L”, that is, the output signal of the sense amplifier SA is “0” (“L” = “0”). That is, it is determined that the data of the selected TMR element is “0”.
[0432]
Note that the differential amplifier DI1 having the configuration shown in FIG. 57 or 58 can also be used for the first-stage differential amplifier DI1 of the sense amplifier of FIG.
[0433]
Thereby, when the data of the selected TMR element and the trial data are the same, that is, when there is almost no difference between the two input potentials, the sense amplifier amplifies the difference and does not output it. The sense amplifier amplifies and outputs the difference only when there is a clear difference between the two input potentials.
[0434]
(5) Specific examples of operational amplifiers
FIG. 60 shows a specific example of the operational amplifier OP1 shown in FIGS.
[0435]
The clamp potential Vclamp is input to the positive input terminal of the operational amplifier OP1, and the potential of the node n1 is input to the negative input terminal. When the enable signal Enable becomes “H”, an output signal Out is output so that the potential of the node n1 becomes equal to the clamp potential Clamp.
[0436]
FIG. 61 shows a specific example of the operational amplifier OP2 of FIG.
[0437]
The output signal of the inverter circuit I8 of FIG. 53 is input to the positive side input terminal of the operational amplifier OP2, and the output signal of the inverter circuit I7 is input to the negative side input terminal thereof. When the enable signal Enable becomes “H”, an output signal Out is output so that the output signal of the inverter circuit I7 becomes equal to the output signal of the inverter circuit I8.
[0438]
(6) Specific example of the current source of the additional current generator
FIG. 62 shows an example of a current source of the additional current generator.
For example, the current source Is of the additional current generation unit 42 can have the same configuration as that of the memory cell array unit. That is, the current source Is can be composed of a plurality of TMR elements connected in parallel, a clamp circuit, and an N-channel MOS transistor.
[0439]
Here, the number of TMR elements in the current source Is is preferably smaller than the number of TMR elements connected in parallel in one column or one block of the memory cell array.
[0440]
In this example, the TMR element is used to configure the additional current generating unit 42. However, for example, a BGR circuit or the like may be used instead.
[0441]
(7) Operation of circuit examples 1, 2, and 3
・ First read operation
In the first read operation, initial data is read.
[0442]
A column address signal is input, and the column selection switch N7 (SW) is turned on. The operational amplifier OP1 controls the gate potential of the N-channel MOS transistor N8 so that the potential of the node n1 becomes equal to the clamp potential Vclamp.
[0443]
At this time, the read current flows from the power supply terminal VDD to the ground point via the transistors M7 and M8 and the plurality of TMR elements. The current mirror circuit M1 plays a role of flowing a current equal to the read current to the N-channel MOS transistor N9.
[0444]
Accordingly, a potential (initial data) corresponding to the combined resistance of the plurality of TMR elements appears at the node n2.
[0445]
The control signal READ1S is “H” during the first read operation. That is, the transfer gate circuit TG1 is in an on state, and the transfer gate circuit TG2 is in an off state. Therefore, the potential of the node n2 is input to the storage circuit 43 via the transfer gate circuit TG1.
[0446]
In the example of FIG. 53, the operational amplifier OP2 controls the gate potential of the N-channel MOS transistor in the inverter circuit I8 so that the minus side input potential and the plus side input potential are equal to each other. As a result, the current flowing through the inverter circuit I8 becomes initial data (cell data).
[0447]
In the example of FIG. 54, the potential of the output node n3 of the inverter circuit I11 becomes initial data (cell data). In the example of FIG. 55, the potential at one end n3 of the capacitor C1 becomes initial data (cell data).
[0448]
When the first read operation is finished, the control signal READ1S becomes “L”, and the control signal bREAD1S becomes “H”. As a result, the initial data is latched in the storage circuit 43.
[0449]
・ Second read operation and data judgment operation
After writing trial data to the selected TMR element (normal destructive read operation) or simultaneously with writing (improved destructive read operation), a second read operation is performed to read comparison data.
[0450]
A column address signal is input, and the column selection switch N7 (SW) is turned on. The operational amplifier OP1 controls the gate potential of the N-channel MOS transistor N8 so that the potential of the node n1 becomes equal to the clamp potential Vclamp.
[0451]
At this time, the read current flows from the power supply terminal VDD to the ground point via the transistors M7 and M8 and the plurality of TMR elements. The current mirror circuit M1 plays a role of flowing a current equal to the read current to the N-channel MOS transistor N9.
[0452]
Therefore, a potential (comparison data) corresponding to the combined resistance of the plurality of TMR elements appears at the node n2.
[0453]
At this time, the potential of the node n2 is input to the plus side input terminal of the sense amplifier SA, and the potential of the node n3 of the memory circuit 43 is input to the minus side input terminal. As a result, the sense amplifier SA determines the data value of the selected TMR element based on the potential of the node n2 and the potential of the node n3.
[0454]
(2) When applying the batch read operation principle
In the collective read operation principle, a read potential Vtotal corresponding to the combined resistance value of the plurality of TMR elements in the read block appears on the read bit line BLj during the read operation. This combined resistance value corresponds to the number of combinations of data values of the TMR elements when the number of TMR elements in the read block is N (N is a plurality).^NThere are only streets.
[0455]
Therefore, if the read potential Vtotal appearing on the read bit line BLj is detected by a read circuit (including a sense amplifier), the data of the TMR elements in the read block can be read easily at a time.
[0456]
(1) Sense amplifier
FIG. 63 shows a circuit example of a read circuit according to the present invention.
This read circuit is composed of an analog / digital converter (A / D converter) as a sense amplifier.
[0457]
One end of the block BKjn composed of four TMR elements connected in series is connected to the power supply terminal via the N-channel MOS transistor SWA and the P-channel MOS transistor Px2, and the other end is connected to the ground terminal. The four TMR elements in the block BKjn may be connected in parallel instead of being connected in series.
[0458]
The first current path is a path from the power supply terminal to the ground terminal via the MOS transistors Px2 and SWA and the plurality of TMR elements.
[0459]
One end of the 14 resistance elements having the resistance value ΔR is connected to the power supply terminal via the P-channel MOS transistor Px3, and the other end is connected to the ground terminal via the resistance element having the resistance value 15R + ΔR / 2. Connected. The second current path is a path from the power supply terminal to the ground terminal via the MOS transistor Px3 and the plurality of resistance elements.
[0460]
Here, R and ΔR have the same meaning as R and ΔR described in the column of the read operation principle.
[0461]
P-channel MOS transistors Px1, Px2, and Px3 form a current mirror circuit. For this reason, the constant current generated by the constant current source Ix flows through the first and second current paths described above.
[0462]
The current flowing through the first current path becomes a read current, and this read current flows through the plurality of TMR elements. As a result, the read potential Vtotal corresponding to the data value (combined resistance value) of the TMR elements in the block BKjn appears at the node nr. On the other hand, when a current flows through the second current path, a predetermined reference potential appears at connection points nx0, nx1,.
[0463]
The differential amplifiers DI0, DI2,... DI13, DI14 compare the read potential Vtotal of the node nr with a predetermined reference potential and output the comparison results as output signals O0b1, O1b2,... O13b14, O14b15. .
[0464]
For example, the reference potential of the node nx0 is input to the plus side input terminal of the differential amplifier DI0, and the read potential Vtotal of the node nr is input to the minus side input terminal. Similarly, the reference potential of the node nx1 is input to the plus side input terminal of the differential amplifier DI1, the read potential Vtotal of the node nr is input to the minus side input terminal, and the plus side input of the differential amplifier DI14 is input. The reference potential of the node nx14 is input to the terminal, and the read potential Vtotal of the node nr is input to the negative input terminal.
[0465]
Since the detailed operation of the sense amplifier is disclosed in Japanese Patent Application No. 2001-365236, it is omitted here.
[0466]
(2) Logic circuit
Next, based on the output signals O0b1, O1b2,... O13b14, O14b15 of the sense amplifier (A / D converter), the data values of the TMR elements MTJ1, MTJ2, MTJ3, MTJ4 in the read block are actually determined. The logic circuit will be described.
[0467]
FIG. 64 shows an example of a logic circuit that determines the data value of the TMR element MTJ4 based on the output signal of the A / D converter.
[0468]
The data value of the TMR element MTJ4 is determined based on the output signal O7b8 among the output signals O0b1, O1b2,... O13b14, O14b15 of the A / D converter.
[0469]
Since the data value of the TMR element MTJ4 can be determined only from the value of the output signal O7b8 as described above, the logic circuit for determining the data value of the TMR element MTJ4 is configured by inverters IV1 and IV2 connected in series.
[0470]
FIG. 65 shows an example of a logic circuit that determines the data value of the TMR element MTJ3 based on the output signal of the A / D converter.
[0471]
The data value of the TMR element MTJ3 is determined based on the output signals O3b4, O7b8, O11b12 among the output signals O0b1, O1b2,... O13b14, O14b15 of the A / D converter.
[0472]
Since the data value of the TMR element MTJ3 can be determined from the values of the output signals O3b4, O7b8, and O11b12 as described above, the logic circuit that determines the data value of the TMR element MTJ3 includes the inverters IV3 and IV4 and the NOR gate circuits NR1, It is composed of NR2.
[0473]
For example, when O3b4 = “1”, the data value of the TMR element MTJ3 is determined to be “1”. When O3b4 = “0” and O7b8 = “1”, the data value of the TMR element MTJ3 is determined as “0”, and O3b4 = “0”, O7b8 = “0”, and O11b12 = “1”. At this time, the data value of the TMR element MTJ3 is determined to be “1”. When O3b4 = “0”, O7b8 = “0”, and O11b12 = “0”, the data value of the TMR element MTJ3 is “0”. It is judged.
[0474]
FIG. 66 shows an example of a logic circuit that determines the data value of the TMR element MTJ2 based on the output signal of the A / D converter.
[0475]
The data value of the TMR element MTJ2 is determined based on the output signals O1b2, O3b4, O5b6, O7b8, O9b10, O11b12, and O13b14 among the output signals O0b1, O1b2,... O13b14, O14b15 of the A / D converter.
[0476]
The logic circuit that determines the data value of the TMR element MTJ2 is composed of inverters IV5, IV6, IV7, IV8 and NOR gate circuits NR3, NR4, NR5, NR6.
[0477]
For example, when O1b2 = “1”, the data value of the TMR element MTJ2 is determined to be “1”. When O1b2 = “0” and O3b4 = “1”, the data value of the TMR element MTJ2 is determined to be “0”, and O1b2 = “0”, O3b4 = “0”, and O5b6 = “1”. In this case, the data value of the TMR element MTJ2 is determined to be “1”.
[0478]
FIG. 67 shows an example of a logic circuit that determines the data value of the TMR element MTJ1 based on the output signal of the A / D converter.
[0479]
The data value of the TMR element MTJ1 is determined based on all output signals O0b1, O1b2,... O13b14, O14b15 of the A / D converter.
[0480]
The logic circuit for determining the data value of the TMR element MTJ1 includes inverters IV9, IV10, IV11, IV12, IV13, IV14, IV15, IV16 and NOR gate circuits NR7, NR8, NR9, NR10, NR11, NR12, NR13, NR14. Is done.
[0481]
For example, when O0b1 = “1”, the data value of the TMR element MTJ1 is determined to be “1”. When O0b1 = “0” and O1b2 = “1”, the data value of the TMR element MTJ1 is determined as “0”, and O0b1 = “0”, O1b2 = “0”, and O2b3 = “1”. In this case, the data value of the TMR element MTJ1 is determined to be “1”.
[0482]
The output signal patterns of the A / D converter output signals O0b1, O1b2,... O13b14, O14b15 are all “1”, all “0”, and “0” and “1”. There are three ways of existence.
[0483]
In addition, when “0” and “1” exist, there is always a boundary between “0” and “1”, and output signals on one side of the boundary are all “0” and on the other side. The output signals are all “1”.
[0484]
6). Circuit examples other than readout circuit
A circuit example other than the read circuit, that is, a write word line driver / sinker circuit example, a write bit line driver / sinker circuit example, a read word line driver circuit example, and a column decoder circuit example will be described.
[0485]
(1) Write word line driver / sinker
FIG. 68 shows a circuit example of the write word line driver / sinker.
In this example, as described in “2. Cell array structure”, it is assumed that there are TMR elements and three write word lines stacked in four stages in one row. In the figure, only one row of the write word line driver / sinker is shown.
[0486]
The write word line driver 23A-0 includes P channel MOS transistors QP15, QP16, QP17 and NAND gate circuits ND1, ND2, ND3. The write word line sinker 24-0 includes N channel MOS transistors QN15, QN16, and QN17.
[0487]
P-channel MOS transistor QP15 is connected between the power supply terminal and upper write word line WWL2. The output signal of NAND gate circuit ND1 is supplied to the gate of P channel MOS transistor QP15. N-channel MOS transistor QN15 is connected between upper write word line WWL2 and the ground terminal.
[0488]
When the output signal of the NAND gate circuit ND1 is “0”, a write current flows through the write word line WWL2.
[0489]
P-channel MOS transistor QP16 is connected between the power supply terminal and middle-stage write word line WWL1. The output signal of NAND gate circuit ND2 is supplied to the gate of P channel MOS transistor QP16. N-channel MOS transistor QN16 is connected between middle-stage write word line WWL1 and the ground terminal.
[0490]
When the output signal of the NAND gate circuit ND2 is “0”, a write current flows through the write word line WWL1.
[0491]
P-channel MOS transistor QP17 is connected between the power supply terminal and lower write word line WWL0. The output signal of NAND gate circuit ND3 is supplied to the gate of P channel MOS transistor QP17. N channel MOS transistor QN17 is connected between lower write word line WWL0 and the ground terminal.
[0492]
When the output signal of the NAND gate circuit ND3 is “0”, a write current flows through the write word line WWL0.
[0493]
The lower 2 bits of the row address signal of a plurality of bits are respectively input to the NOR gate circuit NR15 and the exclusive OR gate circuit Ex-OR1. The lower 2 bits are used to select one of the three write word lines WWL0, WWL1, and WWL2 in the selected row.
[0494]
The output signal of the NOR gate circuit NR15 is input to the NAND gate circuit ND1, and the output signal of the exclusive OR gate circuit Ex-OR1 is input to the NAND gate circuit ND2.
[0495]
In such a write word line driver / sinker, the write signal WRITE is “1” during the write operation. Also, one of the plurality of rows is selected based on the upper row address signal excluding the lower 2 bits among the plurality of row address signals. In the selected row, all the bits of the upper row address signal are “1”.
[0496]
In the selected row, it is determined whether or not a write current is supplied to the write word lines WWL0, WWL1, and WWL2 based on the lower two bits RA0 and RA1 among the row address signals of a plurality of bits.
[0497]
For example, in a write operation, when RA0 = “0” and RA1 = “0” in the selected row, all input signals of the NAND gate circuit ND1 are “1”. As a result, the output signal of the NAND gate circuit ND1 becomes “0”, the P-channel MOS transistor QP15 is turned on, and a write current flows through the write word line WWL2.
[0498]
When RA0 = "1" and RA1 = "1", all input signals to the NAND gate circuit ND3 are "1". As a result, the output signal of the NAND gate circuit ND3 becomes “0”, the P-channel MOS transistor QP17 is turned on, and a write current flows through the write word line WWL0.
[0499]
When RA0 and RA1 have different values (one is “0” and the other is “1”), the input signals of the NAND gate circuit ND2 are all “1”. As a result, the output signal of the NAND gate circuit ND2 becomes “0”, the P-channel MOS transistor QP16 is turned on, and a write current flows through the write word line WWL1.
[0500]
(2) Write bit line driver / sinker
FIG. 69 shows a circuit example of the write bit line driver / sinker.
In this example, it is assumed that there are TMR elements and two write bit lines stacked in four stages in one column. In the figure, only one column of the write bit line driver / sinker is shown.
[0501]
The write bit line driver / sinker 29A includes P-channel MOS transistors QP18 and QP19, N-channel MOS transistors QN18 and QN19, NAND gate circuits ND4 and ND5, AND gate circuits AD1 and AD2, NOR gate circuit NR16, and inverters IV17 and IV18. Is done.
[0502]
The write bit line driver / sinker 31 is composed of P-channel MOS transistors QP20 and QP21, N-channel MOS transistors QN20 and QN21, NAND gate circuits ND6 and ND7, AND gate circuits AD3 and AD4, NOR gate circuit NR17, and inverters IV19 and IV20. Is done.
[0503]
P channel MOS transistor QP18 is connected between the power supply terminal and lower write bit line BL01, and N channel MOS transistor QN18 is connected between lower write bit line BL00 and the ground terminal. P channel MOS transistor QP20 is connected between the power supply terminal and lower write bit line BL00, and N channel MOS transistor QN20 is connected between lower write bit line BL00 and the ground terminal.
[0504]
When the output signal of the NAND gate circuit ND4 is “0” and the output signal of the AND gate circuit AD3 is “1”, the write bit line BL00 is directed from the write bit line driver / sinker 29A to the write bit line driver / sinker 31. Write current flows.
[0505]
When the output signal of the NAND gate circuit ND6 is “0” and the output signal of the AND gate circuit AD1 is “1”, the write bit line BL00 is directed from the write bit line driver / sinker 31 to the write bit line driver / sinker 29A. Write current flows.
[0506]
P channel MOS transistor QP19 is connected between the power supply terminal and upper write bit line BL01, and N channel MOS transistor QN19 is connected between upper write bit line BL01 and the ground terminal. P-channel MOS transistor QP21 is connected between the power supply terminal and upper write bit line BL01, and N-channel MOS transistor QN21 is connected between upper write bit line BL01 and the ground terminal.
[0507]
When the output signal of the NAND gate circuit ND5 is “0” and the output signal of the AND gate circuit AD4 is “1”, the write bit line BL01 is directed from the write bit line driver / sinker 29A to the write bit line driver / sinker 31. Write current flows.
[0508]
When the output signal of the NAND gate circuit ND7 is “0” and the output signal of the AND gate circuit AD2 is “1”, the write bit line BL01 is directed from the write bit line driver / sinker 31 to the write bit line driver / sinker 29A. Write current flows.
[0509]
In such a write bit line driver / sinker, the write signal WRITE is “1” during the write operation. In the selected column, all the bits of the column address signal of a plurality of bits are “1”.
[0510]
In this example, one of the two write bit lines BL00 and BL01 in one column is selected using one bit RA1 of the row address signals of a plurality of bits. For example, when RA1 is “1”, the write bit line BL00 is selected, and when RA1 is “0”, the write bit line BL00 is selected.
[0511]
In addition, the direction of the write current flowing through the selected write bit line in the selected column is determined according to the value of the write data DATA.
[0512]
For example, when the write bit line BL01 is selected (when RA1 = "1"), if the write data DATA is "1", the output signal of the NAND gate circuit ND5 becomes "0", and the AND gate circuit The output signal of AD4 becomes “1”. As a result, a write current flows from the write bit line driver / sinker 29A to the write bit line driver / sinker 31 through the write bit line BL01.
[0513]
Further, when the write bit line BL01 is selected (when RA1 = "1"), if the write data DATA is "0", the output signal of the NAND gate circuit ND7 becomes "0", and the AND gate circuit The output signal of AD2 becomes “1”. As a result, a write current flows from the write bit line driver / sinker 31 to the write bit line driver / sinker 29A through the write bit line BL01.
[0514]
When the write bit line BL00 is selected (when RA1 = "0"), if the write data DATA is "1", the output signal of the NAND gate circuit ND4 becomes "0", and the AND gate circuit The output signal of AD3 becomes “1”. As a result, a write current flows from the write bit line driver / sinker 29A to the write bit line driver / sinker 31 through the write bit line BL00.
[0515]
When the write bit line BL00 is selected (when RA1 = "0"), if the write data DATA is "0", the output signal of the NAND gate circuit ND6 becomes "0", and the AND gate circuit The output signal of AD1 is “1”. As a result, a write current flows from the write bit line driver / sinker 31 to the write bit line driver / sinker 29A through the write bit line BL00.
[0516]
When the device structure shown in FIGS. 2 and 3 is employed, for example, the write bit line BLj0 is shared by the two TMR elements MTJ1 and MTJ2. Here, when viewed from the TMR element MTJ1, the write bit line BLj0 is above it, and when viewed from the TMR element MTJ2, the write bit line BLj0 is below it.
[0517]
Therefore, for example, when the direction of the write current is the direction from the write bit line driver / sinker 29A to the write bit line driver / sinker 31 in FIG. 1, the magnetic field received by the TMR element MTJ1 and the TMR element MTJ2 by this write current. Are opposite to each other.
[0518]
In this way, when one write bit line is shared by two TMR elements, the magnetic fields acting on the two TMR elements are in opposite directions even if the direction of the write current flowing through the write bit line is the same. Therefore, it should be noted that the magnetization directions are also opposite to each other.
[0519]
This is also true for the two TMR elements MTJ3 and MTJ4 in the device structures of FIGS. 2 and 3, for example.
[0520]
Each TMR element MTJ1, MTJ2. When the magnetization direction of the pinned layer can be individually set with respect to MTJ3 and MTJ4, for example, the magnetization direction of the pinned layer of the TMR element MTJ1 existing below the write bit line BLj0 and the write bit line BLj0 above By reversing the magnetization directions of the pinned layers of the TMR element MTJ2 existing in the above, the logic described in the above read operation principle and read circuit can be applied as it is.
[0521]
That is, the case where the magnetization direction of the pinned layer and the magnetization direction of the storage layer are the same can be “1”, and the case where the magnetization direction of the pinned layer and the magnetization direction of the storage layer are different can be “0”.
[0522]
Each TMR element MTJ1, MTJ2. Regarding MTJ3 and MTJ4, if the magnetization directions of the pinned layers are all the same, if the logic described in the above read operation principle and read circuit is applied as it is, further contrivance is required for the write operation or read operation. It becomes.
[0523]
For example, during the write operation, writing to the TMR element below the write bit line and writing to the TMR element above the write bit line are performed separately at different times, so that the magnetization direction of the pinned layer and the storage layer The case where the magnetization directions are the same can be “1”, and the case where the magnetization direction of the pinned layer and the magnetization direction of the storage layer are different can be “0”.
[0524]
The condition “1” / “0” of the TMR element below the write bit line (the relationship between the magnetization direction of the pinned layer and the magnetization direction of the storage layer) and “1” / “of the TMR element above the write bit line When the condition of “0” is reversed, it is necessary to change the logic for determining the data during the read operation.
[0525]
(3) Read word line driver
FIG. 70 shows a circuit example of the read word line driver.
The read word line driver 23B-0 includes an AND gate circuit AD5. The read signal READ and the upper row address signal are input to the AND gate circuit AD5.
[0526]
The read signal is a signal that becomes “1” during the read operation. The upper row address signal is the same as the upper row address signal in the write word line driver / sinker (FIG. 68). That is, the potential of the read word line RWL0 is determined based on the upper row address signal used for column selection among the plurality of bit address signals.
[0527]
In the selected row, since all the bits of the upper row address signal are “1”, the potential of the read word line RWL0 is “1”.
[0528]
(4) Column decoder
FIG. 71 shows a circuit example of the column decoder.
The column decoder 32 includes an AND gate circuit AD6. A read signal READ and a column address signal are input to the AND gate circuit AD6. The read signal is a signal that becomes “1” during the read operation. In the selected column, since all the bits of the column address signal are “1”, the potential of the column selection signal CSLj is “1”.
[0529]
(5) In the case of structural examples 4 and 5
(1) Write word line driver / sinker
FIG. 72 shows a circuit example of the write word line driver / sinker.
This figure shows only one row of the write word line driver / sinker corresponding to FIG.
[0530]
As can be seen from a comparison between FIG. 68 and FIG. 72, when the structural examples 4 and 5 are employed, the write word line driver / sinker is simplified.
[0531]
Specifically, in the case of FIG. 68, three drivers / sinkers for driving the three write word lines WWL0, WWL1, and WWL2 are required in one row. Therefore, it is sufficient to provide one driver / sinker for driving one write word line WWL0 in one row.
[0532]
The write word line driver 23A-0 includes a P-channel MOS transistor QP15 and a NAND gate circuit ND1. The write word line sinker 24-0 includes an N channel MOS transistor QN15.
[0533]
P-channel MOS transistor QP15 is connected between the power supply terminal and write word line WWL0. The output signal of NAND gate circuit ND1 is supplied to the gate of P channel MOS transistor QP15. N-channel MOS transistor QN15 is connected between write word line WWL0 and the ground terminal.
[0534]
When the output signal of the NAND gate circuit ND1 is “0”, a write current flows through the write word line WWL0.
[0535]
In such a write word line driver / sinker, the write signal WRITE is “1” during the write operation. One of the plurality of rows is selected based on the row address signal of a plurality of bits. In the selected row, all the bits of the upper row address signal are “1”. In the selected row, a write current flows through the write word line.
[0536]
(2) Write bit line driver / sinker
FIG. 73 shows a circuit example of the write bit line driver / sinker.
This figure shows only one row of the write word line driver / sinker, corresponding to FIG.
[0537]
As can be seen from a comparison between FIG. 69 and FIG. 73, when the structural examples 4 and 5 are employed, the write bit line driver / sinker is simplified.
[0538]
Specifically, in the case of FIG. 69, two drivers / sinkers for driving the two write bit lines BL00 and BL01 are required in one column, but in the case of FIG. It is sufficient to provide one driver / sinker for driving one write bit line BL01 in one column.
[0539]
The write bit line driver / sinker 31 includes P channel MOS transistors QP19 and QP21, N channel MOS transistors QN19 and QN21, NAND gate circuits ND5 and ND7, AND gate circuits AD2 and AD4, and inverters IV18 and IV20.
[0540]
P-channel MOS transistor QP19 is connected between the power supply terminal and write bit line BL01, and N-channel MOS transistor QN19 is connected between write bit line BL01 and the ground terminal. P-channel MOS transistor QP21 is connected between the power supply terminal and write bit line BL01, and N-channel MOS transistor QN21 is connected between write bit line BL01 and the ground terminal.
[0541]
When the output signal of the NAND gate circuit ND5 is “0” and the output signal of the AND gate circuit AD4 is “1”, a write current from the P channel MOS transistor QP19 to the N channel MOS transistor QN21 flows through the write bit line BL01. .
[0542]
When the output signal of the NAND gate circuit ND7 is “0” and the output signal of the AND gate circuit AD2 is “1”, a write current from the P channel MOS transistor QP21 to the N channel MOS transistor QN19 flows through the write bit line BL01. .
[0543]
In such a write bit line driver / sinker, the write signal WRITE is “1” during the write operation. In the selected column, all the bits of the column address signal of a plurality of bits are “1”.
[0544]
In addition, the direction of the write current flowing through the selected write bit line in the selected column is determined according to the value of the write data DATA.
[0545]
For example, if the write data DATA is “1”, the output signal of the NAND gate circuit ND5 becomes “0”, and the output signal of the AND gate circuit AD4 becomes “1”. As a result, a write current flows from the P channel MOS transistor QP19 to the N channel MOS transistor QN21 through the write bit line BL01.
[0546]
When the write data DATA is “0”, the output signal of the NAND gate circuit ND7 is “0”, and the output signal of the AND gate circuit AD2 is “1”. As a result, a write current flows from the P channel MOS transistor QP21 to the N channel MOS transistor QN19 through the write bit line BL01.
[0547]
7. Positional relationship between the pinned layer and storage layer of each TMR element
As in Structural Examples 1 to 6, for example, a TMR element is disposed above and below a write line (write word line or write bit line), and generated by a write current flowing through the write line. When writing data to the TMR element above or below using a magnetic field, the positional relationship between the pinned layer (fixed layer) and storage layer (free layer) of each TMR element, the magnetization direction of the pinned layer, etc. It is necessary to consider.
[0548]
This is because the write operation principle or the write circuit configuration changes depending on the positional relationship between the pin layer and the memory layer of each TMR element, the direction of the current flowing through the write line, and the like.
[0549]
(1) Positional relationship between the pinned layer and memory layer of each TMR element
As shown in FIG. 74, it is desirable that the positional relationship (relative relationship) between the pin layer and the storage layer of each TMR element (MTJ element) is symmetric with respect to the write line to be used.
[0550]
For example, with respect to a write line (a write word line or a write bit line), a TMR element is disposed above and below the write line, and a magnetic field generated by a write current flowing through the write line is used. When data is written to the TMR element at the bottom, the positional relationship between the pin layer and the storage layer of each TMR element is set to be symmetric with respect to the write line.
[0551]
Specifically, when the structure of the TMR element below the write line is a structure in which the memory layer exists on the side close to the write wiring and the pinned layer exists on the side far from it, the TMR above the write line is provided. Regarding the structure of the element, the memory layer is present on the side closer to the write wiring and the pinned layer is present on the side farther from the memory layer.
[0552]
Similarly, when the structure of the TMR element below the write line is a structure in which the pin layer is present on the side close to the write wiring and the memory layer is present on the side far from it, the structure of the TMR element above the write line is The structure is such that the pinned layer exists on the side closer to the write wiring and the storage layer exists on the side farther from the pinned layer.
[0553]
Such a positional relationship is established with respect to all the TMR elements in the memory cell array. Further, the TMR element disposed above and the TMR element disposed below the TMR element are arranged symmetrically with respect to all the write lines in the memory cell array.
[0554]
With such a positional relationship, the distance from the write line to the storage layer is substantially the same for all TMR elements. That is, since the influence of the magnetic field generated by the write current flowing in the write line is the same in all TMR elements, the write characteristics of all the TMR elements can be made the same.
[0555]
In this case, the direction of the TMR element disposed below (or above) the write line is opposite to the direction of the TMR element disposed above (or below) the write line. Become.
[0556]
However, the TMR elements in such a memory cell array are not all directed in the same direction. For example, regarding the TMR elements stacked in a plurality of stages, the direction of the TMR elements is different for each stage. For the invention, there is no demerit (the orientations here are only two types, upward and downward. In addition, as the definition of upper and lower, the semiconductor substrate side is defined as lower).
[0557]
This is because when the TMR element is formed, the direction of the TMR element can be easily changed only by changing the order of forming the layers constituting the TMR element.
[0558]
(2) Direction of magnetization of pinned layer of TMR element
A TMR element is disposed above and below the write line (write word line or write bit line), and a magnetic field generated by a write current flowing through the write line is used to place the TMR element above or below the write line. When writing data to a certain TMR element, it is necessary to change the write operation principle and the read operation principle depending on the magnetization direction of the pinned layer of the TMR element.
[0559]
This is because even if the direction of the current flowing through the write line is constant, the direction of the magnetic field applied to the TMR element disposed above the write line is opposite to the direction of the magnetic field applied to the TMR element disposed below the write line. Because.
[0560]
(1) When individually setting the magnetization direction of the pinned layer
When the magnetization direction of the pin layer can be individually set, the magnetization direction of the pin layer of the TMR element existing below the write line (write word line, write bit line) and above the write line are present. By reversing the magnetization directions of the pinned layers of the TMR element, the read operation principle and the write operation principle can be applied as usual.
[0561]
That is, the case where the magnetization direction of the pinned layer and the magnetization direction of the storage layer are the same can be “1”, and the case where the magnetization direction of the pinned layer and the magnetization direction of the storage layer are different can be “0”.
[0562]
Specific examples will be described below.
As a precondition, as shown in FIGS. 75 and 76, the easy axes of the TMR elements MTJ1 and MTJ2 face the X direction (the direction in which the write word line extends) and are arranged below the write bit line BL00. It is assumed that the magnetization direction of the pinned layer of the TMR element MTJ1 is on the left side, and the magnetization direction of the pinned layer of the TMR element MTJ2 disposed above the write bit line BL00 is on the right side.
[0563]
Further, it is assumed that write data is determined by the direction of the write current flowing through the write bit line BL00, and only the write current flowing in one direction flows through the write word lines WWL0 and WWL1.
[0564]
・ When writing data to the TMR element below the write bit line
["1"-Write]
As shown in FIG. 75, a write current flowing in one direction is supplied to the write word line WWL0, and a write current is supplied to the write bit line BL00 in the direction of being sucked into the paper surface. The magnetic field generated by the write current flowing through the write bit line BL00 draws a clockwise circle around the write bit line BL00.
[0565]
In this case, a leftward magnetic field is applied to the TMR element MTJ1 below the write bit line BL00. Therefore, the magnetization direction of the TMR element MTJ1 below the write bit line BL00 is leftward.
[0566]
Therefore, the magnetization state of the TMR element MTJ1 below the write bit line BL00 is parallel and data “1” is written.
[0567]
["0"-Write]
A write current flowing in one direction is supplied to the write word line WWL0, and a write current is supplied to the write bit line BL00 in a direction discharged from the paper surface. The magnetic field generated by the write current flowing through the write bit line BL00 draws a counterclockwise circle around the write bit line BL00.
[0568]
In this case, a rightward magnetic field is applied to the TMR element MTJ1 below the write bit line BL00. Therefore, the magnetization direction of the TMR element MTJ1 below the write bit line BL00 is rightward.
[0569]
Accordingly, the magnetization state of the TMR element MTJ1 below the write bit line BL00 is antiparallel, and data “0” is written.
[0570]
・ When writing data to the TMR element above the write bit line
If the same data can be written to the TMR element MTJ2 above the write bit line BL00 under the same conditions as the write conditions for the TMR element MTJ1, the same write circuit is used for the two TMR elements MTJ1 and MTJ2. Write / read operations can be performed using the (write bit line driver / sinker) and the same read circuit.
[0571]
["1"-Write]
As shown in FIG. 76, a write current flowing in one direction is supplied to the write word line WWL1, and a write current is supplied to the write bit line BL00 in the direction of being sucked into the paper surface.
[0572]
This write condition is the same as the “1” -write condition for the TMR element MTJ1 below the write bit line BL00. At this time, the magnetic field generated by the write current flowing through the write bit line BL00 draws a clockwise circle around the write bit line BL00.
[0573]
In this case, a rightward magnetic field is applied to the TMR element MTJ2 above the write bit line BL00. Therefore, the magnetization direction of the TMR element MTJ2 above the write bit line BL00 is rightward.
[0574]
Accordingly, the magnetization state of the TMR element MTJ2 above the write bit line BL00 becomes parallel and data “1” is written.
[0575]
Thus, by making the magnetization directions of the pinned layers of the TMR elements MTJ and MTJ2 different, the same data can be written to the TMR elements MTJ and MTJ2 under the same write conditions.
[0576]
["0"-Write]
A write current flowing in one direction is supplied to the write word line WWL1, and a write current is supplied to the write bit line BL00 in a direction discharged from the paper surface.
[0577]
This write condition is the same as the “0” -write condition for the TMR element MTJ1 below the write bit line BL00. At this time, the magnetic field generated by the write current flowing through the write bit line BL00 draws a counterclockwise circle around the write bit line BL00.
[0578]
In this case, a leftward magnetic field is applied to the TMR element MTJ2 above the write bit line BL00. Therefore, the magnetization direction of the TMR element MTJ2 above the write bit line BL00 is leftward.
[0579]
Accordingly, the magnetization state of the TMR element MTJ2 above the write bit line BL00 is antiparallel, and data “0” is written.
[0580]
Thus, by making the magnetization directions of the pinned layers of the TMR elements MTJ and MTJ2 different, the same data can be written to the TMR elements MTJ and MTJ2 under the same write conditions.
[0581]
(2) When the magnetization direction of the pinned layer of all TMR elements is the same
When the magnetization directions of the pinned layers of all the TMR elements are made the same, for example, after the wafer process is finished, a magnetic field in the same direction is applied to the pinned layers of all the TMR elements at once, and all the TMRs are instantaneously The magnetization direction of the pinned layer of the element can be determined.
[0582]
In particular, when a magnetic field is applied, the magnetization direction of the pinned layers of all TMR elements can be easily determined by increasing the temperature of the wafer.
[0583]
However, in this case, the same data cannot be written under the same write condition for the TMR element disposed below the write line and the TMR element disposed above the write line.
[0584]
Therefore, as a countermeasure, A. A configuration of the write circuit (write bit line driver / sinker), that is, a countermeasure for changing the configuration of the read circuit without changing the write condition; There are two countermeasures for changing the configuration of the write circuit (write bit line driver / sinker), that is, changing the write condition and not changing the configuration of the read circuit.
[0585]
Specific examples will be described below.
As a precondition, as shown in FIGS. 77 and 79, the easy axes of the TMR elements MTJ1 and MTJ2 face the X direction (the direction in which the write word line extends) and are arranged below the write bit line BL00. It is assumed that the magnetization direction of the pinned layer of the TMR element MTJ1 and the magnetization direction of the pinned layer of the TMR element MTJ2 arranged above the write bit line BL00 are both on the left side.
[0586]
Further, it is assumed that write data is determined by the direction of the write current flowing through the write bit line BL00, and only the write current flowing in one direction flows through the write word lines WWL0 and WWL1.
[0587]
A. When writing conditions are not changed
・ When writing data to the TMR element below the write bit line
["1"-Write]
As shown in FIG. 77, a write current flowing in one direction is supplied to the write word line WWL0, and a write current is supplied to the write bit line BL00 in the direction of being sucked into the paper surface. The magnetic field generated by the write current flowing through the write bit line BL00 draws a clockwise circle around the write bit line BL00.
[0588]
In this case, a leftward magnetic field is applied to the TMR element MTJ1 below the write bit line BL00. Therefore, the magnetization direction of the TMR element MTJ1 below the write bit line BL00 is leftward.
[0589]
Therefore, the magnetization state of the TMR element MTJ1 below the write bit line BL00 is parallel and data “1” is written.
[0590]
["0"-Write]
A write current flowing in one direction is supplied to the write word line WWL0, and a write current is supplied to the write bit line BL00 in a direction discharged from the paper surface. The magnetic field generated by the write current flowing through the write bit line BL00 draws a counterclockwise circle around the write bit line BL00.
[0591]
In this case, a rightward magnetic field is applied to the TMR element MTJ1 below the write bit line BL00. Therefore, the magnetization direction of the TMR element MTJ1 below the write bit line BL00 is rightward.
[0592]
Accordingly, the magnetization state of the TMR element MTJ1 below the write bit line BL00 is antiparallel, and data “0” is written.
[0593]
・ When writing data to the TMR element above the write bit line
For the TMR element MTJ2 above the write bit line BL00, a write operation is executed using the same conditions as the write conditions for the TMR element MTJ1, that is, the same write circuit (write bit line driver / sinker).
[0594]
["1"-Write]
As shown in FIG. 78, a write current flowing in one direction is supplied to the write word line WWL1, and a write current is supplied to the write bit line BL00 in the direction of being drawn into the paper surface.
[0595]
This write condition is the same as the “1” -write condition for the TMR element MTJ1 below the write bit line BL00. At this time, the magnetic field generated by the write current flowing through the write bit line BL00 draws a clockwise circle around the write bit line BL00.
[0596]
In this case, a rightward magnetic field is applied to the TMR element MTJ2 above the write bit line BL00. Therefore, the magnetization direction of the TMR element MTJ2 above the write bit line BL00 is rightward.
[0597]
Therefore, the magnetization state of the TMR element MTJ2 above the write bit line BL00 is antiparallel, that is, a state where data “0” is stored.
[0598]
Here, since the write data to the TMR element MTJ2 is “1”, at the time of reading, “0” -data stored in the TMR element MTJ2 is read as “1” instead of “0”. There must be.
[0599]
Therefore, the configuration of the readout circuit is slightly changed.
[0600]
Basically, since the write data is stored in an inverted state with respect to the TMR element existing above the write bit line, the read circuit for reading the data of the TMR element existing above the write bit line is used. What is necessary is just to add one inverter to an output part (final stage).
[0601]
For example, in Structural Examples 1 to 6, the second-stage TMR element MTJ2 and the fourth-stage TMR element MTJ4 are arranged above the write bit line.
Therefore, for example, when the so-called collective reading operation principle is applied, one inverter may be added to the output portion of the logic circuit of FIGS.
[0602]
As described above, when the magnetization directions of the pinned layers of the TMR elements MTJ and MTJ2 are the same, the write data is stored in one of the TMR element disposed above the write line and the TMR element disposed below the TMR element. The opposite data is stored.
[0603]
Therefore, if one inverter is added to the output section (final stage) of the read circuit that reads the data of the TMR element in which the reverse data is stored, the configuration of the write circuit (write bit line driver / sinker) is not changed. A write operation can be performed.
[0604]
["0"-Write]
A write current flowing in one direction is supplied to the write word line WWL1, and a write current is supplied to the write bit line BL00 in a direction discharged from the paper surface.
[0605]
This write condition is the same as the “0” -write condition for the TMR element MTJ1 below the write bit line BL00. At this time, the magnetic field generated by the write current flowing through the write bit line BL00 draws a counterclockwise circle around the write bit line BL00.
[0606]
In this case, a leftward magnetic field is applied to the TMR element MTJ2 above the write bit line BL00. Therefore, the magnetization direction of the TMR element MTJ2 above the write bit line BL00 is leftward.
[0607]
Therefore, the magnetization state of the TMR element MTJ2 above the write bit line BL00 is parallel, that is, a state where data “1” is stored.
[0608]
Here, since the write data to the TMR element MTJ2 is “0”, at the time of reading, “1” -data stored in the TMR element MTJ2 is read as “0” instead of “1”. There must be.
[0609]
Therefore, as described above, if one inverter is added to the output section (final stage) of the read circuit for reading the data of the TMR element existing above the write bit line, the data is read without any problem. be able to.
[0610]
B. Changing the writing conditions
If the write condition is changed, for example, when the write data is “1”, the states of the TMR elements MTJ1 and MTJ2 can be made parallel, and when the write data is “0”, the TMR elements MTJ1 and MTJ1 are parallel. Both MTJ2 states can be antiparallel.
[0611]
That is, there is no need to change the readout circuit.
[0612]
・ When writing data to the TMR element below the write bit line
["1"-Write]
As shown in FIG. 77, a write current flowing in one direction is supplied to the write word line WWL0, and a write current is supplied to the write bit line BL00 in the direction of being sucked into the paper surface. The magnetic field generated by the write current flowing through the write bit line BL00 draws a clockwise circle around the write bit line BL00.
[0613]
In this case, a leftward magnetic field is applied to the TMR element MTJ1 below the write bit line BL00. Therefore, the magnetization direction of the TMR element MTJ1 below the write bit line BL00 is leftward.
[0614]
Therefore, the magnetization state of the TMR element MTJ1 below the write bit line BL00 is parallel and data “1” is written.
[0615]
["0"-Write]
A write current flowing in one direction is supplied to the write word line WWL0, and a write current is supplied to the write bit line BL00 in a direction discharged from the paper surface. The magnetic field generated by the write current flowing through the write bit line BL00 draws a counterclockwise circle around the write bit line BL00.
[0616]
In this case, a rightward magnetic field is applied to the TMR element MTJ1 below the write bit line BL00. Therefore, the magnetization direction of the TMR element MTJ1 below the write bit line BL00 is rightward.
[0617]
Accordingly, the magnetization state of the TMR element MTJ1 below the write bit line BL00 is antiparallel, and data “0” is written.
[0618]
・ When writing data to the TMR element above the write bit line
["1"-Write]
As shown in FIG. 79, a write current flowing in one direction is supplied to the write word line WWL1, and a write current is supplied to the write bit line BL00 in a direction discharged from the paper surface.
[0619]
This write condition is different from the “1” -write condition for the TMR element MTJ1 below the write bit line BL00. That is, assuming that the write data is the same, the direction of the write current flowing through the write line changes depending on whether the TMR element is present above or below the write line.
[0620]
Note that a write circuit (a write bit line driver / sinker for realizing such an operation will be described later.
[0621]
At this time, the magnetic field generated by the write current flowing through the write bit line BL00 draws a counterclockwise circle around the write bit line BL00.
[0622]
In this case, a leftward magnetic field is applied to the TMR element MTJ2 above the write bit line BL00. Therefore, the magnetization direction of the TMR element MTJ2 above the write bit line BL00 is leftward.
[0623]
Therefore, the magnetization state of the TMR element MTJ2 above the write bit line BL00 is parallel, that is, a state where data “1” is stored.
[0624]
["0"-Write]
A write current flowing in one direction is supplied to the write word line WWL1, and a write current is supplied to the write bit line BL00 in the direction of being sucked into the paper surface.
[0625]
This write condition is different from the “0” -write condition for the TMR element MTJ1 below the write bit line BL00. That is, assuming that the write data is the same, the direction of the write current flowing through the write line changes depending on whether the TMR element is present above or below the write line.
[0626]
At this time, the magnetic field generated by the write current flowing through the write bit line BL00 draws a clockwise circle around the write bit line BL00.
[0627]
In this case, a rightward magnetic field is applied to the TMR element MTJ2 above the write bit line BL00. Therefore, the magnetization direction of the TMR element MTJ2 above the write bit line BL00 is rightward.
[0628]
Therefore, the magnetization state of the TMR element MTJ2 above the write bit line BL00 is antiparallel, that is, a state where data “0” is stored.
[0629]
(3) Configuration of a write circuit (write bit line driver / sinker) when the magnetization directions of the pin layers of all TMR elements are the same
FIG. 80 shows a circuit example of the write bit line driver / sinker.
The circuit of FIG. 80 is a modification of the circuit of FIG. That is, the circuit of FIG. 80 is characterized in that the circuit in FIG. 69 has a new function, that is, a function of changing the direction of the write current based on the position information of the TMR element.
[0630]
This write bit line driver / sinker corresponds to the cell array structure of the magnetic random access memory of Structural Examples 1-6.
[0631]
The four TMR elements MTJ1, MTJ2, MTJ3, and MTJ4 constituting the read block are stacked in four stages, the write bit line BL00 is disposed between the TMR element MTJ1 and the TMR element MTJ2, and the TMR element MTJ3 and the TMR element MTJ4. It is assumed that the write bit line BL01 is arranged between.
[0632]
The TMR elements MTJ1 and MTJ3 are disposed below the write bit lines BL00 and BL01, and the TMR elements MTJ2 and MTJ4 are disposed above the write bit lines BL00 and BL01.
[0633]
In the figure, only one column of the write bit line driver / sinker is shown.
[0634]
The write bit line driver / sinker 29A includes P-channel MOS transistors QP18 and QP19, N-channel MOS transistors QN18 and QN19, NAND gate circuits ND4 and ND5, AND gate circuits AD1 and AD2, NOR gate circuit NR16, inverter IV17, and an exclusive OR circuit It consists of Ex-OR1, Ex-OR2, Ex-OR5 and an exclusive NOR circuit Ex-NR1.
[0635]
Write bit line driver / sinker 31 includes P channel MOS transistors QP20 and QP21, N channel MOS transistors QN20 and QN21, NAND gate circuits ND6 and ND7, AND gate circuits AD3 and AD4, NOR gate circuit NR17, inverter IV19, and an exclusive OR circuit It comprises Ex-OR3, Ex-OR4, Ex-OR6 and an exclusive NOR circuit Ex-NR2.
[0636]
P channel MOS transistor QP18 is connected between the power supply terminal and lower write bit line BL00, and N channel MOS transistor QN18 is connected between lower write bit line BL00 and the ground terminal. P channel MOS transistor QP20 is connected between the power supply terminal and lower write bit line BL00, and N channel MOS transistor QN20 is connected between lower write bit line BL00 and the ground terminal.
[0637]
When the output signal of the NAND gate circuit ND4 is “0” and the output signal of the AND gate circuit AD3 is “1”, the write bit line BL00 is directed from the write bit line driver / sinker 29A to the write bit line driver / sinker 31. Write current flows.
[0638]
When the output signal of the NAND gate circuit ND6 is “0” and the output signal of the AND gate circuit AD1 is “1”, the write bit line BL00 is directed from the write bit line driver / sinker 31 to the write bit line driver / sinker 29A. Write current flows.
[0639]
P channel MOS transistor QP19 is connected between the power supply terminal and upper write bit line BL01, and N channel MOS transistor QN19 is connected between upper write bit line BL01 and the ground terminal. P-channel MOS transistor QP21 is connected between the power supply terminal and upper write bit line BL01, and N-channel MOS transistor QN21 is connected between upper write bit line BL01 and the ground terminal.
[0640]
When the output signal of the NAND gate circuit ND5 is “0” and the output signal of the AND gate circuit AD4 is “1”, the write bit line BL01 is directed from the write bit line driver / sinker 29A to the write bit line driver / sinker 31. Write current flows.
[0641]
When the output signal of the NAND gate circuit ND7 is “0” and the output signal of the AND gate circuit AD2 is “1”, the write bit line BL01 is directed from the write bit line driver / sinker 31 to the write bit line driver / sinker 29A. Write current flows.
[0642]
In such a write bit line driver / sinker, the write signal WRITE is “1” during the write operation. In the selected column, all the bits of the column address signal of a plurality of bits are “1”.
[0643]
In this example, one of the two write bit lines BL00 and BL01 in one column is selected using one bit RA1 of the row address signals of a plurality of bits. For example, when RA1 is “0”, the write bit line BL00 is selected, and when RA1 is “1”, the write bit line BL01 is selected.
[0644]
In addition, the direction of the write current that flows through the selected write bit line in the selected column is determined according to the values of the write data DATA and RA0.
[0645]
Here, the value of RA0 determines whether to select the TMR elements MTJ1 and MTJ3 below the write bit lines BL00 and BL01 or to select the TMR elements MTJ2 and MTJ4 above the write bit lines BL00 and BL01. Signal.
[0646]
・ When BL00 is selected
For example, when the write bit line BL00 is selected (when RA1 = "0"), if RA0 = 0, the TMR element MTJ1 below the write bit line BL00 is selected.
[0647]
At this time, if the write data DATA is “1”, the output signals of the exclusive OR circuits Ex-OR1 to Ex-OR4 are all “1”. The output signals of the NOR gate circuits NR16 and NR17 are both “0”.
[0648]
Therefore, the output signal of the NAND gate circuit ND4 becomes “0”, and the output signal of the AND gate circuit AD3 becomes “1”. As a result, a write current flows from the write bit line driver / sinker 29A to the write bit line driver / sinker 31 through the write bit line BL00.
[0649]
When the write data DATA is “0”, all the output signals of the exclusive OR circuits Ex-OR1 to Ex-OR4 are “0”. The output signals of the NOR gate circuits NR16 and NR17 are both “1”.
[0650]
Therefore, the output signal of the NAND gate circuit ND6 becomes “0”, and the output signal of the AND gate circuit AD1 becomes “1”. As a result, a write current from the write bit line driver / sinker 31 toward the write bit line driver / sinker 29A flows through the write bit line BL00.
[0651]
For example, when the write bit line BL00 is selected (when RA1 = “0”), if RA0 = 1, the TMR element MTJ2 above the write bit line BL00 is selected.
[0652]
At this time, if the write data DATA is “1”, the output signals of the exclusive OR circuits Ex-OR1 to Ex-OR4 are all “0”. The output signals of the NOR gate circuits NR16 and NR17 are both “1”.
[0653]
Therefore, the output signal of the NAND gate circuit ND6 becomes “0”, and the output signal of the AND gate circuit AD1 becomes “1”. As a result, a write current from the write bit line driver / sinker 31 toward the write bit line driver / sinker 29A flows through the write bit line BL00.
[0654]
When the write data DATA is “0”, all the output signals of the exclusive OR circuits Ex-OR1 to Ex-OR4 are “1”. The output signals of the NOR gate circuits NR16 and NR17 are both “0”.
[0655]
Therefore, the output signal of the NAND gate circuit ND4 becomes “0”, and the output signal of the AND gate circuit AD3 becomes “1”. As a result, a write current flows from the write bit line driver / sinker 29A to the write bit line driver / sinker 31 through the write bit line BL00.
[0656]
・ When BL01 is selected
For example, when the write bit line BL01 is selected (when RA1 = "1"), if RA0 = 0, the TMR element MTJ3 below the write bit line BL01 is selected.
[0657]
At this time, if the write data DATA is “1”, the output signals of the exclusive OR circuits Ex-OR5 and Ex-OR6 are both “1”. Further, the output signals of the exclusive NOR circuits Ex-NR1 and Ex-NR2 are both “0”.
[0658]
Therefore, the output signal of the NAND gate circuit ND5 becomes “0”, and the output signal of the AND gate circuit AD4 becomes “1”. As a result, a write current from the write bit line driver / sinker 29A to the write bit line driver / sinker 31 flows through the write bit line BL01.
[0659]
When the write data DATA is “0”, the output signals of the exclusive OR circuits Ex-OR5 and Ex-OR6 are both “0”. Further, the output signals of the exclusive NOR circuits Ex-NR1 and Ex-NR2 are both "1".
[0660]
Therefore, the output signal of the NAND gate circuit ND7 becomes “0”, and the output signal of the AND gate circuit AD2 becomes “1”. As a result, a write current flows from the write bit line driver / sinker 31 to the write bit line driver / sinker 29A through the write bit line BL01.
[0661]
Further, for example, when the write bit line BL01 is selected (when RA1 = "1"), if RA0 = 1, the TMR element MTJ4 above the write bit line BL01 is selected.
[0662]
At this time, if the write data DATA is “1”, the output signals of the exclusive OR circuits Ex-OR5 and Ex-OR6 are both “0”. Further, the output signals of the exclusive NOR circuits Ex-NR1 and Ex-NR2 are both "1".
[0663]
Therefore, the output signal of the NAND gate circuit ND7 becomes “0”, and the output signal of the AND gate circuit AD2 becomes “1”. As a result, a write current flows from the write bit line driver / sinker 31 to the write bit line driver / sinker 29A through the write bit line BL01.
[0664]
When the write data DATA is “0”, the output signals of the exclusive OR circuits Ex-OR5 and Ex-OR6 are both “1”. Further, the output signals of the exclusive NOR circuits Ex-NR1 and Ex-NR2 are both “0”.
[0665]
Therefore, the output signal of the NAND gate circuit ND5 becomes “0”, and the output signal of the AND gate circuit AD4 becomes “1”. As a result, a write current from the write bit line driver / sinker 29A to the write bit line driver / sinker 31 flows through the write bit line BL01.
[0666]
8). Production method
The cell array structure, the read operation principle, the TMR element structure, the peripheral circuit including the read circuit, and the positional relationship between the pinned layer and the storage layer with respect to the write line are as described above.
[0667]
Therefore, finally, a manufacturing method for realizing the magnetic random access memory of the present invention will be described.
[0668]
(1) Manufacturing method 1
In this manufacturing method 1, a plurality of TMR elements are stacked in a plurality of stages, and the plurality of TMR elements have a cell array structure (one switch-nMTJ structure) connected in series between a read bit line and a ground terminal. Applies to random access memory.
[0669]
First, a cell array structure completed by the manufacturing method of the present invention will be briefly described. Thereafter, a method for manufacturing the cell array structure will be described.
[0670]
(1) Cell array structure for manufacturing method 1
FIG. 81 shows an example of a cell array structure of a magnetic random access memory composed of a plurality of TMR elements in which one block is connected in series.
The cell array structure is characterized in that one read bit line is arranged in one column (Y direction), and a plurality of TMR elements connected in series are arranged immediately below. The plurality of TMR elements constitute one read block and are connected between the read bit line and the ground terminal.
[0671]
A read selection switch (MOS transistor) RSW is disposed in the surface region of the semiconductor substrate. The source of the read selection switch RSW is connected to the ground terminal via the source line SL. The source line SL is shared by two read blocks adjacent in the column direction. The source line SL extends, for example, in a straight line in the X direction (direction perpendicular to the paper surface).
[0672]
The gate of the read selection switch (MOS transistor) RSW is a read word line RWLn. The read word line RWLn extends in the X direction. Four TMR elements (MTJ (Magnetic Tunnel Junction) elements) are stacked on the read selection switch RSW.
[0673]
Each of the TMR elements is disposed between the lower electrode and the upper electrode, and is connected to each other in series by a contact plug. The lower electrode of the lowermost TMR element is connected to the drain of the read selection switch (MOS transistor) RSW. The upper electrode of the uppermost TMR element is connected to a read bit line BL0 extending in the Y direction by a contact plug.
[0674]
In one row, there are three write word lines WWL0, WWL1, WWL2 extending in the X direction, and in one column, there are two write bit lines BL00, BL01 extending in the Y direction.
[0675]
When the cell array structure is viewed from the top of the semiconductor substrate, for example, a plurality of stacked TMR elements are laid out so as to overlap each other. The three write word lines are also laid out so as to overlap each other. Further, the read bit line and the two write bit lines are also laid out so as to overlap each other.
[0676]
A contact plug for connecting a plurality of TMR elements in series is laid out at a position that does not overlap a write word line or a write bit line. The upper and lower electrodes of the TMR element are formed in a pattern that facilitates contact with the contact plug.
[0677]
(2) Each step of manufacturing method 1
A manufacturing method for realizing the cell array structure of FIG. 81 will be described below. Since a specific manufacturing method (for example, employing a dual damascene process) will be described here, it should be noted that elements not included in the cell array structure of FIG. 81 are also described. However, the outline of the finally completed cell array structure is almost the same as the cell array structure of FIG.
[0678]
・ Element separation step
First, as shown in FIG. 82, an element isolation insulating layer 52 having an STI (Shallow Trench Isolation) structure is formed in a semiconductor substrate 51.
[0679]
The element isolation insulating layer 52 can be formed by the following process, for example.
[0680]
A mask pattern (such as silicon nitride) is formed on the semiconductor substrate 51 by PEP (Photo Engraving Process). Using this mask pattern as a mask, the semiconductor substrate 51 is etched using RIE (Reactive Ion Etching) to form a trench in the semiconductor substrate 51. For example, an insulating layer (silicon oxide or the like) is filled in the trench by using a CVD (Chemical Vapor Deposition) method and a CMP (Chemical Mechanical Polishing) method.
[0681]
Thereafter, if necessary, P-type impurities (B, BF) may be formed in the semiconductor substrate by ion implantation, for example.₂Or N-type impurities (P, As, etc.) are implanted to form a P-type well region or an N-type well region.
[0682]
・ MOSFET formation step
Next, as shown in FIG. 83, a MOS transistor that functions as a read selection switch is formed in the surface region of the semiconductor substrate 51.
[0683]
The MOS transistor can be formed by the following process, for example.
[0684]
Impurities for controlling the threshold value of the MOS transistor are ion-implanted into the channel portion in the element region surrounded by the element isolation insulating layer 52. A gate insulating film (such as silicon oxide) 53 is formed in the element region by thermal oxidation. A gate electrode material (such as polysilicon containing impurities) and a cap insulating film (such as silicon nitride) 55 are formed on the gate insulating film 53 by CVD.
[0685]
After the cap insulating film 55 is patterned by PEP, the gate electrode material and the gate insulating film 53 are processed (etched) by RIE using the cap insulating film 55 as a mask. As a result, a gate electrode 54 extending in the X direction is formed on the semiconductor substrate 51.
[0686]
P-type impurities or N-type impurities are implanted into the semiconductor substrate 51 by ion implantation using the cap insulating film 55 and the gate electrode 54 as a mask. Then, a low concentration impurity region (LDD region or extension region) is formed in the semiconductor substrate.
[0687]
An insulating film (such as silicon nitride) is formed on the entire surface of the semiconductor substrate 51 by the CVD method, and then the insulating film is etched by RIE, so that a sidewall insulating layer is formed on the side walls of the gate electrode 54 and the cap insulating film 55. 57 is formed. P-type impurities or N-type impurities are implanted into the semiconductor substrate 51 by ion implantation using the cap insulating film 55, the gate electrode 54, and the sidewall insulating layers 57 as a mask. As a result, a source region 56A and a drain region 56B are formed in the semiconductor substrate 51.
Thereafter, an interlayer insulating film (eg, silicon oxide) 58 that completely covers the MOS transistor is formed on the entire semiconductor substrate 51 by CVD. Further, the surface of the interlayer insulating film 58 is planarized by using the CMP technique.
[0688]
・ Contact hole formation step
Next, as shown in FIGS. 84 and 85, a contact hole 59 reaching the source region 56A and the drain region 56B of the MOS transistor is formed in the interlayer insulating film 58 on the semiconductor substrate 51.
[0689]
The contact hole 59 can be easily formed by forming a resist pattern on the interlayer insulating film 58 by PEP, for example, and etching the interlayer insulating film 58 by RIE using this resist pattern as a mask. After this etching, the resist pattern is removed.
[0690]
・ Wiring groove formation step
Next, as shown in FIG. 86, a wiring trench 60 is formed in the interlayer insulating film 58 on the semiconductor substrate 51. In this example, since the wiring groove 60 extends in the X direction, the wiring groove 60 overlaps the contact hole 59 when viewed in a cross section along the Y direction. Therefore, in the figure, the wiring groove 60 is indicated by a broken line.
[0691]
The wiring trench 60 can be easily formed, for example, by forming a resist pattern on the interlayer insulating film 58 by PEP, and etching the interlayer insulating film 58 by RIE using this resist pattern as a mask. After this etching, the resist pattern is removed.
[0692]
・ First wiring layer formation step
Next, as shown in FIG. 87, for example, a sputtering method is used to form barrier metal layers (Ti and TiN laminated layers) on the interlayer insulating film 58, on the inner surface of the contact hole 59, and on the inner surface of the wiring groove 60, respectively. Etc.) 61 is formed. Subsequently, a metal layer (W or the like) 62 that completely fills the contact hole 59 and the wiring groove 60 is formed on the barrier metal layer 61 by sputtering, for example.
[0693]
Thereafter, as shown in FIG. 88, the metal layer 62 is polished by using, for example, a CMP method, and the metal layer 62 is left only in the contact hole 59 and the wiring groove 60. The metal layer 62 remaining in the contact hole 59 becomes a contact plug, and the metal layer 62 remaining in the wiring groove 60 becomes a first wiring layer. Further, an interlayer insulating film (such as silicon oxide) 63 is formed on the interlayer insulating film 58 by CVD.
[0694]
Note that a step including a contact hole forming step, a wiring groove forming step, and a first wiring layer forming step is called a dual damascene process.
[0695]
・ Wiring groove formation step
Next, as shown in FIG. 89, a wiring trench 64 is formed in the interlayer insulating film 63. In this example, the wiring trench 64 is a trench for forming a write word line and extends in the X direction. A sidewall insulating layer (such as silicon nitride) 65 for a self-aligned contact process is formed on the side surface of the wiring trench 64.
[0696]
The wiring trench 64 can be easily formed, for example, by forming a resist pattern on the interlayer insulating film 63 by PEP, and etching the interlayer insulating film 63 by RIE using this resist pattern as a mask. After this etching, the resist pattern is removed.
[0697]
The sidewall insulating layer 65 can be easily formed by forming an insulating film (such as silicon nitride) over the entire interlayer insulating film 63 by CVD and then etching the insulating film by RIE. it can.
[0698]
・ Second wiring layer formation step
Next, as shown in FIG. 90, for example, a barrier metal layer (a stack of Ta and TaN) is formed on the interlayer insulating film 63, the inner surface of the wiring groove 64, and the sidewall insulating layer 65 using a sputtering method. Etc.) 66 is formed. Subsequently, a metal layer (such as Cu) 67 that completely fills the wiring trench 64 is formed on the barrier metal layer 66 by, for example, sputtering.
[0699]
Thereafter, as shown in FIG. 91, the metal layer 67 is polished by using, for example, a CMP method, and the metal layer 67 is left only in the wiring trench 64. The metal layer 67 remaining in the wiring trench 64 becomes a second wiring layer that functions as a write word line.
[0700]
In addition, an insulating layer (such as silicon nitride) 68 is formed on the interlayer insulating film 63 by CVD. Further, the insulating layer 68 is polished by CMP, and the insulating layer 68 is left only on the metal layer 67 as the second wiring layer. An interlayer insulating film (such as silicon oxide) 69 that completely covers the metal layer 67 as the second wiring layer is formed on the interlayer insulating film 63.
[0701]
Note that a step including a wiring trench forming step and a second wiring layer forming step is called a damascene process.
[0702]
-Step of forming the lower electrode of the first MTJ element
Next, as shown in FIGS. 92 and 93, a contact hole reaching the metal layer 62 as the first wiring layer is formed in the interlayer insulating film 69.
[0703]
This contact hole can be easily formed by forming a resist pattern on the interlayer insulating film 69 by PEP, for example, and etching the interlayer insulating films 63 and 69 by RIE using this resist pattern as a mask. it can. After this etching, the resist pattern is removed.
[0704]
Further, for example, a barrier metal layer (such as a laminate of Ti and TiN) 70 is formed on the inner surface of the contact hole by sputtering. Subsequently, a metal layer (W or the like) 71 that completely fills the contact hole is formed on the barrier metal layer 70 by sputtering, for example.
[0705]
Thereafter, the metal layer 71 is polished using, for example, a CMP method, and the metal layer 71 is left only in the contact hole. The metal layer 71 remaining in the contact hole becomes a contact plug. Also, a metal layer (Ta or the like) 72 to be the lower electrode of the first MTJ element is formed on the interlayer insulating film 69 by CVD.
[0706]
Step of forming the first MTJ element and its upper electrode
Next, as shown in FIG. 94, a first MTJ element 73 is formed on the metal layer 72. The first MTJ element 73 includes a tunnel barrier, two ferromagnetic layers sandwiching the tunnel barrier, and an antiferromagnetic layer. For example, the first MTJ element 73 has a structure as shown in FIG.
[0707]
An interlayer insulating film (such as silicon oxide) 75A that completely covers the first MTJ element 73 is formed by CVD. Further, for example, the interlayer insulating film 75A is polished by CMP, and the interlayer insulating film 75A is left only between the first MTJ elements 73.
[0708]
Further, a metal layer (Ta or the like) 74 to be the upper electrode of the first MTJ element 73 is formed on the interlayer insulating film 75A by sputtering.
[0709]
-Patterning step of lower / upper electrode of the first MTJ element
Next, as shown in FIGS. 95 and 96, the lower electrode 72 and the upper electrode 74 of the first MTJ element 73 are patterned, respectively.
[0710]
For patterning the lower / upper electrodes 72, 74 of the first MTJ element 73, after forming a resist pattern on the upper electrode 74 by PEP, the lower / upper electrodes 72, 74 are formed by RIE using this resist pattern as a mask. This can be easily done by etching. Thereafter, the resist pattern is removed.
[0711]
An interlayer insulating film 75 that completely covers the upper electrode 74 of the first MTJ element 73 is formed by CVD.
[0712]
・ Wiring groove formation step
Next, as shown in FIG. 97, a wiring groove 75 </ b> A is formed in the interlayer insulating film 75. In this example, the wiring groove 75A is a groove for forming a write bit line and extends in the Y direction. A sidewall insulating layer (such as silicon nitride) for the self-aligned contact process is formed on the side surface of the wiring trench 75A.
[0713]
The wiring trench 75A can be easily formed by forming a resist pattern on the interlayer insulating film 75 by PEP, for example, and etching the interlayer insulating film 75 by RIE using this resist pattern as a mask. After this etching, the resist pattern is removed.
[0714]
The sidewall insulating layer can be easily formed by forming an insulating film (such as silicon nitride) over the entire interlayer insulating film 75 by CVD and then etching the insulating film by RIE. .
[0715]
・ Step of forming the third wiring layer
Next, as shown in FIG. 98, for example, using a sputtering method, a barrier metal layer (such as a stack of Ta and TaN) is formed on the interlayer insulating film 75, the inner surface of the wiring trench 75A, and the sidewall insulating layer. ) 76 is formed. Subsequently, a metal layer (such as Cu) 77 that completely fills the wiring trench 75A is formed on the barrier metal layer 76 by, for example, sputtering.
[0716]
Thereafter, as shown in FIG. 99, the metal layer 77 is polished by using, for example, a CMP method, and the metal layer 77 is left only in the wiring trench 75A. The metal layer 77 remaining in the wiring trench 75A becomes a third wiring layer that functions as a write bit line.
[0717]
Further, an insulating layer (such as silicon nitride) 78 is formed on the interlayer insulating film 75 by a CVD method. Further, the insulating layer 78 is polished by the CMP method, and the insulating layer 78 is left only on the metal layer 77 as the third wiring layer. Further, an interlayer insulating film (such as silicon oxide) 79 that completely covers the metal layer 77 as the third wiring layer is formed on the interlayer insulating film 75.
[0718]
-Step of forming the lower electrode of the second MTJ element
Next, as shown in FIGS. 100 and 101, contact holes reaching the upper electrode 74 of the first MTJ element are formed in the interlayer insulating films 75 and 79.
[0719]
This contact hole can be easily formed by forming a resist pattern on the interlayer insulating film 79 by PEP, for example, and etching the interlayer insulating films 75 and 79 by RIE using this resist pattern as a mask. it can. After this etching, the resist pattern is removed.
[0720]
Also, for example, a barrier metal layer (such as a laminate of Ti and TiN) 80 is formed on the inner surface of the contact hole by sputtering. Subsequently, a metal layer (such as W) 81 that completely fills the contact hole is formed on the barrier metal layer 80 by sputtering, for example.
[0721]
Thereafter, the metal layer 81 is polished by using, for example, a CMP method, and the metal layer 81 is left only in the contact hole. The metal layer 81 remaining in the contact hole becomes a contact plug. Further, a metal layer (Ta or the like) 82 to be the lower electrode of the second MTJ element is formed on the interlayer insulating film 79 by sputtering.
[0722]
Step of forming the second MTJ element and its upper electrode
Next, as shown in FIG. 102, the second MTJ element 84 is formed on the metal layer 82. The second MTJ element 84 includes a tunnel barrier and two ferromagnetic layers and an antiferromagnetic layer sandwiching the tunnel barrier, and has a structure as shown in FIG. 46, for example.
[0723]
An interlayer insulating film (such as silicon oxide) 83 that completely covers the second MTJ element 84 is formed by CVD. Further, for example, the interlayer insulating film 83 is polished by the CMP method, and the interlayer insulating film 83 is left only between the second MTJ elements 84.
[0724]
In addition, a metal layer (such as Ta) 85 to be the upper electrode of the second MTJ element 84 is formed on the interlayer insulating film 83 by sputtering.
[0725]
-Patterning step of the lower / upper electrode of the second MTJ element
Next, as shown in FIGS. 103 and 104, the lower electrode 82 and the upper electrode 85 of the second MTJ element 84 are patterned, respectively.
[0726]
For patterning the lower / upper electrodes 82, 85 of the second MTJ element 84, after forming a resist pattern on the upper electrode 85 by PEP, the lower / upper electrodes 82, 85 are formed by RIE using this resist pattern as a mask. This can be easily done by etching. Thereafter, the resist pattern is removed.
[0727]
An interlayer insulating film 86 that completely covers the upper electrode 85 of the second MTJ element 84 is formed by CVD.
[0728]
・ Wiring groove formation step
Next, as shown in FIG. 105, a wiring groove 87 is formed in the interlayer insulating film 86. In this example, the wiring groove 87 is a groove for forming a write word line and extends in the X direction. A sidewall insulating layer (such as silicon nitride) 88 for a self-aligned contact process is formed on the side surface of the wiring groove 87.
[0729]
The wiring groove 87 can be easily formed by forming a resist pattern on the interlayer insulating film 86 by PEP, for example, and etching the interlayer insulating film 86 by RIE using this resist pattern as a mask. After this etching, the resist pattern is removed.
[0730]
The sidewall insulating layer 88 can be easily formed by forming an insulating film (such as silicon nitride) over the entire interlayer insulating film 86 by CVD and then etching the insulating film by RIE. it can.
[0731]
・ Step of forming the fourth wiring layer
Next, as shown in FIG. 106, for example, a barrier metal layer (a stack of Ta and TaN) is formed on the interlayer insulating film 86, on the inner surface of the wiring groove 87, and on the sidewall insulating layer 88 by sputtering. Etc.) 89 is formed. Subsequently, a metal layer (such as Cu) 91 that completely fills the wiring groove 87 is formed on the barrier metal layer 89 by sputtering, for example.
[0732]
Thereafter, as shown in FIG. 107, the metal layer 91 is polished by using, for example, a CMP method, and the metal layer 91 is left only in the wiring trench 87. The metal layer 91 remaining in the wiring trench 87 becomes a fourth wiring layer that functions as a write word line.
[0733]
Further, an insulating layer (such as silicon nitride) 92 is formed on the interlayer insulating film 86 by a CVD method. Further, the insulating layer 92 is polished by CMP, and the insulating layer 92 is left only on the metal layer 91 as the fourth wiring layer. Further, an interlayer insulating film (such as silicon oxide) 93 that completely covers the metal layer 91 as the fourth wiring layer is formed on the interlayer insulating film 86.
[0734]
-Step of forming the lower electrode of the third MTJ element
Next, as shown in FIGS. 108 and 109, contact holes reaching the upper electrode 85 of the second MTJ element are formed in the interlayer insulating films 86 and 93.
[0735]
This contact hole can be easily formed by forming a resist pattern on the interlayer insulating film 93 by PEP, for example, and etching the interlayer insulating films 86 and 93 by RIE using this resist pattern as a mask. it can. After this etching, the resist pattern is removed.
[0736]
Further, for example, a barrier metal layer (such as a laminate of Ti and TiN) 94 is formed on the inner surface of the contact hole by sputtering. Subsequently, a metal layer (such as W) 95 that completely fills the contact hole is formed on the barrier metal layer 94 by sputtering, for example.
[0737]
Thereafter, the metal layer 95 is polished using, for example, a CMP method, and the metal layer 95 is left only in the contact hole. The metal layer 95 remaining in the contact hole becomes a contact plug. In addition, a metal layer (Ta or the like) 96 serving as a lower electrode of the third MTJ element is formed on the interlayer insulating film 93 by sputtering.
[0738]
-Step of forming the third MTJ element and its upper electrode
Next, as shown in FIG. 110, the third MTJ element 97 is formed on the metal layer 96. The third MTJ element 97 includes a tunnel barrier, two ferromagnetic layers sandwiching the tunnel barrier, and an antiferromagnetic layer, and has a structure as shown in FIG. 47, for example.
[0739]
An interlayer insulating film (such as silicon oxide) 98 that completely covers the third MTJ element 97 is formed by CVD. Further, for example, the interlayer insulating film 98 is polished by the CMP method, and the interlayer insulating film 98 is left only between the third MTJ elements 97.
[0740]
In addition, a metal layer (Ta or the like) 99 serving as the upper electrode of the third MTJ element 97 is formed on the interlayer insulating film 98 by sputtering.
[0741]
-Patterning step of the lower / upper electrode of the third MTJ element
Next, as shown in FIGS. 111 and 112, the lower electrode 96 and the upper electrode 99 of the third MTJ element 97 are patterned, respectively.
[0741]
For patterning the lower / upper electrodes 96, 99 of the third MTJ element 97, after forming a resist pattern on the upper electrode 99 by PEP, the lower / upper electrodes 96, 99 are formed by RIE using this resist pattern as a mask. This can be easily done by etching. Thereafter, the resist pattern is removed.
[0743]
An interlayer insulating film 100 that completely covers the upper electrode 99 of the third MTJ element 97 is formed by CVD.
[0744]
・ Wiring groove formation step
Next, as shown in FIG. 113, a wiring trench 100 </ b> A is formed in the interlayer insulating film 100. In this example, the wiring groove 100A is a groove for forming a write bit line and extends in the Y direction. A sidewall insulating layer (such as silicon nitride) for a self-aligned contact process is formed on the side surface of the wiring trench 100A.
[0745]
The wiring trench 100A can be easily formed by forming a resist pattern on the interlayer insulating film 100 by PEP, for example, and etching the interlayer insulating film 100 by RIE using the resist pattern as a mask. After this etching, the resist pattern is removed.
[0746]
The sidewall insulating layer can be easily formed by forming an insulating film (such as silicon nitride) over the entire interlayer insulating film 100 by a CVD method and then etching the insulating film by RIE. .
[0747]
・ Fifth wiring layer formation step
Next, as shown in FIG. 114, for example, using a sputtering method, a barrier metal layer (such as a stack of Ta and TaN) is formed on the interlayer insulating film 100, the inner surface of the wiring groove 100A, and the sidewall insulating layer. ) 101 is formed. Subsequently, a metal layer (such as Cu) 102 that completely fills the wiring trench 100A is formed on the barrier metal layer 101 by, for example, sputtering.
[0748]
Thereafter, as shown in FIG. 115, for example, the CMP method is used to polish the metal layer 102, leaving the metal layer 102 only in the wiring trench 100A. The metal layer 102 remaining in the wiring trench 100A becomes a fifth wiring layer that functions as a write bit line.
[0749]
Further, an insulating layer (such as silicon nitride) 103 is formed on the interlayer insulating film 100 by a CVD method. Further, this insulating layer 103 is polished by CMP, and this insulating layer 103 is left only on the metal layer 102 as the fifth wiring layer. Further, an interlayer insulating film (such as silicon oxide) 104 that completely covers the metal layer 102 as the fifth wiring layer is formed on the interlayer insulating film 100.
[0750]
-Step of forming the lower electrode of the fourth MTJ element
Next, as shown in FIGS. 116 and 117, a contact hole reaching the upper electrode 99 of the third MTJ element is formed in the interlayer insulating films 100 and 104.
[0751]
This contact hole can be easily formed, for example, by forming a resist pattern on the interlayer insulating film 104 by PEP, and etching the interlayer insulating films 100 and 104 by RIE using this resist pattern as a mask. it can. After this etching, the resist pattern is removed.
[0752]
Also, for example, a barrier metal layer (such as a laminate of Ti and TiN) 105 is formed on the inner surface of the contact hole by sputtering. Subsequently, a metal layer (such as W) 106 that completely fills the contact hole is formed on the barrier metal layer 105 by sputtering, for example.
[0753]
Thereafter, the metal layer 106 is polished by using, for example, a CMP method, and the metal layer 106 is left only in the contact hole. The metal layer 106 remaining in the contact hole becomes a contact plug. Further, a metal layer (Ta or the like) 107 to be the lower electrode of the fourth MTJ element is formed on the interlayer insulating film 104 by sputtering.
[0754]
-Step of forming the fourth MTJ element and its upper electrode
Next, as shown in FIG. 118, a fourth MTJ element 108 is formed on the metal layer 107. The fourth MTJ element 108 includes a tunnel barrier, two ferromagnetic layers sandwiching the tunnel barrier, and an antiferromagnetic layer, and has a structure as shown in FIG. 48, for example.
[0755]
An interlayer insulating film (such as silicon oxide) 109 that completely covers the fourth MTJ element 108 is formed by CVD. Further, for example, the interlayer insulating film 109 is polished by the CMP method, and the interlayer insulating film 109 is left only between the fourth MTJ elements 108.
[0756]
Also, a metal layer (Ta or the like) 110 to be the upper electrode of the fourth MTJ element 108 is formed on the interlayer insulating film 109 by sputtering.
[0757]
-Patterning step of lower / upper electrode of 4th MTJ element
Next, as shown in FIGS. 119 and 120, the lower electrode 107 and the upper electrode 110 of the fourth MTJ element 108 are patterned, respectively.
[0758]
For patterning of the lower / upper electrodes 107, 110 of the fourth MTJ element 108, after forming a resist pattern on the upper electrode 110 by PEP, the lower / upper electrodes 107, 110 are formed by RIE using this resist pattern as a mask. This can be easily done by etching. Thereafter, the resist pattern is removed.
[0759]
An interlayer insulating film 111 that completely covers the upper electrode 110 of the fourth MTJ element 108 is formed using a CVD method.
[0760]
・ Wiring groove formation step
Next, as shown in FIG. 121, a wiring trench 112 is formed in the interlayer insulating film 111. In this example, the wiring trench 112 is a trench for forming a write word line and extends in the X direction. Sidewall insulating layers (such as silicon nitride) 113 for a self-aligned contact process are formed on the side surfaces of the wiring trench 112.
[0761]
The wiring trench 112 can be easily formed, for example, by forming a resist pattern on the interlayer insulating film 111 by PEP, and etching the interlayer insulating film 111 by RIE using this resist pattern as a mask. After this etching, the resist pattern is removed.
[0762]
The sidewall insulating layer 113 can be easily formed by forming an insulating film (such as silicon nitride) over the entire interlayer insulating film 111 by CVD and then etching the insulating film by RIE. it can.
[0763]
・ Step of forming the sixth wiring layer
Next, as shown in FIG. 122, for example, using a sputtering method, a barrier metal layer (a stack of Ta and TaN) is formed on the interlayer insulating film 111, the inner surface of the wiring groove 112, and the sidewall insulating layer 113. Etc.) 114. Subsequently, a metal layer (such as Cu) 115 that completely fills the wiring trench 112 is formed on the barrier metal layer 114 by sputtering, for example.
[0764]
Thereafter, as shown in FIGS. 123 and 124, the metal layer 115 is polished using, for example, a CMP method, and the metal layer 115 is left only in the wiring trench 112. The metal layer 115 remaining in the wiring trench 112 becomes a sixth wiring layer that functions as a write word line.
[0765]
In addition, an insulating layer (such as silicon nitride) 116 is formed over the interlayer insulating film 111 by a CVD method. Further, the insulating layer 116 is polished by the CMP method, and the insulating layer 116 is left only on the metal layer 115 as the sixth wiring layer. Further, an interlayer insulating film (such as silicon oxide) 117 that completely covers the metal layer 115 as the sixth wiring layer is formed on the interlayer insulating film 111.
[0766]
・ Step of forming the seventh wiring layer
Next, as shown in FIGS. 125 and 126, contact holes reaching the upper electrode 110 of the fourth MTJ element are formed in the interlayer insulating films 111 and 117.
[0767]
The contact holes can be easily formed by forming a resist pattern on the interlayer insulating film 117 by, for example, PEP, and etching the interlayer insulating films 111 and 117 by RIE using the resist pattern as a mask. it can. After this etching, the resist pattern is removed.
[0768]
In addition, a wiring trench for forming a read bit line is formed in the interlayer insulating film 117.
[0769]
The wiring trench can be easily formed by forming a resist pattern on the interlayer insulating film 117 by PEP, for example, and etching the interlayer insulating film 117 by RIE using the resist pattern as a mask. After this etching, the resist pattern is removed.
[0770]
Thereafter, for example, a barrier metal layer (such as a laminate of Ti and TiN) 118 is formed on the interlayer insulating film 117, on the inner surface of the contact hole, and on the inner surface of the wiring groove by sputtering, for example. Subsequently, a metal layer (W or the like) 119 that completely fills the contact hole and the wiring groove is formed on the barrier metal layer 118 by sputtering, for example.
[0771]
Further, the metal layer 119 and the barrier metal layer 117 are polished by, for example, a CMP method, and the metal layer 119 and the barrier metal layer 117 are left only in the contact hole and the wiring groove. The metal layer 119 remaining in the contact hole becomes a contact plug. Also, the metal layer 119 remaining in the wiring trench becomes a seventh wiring layer that functions as a read bit line.
[0772]
▲ 3 ▼ Summary
According to this manufacturing method 1, a cell array structure (one switch-nMTJ structure) in which a plurality of TMR elements are stacked in a plurality of stages and the plurality of TMR elements are connected in series between a read bit line and a ground terminal. Can be realized.
[0773]
In this example, the damascene process and the dual damascene process are employed in forming the wiring layer. However, instead of this, for example, a process of processing the wiring layer by etching may be employed.
[0774]
(2) Manufacturing method 2
In this manufacturing method 2, a plurality of TMR elements are stacked in a plurality of stages, and a magnetic array having a cell array structure (one switch-nMTJ structure) in which the plurality of TMR elements are connected in parallel between a read bit line and a ground terminal. Applies to random access memory.
[0775]
First, a cell array structure completed by the manufacturing method of the present invention will be briefly described. Thereafter, a method for manufacturing the cell array structure will be described.
[0776]
(1) Cell array structure for manufacturing method 2
FIG. 127 shows an example of a cell array structure of a magnetic random access memory composed of a plurality of TMR elements in which one block is connected in parallel.
The cell array structure is characterized in that one read bit line is arranged in one column (Y direction), and a plurality of TMR elements connected in parallel are arranged immediately below. The plurality of TMR elements constitute one read block and are connected between the read bit line and the ground terminal.
[0777]
A read selection switch (MOS transistor) RSW is disposed in the surface region of the semiconductor substrate. The source of the read selection switch RSW is connected to the ground terminal via the source line SL. The source line SL is shared by two read blocks adjacent in the column direction. The source line SL extends, for example, in a straight line in the X direction (direction perpendicular to the paper surface).
[0778]
The gate of the read selection switch (MOS transistor) RSW is a read word line RWLn. The read word line RWLn extends in the X direction. Four TMR elements (MTJ (Magnetic Tunnel Junction) elements) are stacked on the read selection switch RSW.
[0779]
Each of the TMR elements is disposed between the lower electrode and the upper electrode, and is connected in parallel to each other by a contact plug. The lower electrode of the lowermost TMR element is connected to the drain of the read selection switch (MOS transistor) RSW. The upper electrode of the uppermost TMR element is connected to a read bit line BL0 extending in the Y direction by a contact plug.
[0780]
In one row, there are three write word lines WWL0, WWL1, WWL2 extending in the X direction, and in one column, there are two write bit lines BL00, BL01 extending in the Y direction.
[0781]
When the cell array structure is viewed from the top of the semiconductor substrate, for example, a plurality of stacked TMR elements are laid out so as to overlap each other. The three write word lines are also laid out so as to overlap each other. Further, the read bit line and the two write bit lines are also laid out so as to overlap each other.
[0782]
A contact plug for connecting a plurality of TMR elements in series is laid out at a position that does not overlap a write word line or a write bit line. The upper and lower electrodes of the TMR element are formed in a pattern that facilitates contact with the contact plug.
[0783]
(2) Each step of manufacturing method 2
Hereinafter, a manufacturing method for realizing the cell array structure of FIG. 127 will be described. Since a specific manufacturing method (for example, employing a dual damascene process) will be described here, it should be noted that elements not included in the cell array structure of FIG. 127 are also described. However, the outline of the finally completed cell array structure is almost the same as the cell array structure of FIG.
[0784]
・ Element separation step
First, as shown in FIG. 128, an element isolation insulating layer 52 having an STI (Shallow Trench Isolation) structure is formed in a semiconductor substrate 51.
[0785]
The element isolation insulating layer 52 can be formed by the following process, for example.
[0786]
A mask pattern (such as silicon nitride) is formed on the semiconductor substrate 51 by PEP (Photo Engraving Process). Using this mask pattern as a mask, the semiconductor substrate 51 is etched using RIE (Reactive Ion Etching) to form a trench in the semiconductor substrate 51. For example, an insulating layer (silicon oxide or the like) is filled in the trench by using a CVD (Chemical Vapor Deposition) method and a CMP (Chemical Mechanical Polishing) method.
[0787]
Thereafter, if necessary, P-type impurities (B, BF) may be formed in the semiconductor substrate by ion implantation, for example.₂Or N-type impurities (P, As, etc.) are implanted to form a P-type well region or an N-type well region.
[0788]
・ MOSFET formation step
Next, as shown in FIG. 129, a MOS transistor that functions as a read selection switch is formed in the surface region of the semiconductor substrate 51.
[0789]
The MOS transistor can be formed by the following process, for example.
[0790]
Impurities for controlling the threshold value of the MOS transistor are ion-implanted into the channel portion in the element region surrounded by the element isolation insulating layer 52. A gate insulating film (such as silicon oxide) 53 is formed in the element region by thermal oxidation. A gate electrode material (such as polysilicon containing impurities) and a cap insulating film (such as silicon nitride) 55 are formed on the gate insulating film 53 by CVD.
[0791]
After the cap insulating film 55 is patterned by PEP, the gate electrode material and the gate insulating film 53 are processed (etched) by RIE using the cap insulating film 55 as a mask. As a result, a gate electrode 54 extending in the X direction is formed on the semiconductor substrate 51.
[0792]
P-type impurities or N-type impurities are implanted into the semiconductor substrate 51 by ion implantation using the cap insulating film 55 and the gate electrode 54 as a mask. Then, a low concentration impurity region (LDD region or extension region) is formed in the semiconductor substrate.
[0793]
An insulating film (such as silicon nitride) is formed on the entire surface of the semiconductor substrate 51 by the CVD method, and then the insulating film is etched by RIE, so that a sidewall insulating layer is formed on the side walls of the gate electrode 54 and the cap insulating film 55. 57 is formed. P-type impurities or N-type impurities are implanted into the semiconductor substrate 51 by ion implantation using the cap insulating film 55, the gate electrode 54, and the sidewall insulating layers 57 as a mask. As a result, a source region 56A and a drain region 56B are formed in the semiconductor substrate 51.
Thereafter, an interlayer insulating film (eg, silicon oxide) 58 that completely covers the MOS transistor is formed on the entire semiconductor substrate 51 by CVD. Further, the surface of the interlayer insulating film 58 is planarized by using the CMP technique.
[0794]
・ Contact hole formation step
Next, as shown in FIGS. 130 and 131, contact holes 59 reaching the source region 56 </ b> A and the drain region 56 </ b> B of the MOS transistor are formed in the interlayer insulating film 58 on the semiconductor substrate 51.
[0795]
The contact hole 59 can be easily formed by forming a resist pattern on the interlayer insulating film 58 by PEP, for example, and etching the interlayer insulating film 58 by RIE using this resist pattern as a mask. After this etching, the resist pattern is removed.
[0796]
・ Wiring groove formation step
Next, as shown in FIG. 132, a wiring trench 60 is formed in the interlayer insulating film 58 on the semiconductor substrate 51. In this example, since the wiring groove 60 extends in the X direction, the wiring groove 60 overlaps the contact hole 59 when viewed in a cross section along the Y direction. Therefore, in the figure, the wiring groove 60 is indicated by a broken line.
[0797]
The wiring trench 60 can be easily formed, for example, by forming a resist pattern on the interlayer insulating film 58 by PEP, and etching the interlayer insulating film 58 by RIE using this resist pattern as a mask. After this etching, the resist pattern is removed.
[0798]
・ First wiring layer formation step
Next, as shown in FIG. 133, for example, a barrier metal layer (Ti and TiN laminated layers) is formed on the interlayer insulating film 58, on the inner surface of the contact hole 59, and on the inner surface of the wiring groove 60 by sputtering. Etc.) 61 is formed. Subsequently, a metal layer (W or the like) 62 that completely fills the contact hole 59 and the wiring groove 60 is formed on the barrier metal layer 61 by sputtering, for example.
[0799]
Thereafter, as shown in FIG. 134, the metal layer 62 is polished by using, for example, a CMP method, and the metal layer 62 is left only in the contact hole 59 and the wiring groove 60. The metal layer 62 remaining in the contact hole 59 becomes a contact plug, and the metal layer 62 remaining in the wiring groove 60 becomes a first wiring layer. Further, an interlayer insulating film (such as silicon oxide) 63 is formed on the interlayer insulating film 58 by CVD.
[0800]
Note that a step including a contact hole forming step, a wiring groove forming step, and a first wiring layer forming step is called a dual damascene process.
[0801]
・ Wiring groove formation step
Next, as shown in FIG. 135, a wiring trench 64 is formed in the interlayer insulating film 63. In this example, the wiring trench 64 is a trench for forming a write word line and extends in the X direction. A sidewall insulating layer (such as silicon nitride) 65 for a self-aligned contact process is formed on the side surface of the wiring trench 64.
[0802]
The wiring trench 64 can be easily formed, for example, by forming a resist pattern on the interlayer insulating film 63 by PEP, and etching the interlayer insulating film 63 by RIE using this resist pattern as a mask. After this etching, the resist pattern is removed.
[0803]
The sidewall insulating layer 65 can be easily formed by forming an insulating film (such as silicon nitride) over the entire interlayer insulating film 63 by CVD and then etching the insulating film by RIE. it can.
[0804]
・ Second wiring layer formation step
Next, as shown in FIG. 136, for example, using a sputtering method, a barrier metal layer (a stack of Ta and TaN) is formed on the interlayer insulating film 63, the inner surface of the wiring groove 64, and the sidewall insulating layer 65. Etc.) 66 is formed. Subsequently, a metal layer (such as Cu) 67 that completely fills the wiring trench 64 is formed on the barrier metal layer 66 by, for example, sputtering.
[0805]
Thereafter, as shown in FIG. 137, the metal layer 67 is polished by using, for example, a CMP method, and the metal layer 67 is left only in the wiring trench 64. The metal layer 67 remaining in the wiring trench 64 becomes a second wiring layer that functions as a write word line.
[0806]
In addition, an insulating layer (such as silicon nitride) 68 is formed on the interlayer insulating film 63 by CVD. Further, the insulating layer 68 is polished by CMP, and the insulating layer 68 is left only on the metal layer 67 as the second wiring layer. An interlayer insulating film (such as silicon oxide) 69 that completely covers the metal layer 67 as the second wiring layer is formed on the interlayer insulating film 63.
[0807]
Note that a step including a wiring trench forming step and a second wiring layer forming step is called a damascene process.
[0808]
-Step of forming the lower electrode of the first MTJ element
Next, as shown in FIGS. 138 and 139, a contact hole reaching the metal layer 62 as the first wiring layer is formed in the interlayer insulating film 69.
[0809]
This contact hole can be easily formed by forming a resist pattern on the interlayer insulating film 69 by PEP, for example, and etching the interlayer insulating films 63 and 69 by RIE using this resist pattern as a mask. it can. After this etching, the resist pattern is removed.
[0810]
Further, for example, a barrier metal layer (such as a laminate of Ti and TiN) 70 is formed on the inner surface of the contact hole by sputtering. Subsequently, a metal layer (W or the like) 71 that completely fills the contact hole is formed on the barrier metal layer 70 by sputtering, for example.
[0811]
Thereafter, the metal layer 71 is polished using, for example, a CMP method, and the metal layer 71 is left only in the contact hole. The metal layer 71 remaining in the contact hole becomes a contact plug. Further, a metal layer 72 to be the lower electrode of the first MTJ element is formed on the interlayer insulating film 69 by sputtering.
[0812]
Step of forming the first MTJ element and its upper electrode
Next, as shown in FIGS. 140 and 141, the first MTJ element 73 is formed on the metal layer 72. The first MTJ element 73 includes a tunnel barrier, two ferromagnetic layers sandwiching the tunnel barrier, and an antiferromagnetic layer. For example, the first MTJ element 73 has a structure as shown in FIG.
[0813]
In this example, a protective insulating layer (such as silicon oxide) 73 </ b> A that protects the first MTJ element 73 is formed on the side surface of the first MTJ element 73. The protective insulating layer 73A can be easily formed on the side surface of the first MTJ element 73 by using the CVD method and the RIE method.
[0814]
An interlayer insulating film (such as silicon oxide) 75B that completely covers the first MTJ element 73 is formed by CVD. Further, the interlayer insulating film 75B is polished by, for example, a CMP method, and the interlayer insulating film 75B is left only between the first MTJ elements 73.
[0815]
Further, as shown in FIG. 142, a metal layer 74 to be the upper electrode of the first MTJ element 73 is formed on the interlayer insulating film 75B by sputtering. Subsequently, an alumina layer 74A that protects the first MTJ element 73 is formed on the metal layer 74 by a CVD method.
[0816]
Thereafter, a resist pattern is formed by PEP, and the alumina layer 74A, the metal layer 74, and the interlayer insulating film 75B are patterned using the resist pattern as a mask. At the same time, the surface of the metal layer 72 as the lower electrode of the first MTJ element 73 is exposed.
[0817]
When the alumina layer 74A is formed again and the alumina layer 74A is etched by RIE, the alumina layer 74A remains in a form covering the metal layer 74 as the upper electrode and the upper portion and the side wall portion of the first MTJ element 73. .
[0818]
Thereafter, an interlayer insulating film 75 that completely covers the first MTJ element 73 is formed by CVD.
[0819]
・ Wiring groove formation step
Next, as shown in FIG. 143, for example, a wiring groove 75A is formed in the interlayer insulating film 75 by RIE using the resist pattern as a mask. At this time, since the alumina layer 74A functions as an etching stopper, the bottom of the wiring groove 75A does not reach the metal layer 74 and the first MTJ element 73.
[0820]
In this example, the wiring groove 75A is a groove for forming a write bit line and extends in the Y direction. A sidewall insulating layer (such as silicon nitride) for the self-aligned contact process is formed on the side surface of the wiring trench 75A.
[0821]
The wiring trench 75A can be easily formed by forming a resist pattern on the interlayer insulating film 75 by PEP, for example, and etching the interlayer insulating film 75 by RIE using this resist pattern as a mask. After this etching, the resist pattern is removed.
[0822]
The sidewall insulating layer can be easily formed by forming an insulating film (such as silicon nitride) over the entire interlayer insulating film 75 by CVD and then etching the insulating film by RIE. .
[0823]
・ Step of forming the third wiring layer
Next, as shown in FIG. 144, for example, a sputtering method is used to form barrier metal layers (such as a stack of Ta and TaN) on the interlayer insulating film 75, on the inner surface of the wiring trench 75A, and on the sidewall insulating layers. ) 76 is formed. Subsequently, a metal layer (such as Cu) 77 that completely fills the wiring trench 75A is formed on the barrier metal layer 76 by, for example, sputtering.
[0824]
Thereafter, the metal layer 77 is polished using, for example, a CMP method, and the metal layer 77 is left only in the wiring groove 75A. The metal layer 77 remaining in the wiring trench 75A becomes a third wiring layer that functions as a write bit line.
[0825]
Further, an insulating layer (such as silicon nitride) 78 is formed on the interlayer insulating film 75 by a CVD method. Further, the insulating layer 78 is polished by the CMP method, and the insulating layer 78 is left only on the metal layer 77 as the third wiring layer. Further, an interlayer insulating film (such as silicon oxide) 79 that completely covers the metal layer 77 as the third wiring layer is formed on the interlayer insulating film 75.
[0826]
-Step of forming the lower electrode of the second MTJ element
Next, as shown in FIGS. 145 and 146, contact holes reaching the upper electrode 74 of the first MTJ element are formed in the interlayer insulating films 75 and 79 and the alumina layer 74A.
[0827]
This contact hole can be easily formed by forming a resist pattern on the interlayer insulating film 79 by PEP, for example, and etching the interlayer insulating films 75 and 79 and the alumina layer 74A by RIE using the resist pattern as a mask. Can be formed. After this etching, the resist pattern is removed.
[0828]
Also, for example, a barrier metal layer (such as a laminate of Ti and TiN) 80 is formed on the inner surface of the contact hole by sputtering. Subsequently, a metal layer (such as W) 81 that completely fills the contact hole is formed on the barrier metal layer 80 by sputtering, for example.
[0829]
Thereafter, the metal layer 81 is polished by using, for example, a CMP method, and the metal layer 81 is left only in the contact hole. The metal layer 81 remaining in the contact hole becomes a contact plug. Further, a metal layer 82 to be the lower electrode of the second MTJ element is formed on the interlayer insulating film 79 by sputtering.
[0830]
Step of forming the second MTJ element and its upper electrode
Next, as shown in FIGS. 147 and 148, the second MTJ element 84 is formed on the metal layer 82. The second MTJ element 84 includes a tunnel barrier and two ferromagnetic layers and an antiferromagnetic layer sandwiching the tunnel barrier, and has a structure as shown in FIG. 46, for example.
[0831]
In this example, a protective insulating layer (such as silicon oxide) 83A that protects the second MTJ element 84 is formed on the side surface of the second MTJ element 84. The protective insulating layer 83A can be easily formed on the side surface of the second MTJ element 84 by using the CVD method and the RIE method.
[0832]
Thereafter, the lower electrode 82 of the second MTJ element 84 is patterned. The lower electrode 82 of the second MTJ element 84 can be easily patterned by forming a resist pattern on the lower electrode 82 by PEP and then etching the lower electrode 82 by RIE using the resist pattern as a mask. . Thereafter, the resist pattern is removed.
[0833]
Next, as shown in FIG. 149, an alumina layer 83B that protects the second MTJ element 84 is formed on the second MTJ element 84 by the CVD method. Thereafter, the alumina layer 83B is etched by RIE, and as a result, the alumina layer 83B remains on the side wall portion of the second MTJ element 84.
[0834]
An interlayer insulating film (such as silicon oxide) 84B that completely covers the second MTJ element 84 is formed by using the CVD method. Further, for example, the interlayer insulating film 84B is polished by the CMP method, and the interlayer insulating film 84B is left only between the second MTJ elements 84.
[0835]
In addition, a contact hole reaching the lower electrode 72 of the first MTJ element is formed in the interlayer insulating films 75, 79, and 84B.
[0836]
This contact hole is easily formed by forming a resist pattern on the interlayer insulating film 84B by PEP, for example, and etching the interlayer insulating films 75, 79, and 84B by RIE using this resist pattern as a mask. be able to. After this etching, the resist pattern is removed.
[0837]
In this etching step, the etching rates of the alumina layers 74A, 83B are set to be sufficiently smaller than the etching rates of the interlayer insulating films 75, 79, 84B.
[0838]
That is, according to this example, even if the contact hole is misaligned, the alumina layers 74A and 83B protect the first and second MTJ elements 73 and 84, and therefore the first and second MTJ elements 73 and 84 are The situation of being etched does not occur.
[0839]
Next, as shown in FIG. 150, for example, a barrier metal layer (such as a laminate of Ti and TiN) 85A is formed on the inner surface of the contact hole by sputtering. Subsequently, a metal layer (such as W) 85B that completely fills the contact hole is formed on the barrier metal layer 85A by sputtering, for example.
[0840]
Thereafter, the metal layer 85B is polished by using, for example, a CMP method, and the metal layer 85B is left only in the contact hole. The metal layer 85B remaining in the contact hole becomes a contact plug. Further, a metal layer 85 to be the upper electrode of the second MTJ element 84 is formed on the interlayer insulating film 84B by sputtering. Subsequently, an alumina layer 85C that protects the second MTJ element 84 is formed on the metal layer 85 by a CVD method.
[0841]
Thereafter, as shown in FIG. 151, a resist pattern is formed by PEP, and the alumina layer 85C and the metal layer 85 are patterned using the resist pattern as a mask. After the alumina layer 85C is formed again, when the alumina layer 85C is etched by RIE, the alumina layer 85C remains in a form covering the metal layer 85 as the upper electrode and the upper and side wall portions of the second MTJ element 84. .
[0841]
Thereafter, an interlayer insulating film 86 that completely covers the second MTJ element 85 is formed by CVD.
[0843]
・ Wiring groove formation step
Next, as shown in FIG. 152, for example, a wiring groove 87 is formed in the interlayer insulating film 86 by RIE using the resist pattern as a mask. At this time, since the alumina layer 85C functions as an etching stopper, the bottom of the wiring groove 87 does not reach the metal layer 85 and the second MTJ element 84.
[0844]
In this example, the wiring groove 87 is a groove for forming a write word line and extends in the X direction. A sidewall insulating layer (such as silicon nitride) 88 for a self-aligned contact process is formed on the side surface of the wiring groove 87.
[0845]
The wiring groove 87 can be easily formed by forming a resist pattern on the interlayer insulating film 86 by PEP, for example, and etching the interlayer insulating film 86 by RIE using this resist pattern as a mask. After this etching, the resist pattern is removed.
[0846]
The sidewall insulating layer 88 can be easily formed by forming an insulating film (such as silicon nitride) over the entire interlayer insulating film 86 by CVD and then etching the insulating film by RIE. it can.
[0847]
・ Step of forming the fourth wiring layer
Next, as shown in FIG. 153, for example, a barrier metal layer (stacking of Ta and TaN) is formed on the interlayer insulating film 86, on the inner surface of the wiring groove 87, and on the sidewall insulating layer 88 by sputtering. Etc.) 89 is formed. Subsequently, a metal layer (such as Cu) 90 that completely fills the wiring trench 87 is formed on the barrier metal layer 89 by, for example, sputtering.
[0848]
Thereafter, the metal layer 90 is polished using, for example, a CMP method, and the metal layer 90 is left only in the wiring groove 87. The metal layer 90 remaining in the wiring trench 87 becomes a fourth wiring layer that functions as a write word line.
[0849]
Further, an insulating layer (such as silicon nitride) 92 is formed on the interlayer insulating film 86 by a CVD method. Further, the insulating layer 92 is polished by CMP, and the insulating layer 92 is left only on the metal layer 90 as the fourth wiring layer. Further, an interlayer insulating film (such as silicon oxide) 93 that completely covers the metal layer 90 as the fourth wiring layer is formed on the interlayer insulating film 86.
[0850]
-Step of forming the lower electrode of the third MTJ element
Next, as shown in FIGS. 154 and 155, a contact hole reaching the upper electrode 85 of the second MTJ element 84 is formed in the interlayer insulating films 86 and 93.
[0851]
This contact hole can be easily formed by forming a resist pattern on the interlayer insulating film 93 by PEP, for example, and etching the interlayer insulating films 86 and 93 by RIE using this resist pattern as a mask. it can. After this etching, the resist pattern is removed.
[0852]
Further, for example, a barrier metal layer (such as a laminate of Ti and TiN) 94 is formed on the inner surface of the contact hole by sputtering. Subsequently, a metal layer (such as W) 95 that completely fills the contact hole is formed on the barrier metal layer 94 by sputtering, for example.
[0853]
Thereafter, the metal layer 95 is polished using, for example, a CMP method, and the metal layer 95 is left only in the contact hole. The metal layer 95 remaining in the contact hole becomes a contact plug. Further, a metal layer 96 to be the lower electrode of the third MTJ element is formed on the interlayer insulating film 93 by the CVD method.
[0854]
-Step of forming the third MTJ element and its upper electrode
Next, as shown in FIGS. 156 and 157, the third MTJ element 97 is formed on the metal layer 96. The third MTJ element 97 includes a tunnel barrier, two ferromagnetic layers sandwiching the tunnel barrier, and an antiferromagnetic layer, and has a structure as shown in FIG. 47, for example.
[0855]
In this example, a protective insulating layer (such as silicon oxide) 97A that protects the third MTJ element 97 is formed on the side surface of the third MTJ element 97. The protective insulating layer 97A can be easily formed on the side surface of the third MTJ element 97 by using the CVD method and the RIE method.
[0856]
Thereafter, the lower electrode 96 of the third MTJ element 97 is patterned. The lower electrode 96 of the third MTJ element 97 can be easily patterned by forming a resist pattern on the lower electrode 96 by PEP and then etching the lower electrode 96 by RIE using the resist pattern as a mask. . Thereafter, the resist pattern is removed.
[0857]
Next, as shown in FIG. 158, an interlayer insulating film (such as silicon oxide) 98 that completely covers the third MTJ element 97 is formed by CVD. Further, for example, the interlayer insulating film 98 is polished by the CMP method, and the interlayer insulating film 98 is left only between the third MTJ elements 97.
[0858]
Thereafter, contact holes reaching the lower electrode 82 of the second MTJ element 84 are formed in the interlayer insulating films 86, 93, 98.
[0859]
This contact hole is easily formed by forming a resist pattern on the interlayer insulating film 98 by, for example, PEP, and etching the interlayer insulating films 86, 93, 98 by RIE using this resist pattern as a mask. be able to. After this etching, the resist pattern is removed.
[0860]
Next, as shown in FIG. 159, for example, a barrier metal layer (such as a laminate of Ti and TiN) 99A is formed on the inner surface of the contact hole by sputtering. Subsequently, a metal layer (such as W) 99B that completely fills the contact hole is formed on the barrier metal layer 99A by, for example, sputtering.
[0861]
Thereafter, the metal layer 99B is polished by using, for example, a CMP method, and the metal layer 99B is left only in the contact hole. The metal layer 99B remaining in the contact hole becomes a contact plug. Further, a metal layer 99 to be the upper electrode of the third MTJ element is formed on the interlayer insulating film 98 by the CVD method.
[0862]
Also, an alumina layer 99C that protects the third MTJ element 97 is formed on the upper electrode 99 of the third MTJ element 97 by CVD.
[0863]
Next, as shown in FIG. 160, a resist pattern is formed by PEP, and the alumina layer 99C and the metal layer 99 are patterned using the resist pattern as a mask. After the alumina layer 99C is formed again, when the alumina layer 99C is etched by RIE, the alumina layer 99C remains in a form covering the metal layer 99 as the upper electrode and the upper part and the side wall part of the third MTJ element 97. .
[0864]
Thereafter, an interlayer insulating film 100 that completely covers the third MTJ element 97 is formed by CVD.
[0865]
・ Wiring groove formation step
Next, as shown in FIGS. 161 and 162, a wiring groove extending in the Y direction is formed in the interlayer insulating film 100 by RIE, for example, using the resist pattern as a mask. At this time, since the alumina layer 99C functions as an etching stopper, the bottom of the wiring groove does not reach the metal layer 99 and the third MTJ element 97.
[0866]
In this example, the wiring groove is a groove for forming a write bit line and extends in the Y direction. A sidewall insulating layer (such as silicon nitride) for a self-aligned contact process is formed on the side surface of the wiring trench.
[0867]
The wiring trench can be easily formed, for example, by forming a resist pattern on the interlayer insulating film 100 by PEP, and etching the interlayer insulating film 100 by RIE using this resist pattern as a mask. After this etching, the resist pattern is removed.
[0868]
The sidewall insulating layer can be easily formed by forming an insulating film (such as silicon nitride) over the entire interlayer insulating film 100 by a CVD method and then etching the insulating film by RIE. .
[0869]
・ Fifth wiring layer formation step
Next, as shown in FIGS. 161 and 162, for example, using a sputtering method, a barrier metal layer (Ta and TaN layers) is formed on the interlayer insulating film 100, the inner surface of the wiring trench, and the sidewall insulating layer, respectively. 101) is formed. Subsequently, a metal layer (Cu or the like) 102 that completely fills the wiring groove is formed on the barrier metal layer 101 by, for example, sputtering.
[0870]
Thereafter, the metal layer 102 is polished by using, for example, a CMP method, and the metal layer 102 is left only in the wiring trench. The metal layer 102 remaining in the wiring trench becomes a fifth wiring layer functioning as a write bit line.
[0871]
Further, an insulating layer (such as silicon nitride) 103 is formed on the interlayer insulating film 100 by a CVD method. Further, this insulating layer 103 is polished by CMP, and this insulating layer 103 is left only on the metal layer 102 as the fifth wiring layer. Further, an interlayer insulating film (such as silicon oxide) 104 that completely covers the metal layer 102 as the fifth wiring layer is formed on the interlayer insulating film 100.
[0872]
-Step of forming the lower electrode of the fourth MTJ element
Next, as shown in FIGS. 163 and 164, contact holes reaching the upper electrode 99 of the third MTJ element 97 are formed in the interlayer insulating films 100 and 104 and the alumina layer 99C.
[0873]
This contact hole can be easily formed by forming a resist pattern on the interlayer insulating film 104 by PEP and etching the interlayer insulating films 100 and 104 and the alumina layer 99C by RIE using the resist pattern as a mask. Can be formed. After this etching, the resist pattern is removed.
[0874]
Further, for example, a barrier metal layer (such as a laminate of Ti and TiN) 80X is formed on the inner surface of the contact hole by sputtering. Subsequently, a metal layer (such as W) 81X that completely fills the contact hole is formed on the barrier metal layer 80X by sputtering, for example.
[0875]
Thereafter, the metal layer 81X is polished by using, for example, a CMP method, and the metal layer 81X is left only in the contact hole. The metal layer 81X remaining in the contact hole becomes a contact plug. Further, a metal layer 107 to be the lower electrode of the fourth MTJ element is formed on the interlayer insulating film 104 by sputtering.
[0876]
-Step of forming the fourth MTJ element and its upper electrode
Next, as shown in FIGS. 163 and 164, the fourth MTJ element 108 is formed on the metal layer 107. The fourth MTJ element 108 includes a tunnel barrier, two ferromagnetic layers sandwiching the tunnel barrier, and an antiferromagnetic layer, and has a structure as shown in FIG. 48, for example.
[0877]
In this example, a protective insulating layer (such as silicon oxide) 108A that protects the fourth MTJ element 108 is formed on the side surface of the fourth MTJ element 108. The protective insulating layer 108A can be easily formed on the side surface of the fourth MTJ element 108 by using the CVD method and the RIE method.
[0878]
Thereafter, the lower electrode 107 of the fourth MTJ element 108 is patterned. The patterning of the lower electrode 107 of the fourth MTJ element 108 can be easily performed by forming a resist pattern on the lower electrode 107 by PEP and then etching the lower electrode 107 by RIE using this resist pattern as a mask. . Thereafter, the resist pattern is removed.
[0879]
Next, as shown in FIG. 165, an alumina layer 108B that protects the fourth MTJ element 108 is formed on the fourth MTJ element 108 by CVD. Thereafter, the alumina layer 108B is etched by RIE, and as a result, the alumina layer 108B remains on the side wall portion of the fourth MTJ element 108.
[0880]
An interlayer insulating film (such as silicon oxide) 109 that completely covers the fourth MTJ element 108 is formed by CVD. Further, for example, the interlayer insulating film 109 is polished by the CMP method, and the interlayer insulating film 109 is left only between the fourth MTJ elements 108.
[0881]
Further, contact holes reaching the lower electrode 96 of the third MTJ element 97 are formed in the interlayer insulating films 100, 104, and 109.
[0882]
This contact hole is easily formed by forming a resist pattern on the interlayer insulating film 109 by, for example, PEP, and etching the interlayer insulating films 100, 104, and 109 by RIE using this resist pattern as a mask. be able to. After this etching, the resist pattern is removed.
[0883]
In this etching step, the etching rates of the alumina layers 99C and 108B are set to be sufficiently smaller than the etching rates of the interlayer insulating films 100, 104, and 109.
[0884]
That is, according to the present example, even if contact hole misalignment occurs, the alumina layers 99C and 108B protect the third and fourth MTJ elements 97 and 108, so that the third and fourth MTJ elements 97 and 108 are The situation of being etched does not occur.
[0885]
Next, as shown in FIG. 166, for example, a barrier metal layer (such as a laminate of Ti and TiN) 105 is formed on the inner surface of the contact hole by sputtering. Subsequently, a metal layer (such as W) 106 that completely fills the contact hole is formed on the barrier metal layer 105 by sputtering, for example.
[0886]
Thereafter, the metal layer 106 is polished by using, for example, a CMP method, and the metal layer 106 is left only in the contact hole. The metal layer 106 remaining in the contact hole becomes a contact plug. Further, a metal layer 107 to be the upper electrode of the fourth MTJ element 108 is formed on the interlayer insulating film 109 by sputtering. Subsequently, an alumina layer 107A that protects the fourth MTJ element 108 is formed on the metal layer 107 by a CVD method.
[0887]
Next, as shown in FIG. 167, a resist pattern is formed by PEP, and the alumina layer 107A and the metal layer 107 are patterned using the resist pattern as a mask.
[0888]
After the alumina layer 107A is formed again, when the alumina layer 107A is etched by RIE, the alumina layer 107A remains so as to cover the metal layer 107 as the upper electrode and the upper and side wall portions of the fourth MTJ element 108. .
[0889]
Thereafter, an interlayer insulating film 111 that completely covers the fourth MTJ element 108 is formed by CVD.
[0890]
・ Wiring groove formation step
Next, as shown in FIGS. 168 and 169, for example, a wiring groove 112 extending in the X direction is formed in the interlayer insulating film 111 by RIE using the resist pattern as a mask. At this time, since the alumina layer 107A functions as an etching stopper, the bottom of the wiring groove 112 does not reach the metal layer 107 and the fourth MTJ element 108.
[0891]
In this example, the wiring trench 112 is a trench for forming a write word line and extends in the X direction. Sidewall insulating layers (such as silicon nitride) 113 for a self-aligned contact process are formed on the side surfaces of the wiring trench 112.
[0892]
The wiring trench 112 can be easily formed, for example, by forming a resist pattern on the interlayer insulating film 111 by PEP, and etching the interlayer insulating film 111 by RIE using this resist pattern as a mask. After this etching, the resist pattern is removed.
[0893]
The sidewall insulating layer 113 can be easily formed by forming an insulating film (such as silicon nitride) over the entire interlayer insulating film 111 by CVD and then etching the insulating film by RIE. it can.
[0894]
・ Step of forming the sixth wiring layer
Next, as shown in FIGS. 168 and 169, for example, using a sputtering method, barrier metal layers (Ta and Ta) are formed on the interlayer insulating film 111, the inner surface of the wiring groove 112, and the sidewall insulating layer 113, respectively. (TaN stack or the like) 114 is formed. Subsequently, a metal layer (such as Cu) 115 that completely fills the wiring trench 112 is formed on the barrier metal layer 114 by sputtering, for example.
[0895]
Thereafter, the metal layer 115 is polished by using, for example, a CMP method, and the metal layer 115 is left only in the wiring groove 112. The metal layer 115 remaining in the wiring trench 112 becomes a sixth wiring layer that functions as a write word line.
[0896]
In addition, an insulating layer (such as silicon nitride) 116 is formed over the interlayer insulating film 111 by a CVD method. Further, the insulating layer 116 is polished by the CMP method, and the insulating layer 116 is left only on the metal layer 115 as the sixth wiring layer.
[0897]
・ Step of forming the seventh wiring layer
Next, as shown in FIGS. 170 and 171, an interlayer insulating film (such as silicon oxide) 117 that completely covers the metal layer 115 as the sixth wiring layer is formed on the interlayer insulating film 111. A contact hole reaching the lower electrode 107 of the fourth MTJ element is formed in the interlayer insulating films 111 and 117.
[0898]
The contact holes can be easily formed by forming a resist pattern on the interlayer insulating film 117 by, for example, PEP, and etching the interlayer insulating films 111 and 117 by RIE using the resist pattern as a mask. it can. After this etching, the resist pattern is removed.
[0899]
In addition, a wiring trench for forming a read bit line is formed in the interlayer insulating film 117.
[0900]
The wiring trench can be easily formed by forming a resist pattern on the interlayer insulating film 117 by PEP, for example, and etching the interlayer insulating film 117 by RIE using the resist pattern as a mask. After this etching, the resist pattern is removed.
[0901]
Thereafter, for example, a barrier metal layer (such as a laminate of Ti and TiN) 118 is formed on the interlayer insulating film 117, on the inner surface of the contact hole, and on the inner surface of the wiring groove by sputtering, for example. Subsequently, a metal layer (W or the like) 119 that completely fills the contact hole and the wiring groove is formed on the barrier metal layer 118 by sputtering, for example.
[0902]
Further, the metal layer 119 and the barrier metal layer 117 are polished by, for example, a CMP method, and the metal layer 119 and the barrier metal layer 117 are left only in the contact hole and the wiring groove. The metal layer 119 remaining in the contact hole becomes a contact plug. Also, the metal layer 119 remaining in the wiring trench becomes a seventh wiring layer that functions as a read bit line.
[0903]
▲ 3 ▼ Summary
According to this manufacturing method 2, a cell array structure (one switch-nMTJ structure) in which a plurality of TMR elements are stacked in a plurality of stages and the plurality of TMR elements are connected in parallel between a read bit line and a ground terminal. Can be realized.
[0904]
In this example, the damascene process and the dual damascene process are employed in forming the wiring layer. However, instead of this, for example, a process of processing the wiring layer by etching may be employed.
[0905]
(3) Manufacturing method 3
This manufacturing method 3 has a cell array structure (one switch-nMTJ structure) in which a plurality of TMR elements are stacked in a plurality of stages, and the plurality of TMR elements are connected in series and parallel between a read bit line and a ground terminal. Applied to magnetic random access memory.
[0906]
First, a cell array structure completed by the manufacturing method of the present invention will be briefly described. Thereafter, a method for manufacturing the cell array structure will be described.
[0907]
(1) Cell array structure for manufacturing method 3
FIG. 172 shows an example of a cell array structure of a magnetic random access memory composed of a plurality of TMR elements in which one block is connected in series and parallel.
The cell array structure is characterized in that one read bit line is arranged in one column (Y direction), and a plurality of TMR elements connected in series and parallel are arranged immediately below. The plurality of TMR elements constitute one read block and are connected between the read bit line and the ground terminal.
[0908]
A read selection switch (MOS transistor) RSW is disposed in the surface region of the semiconductor substrate. The source of the read selection switch RSW is connected to the ground terminal via the source line SL. The source line SL is shared by two read blocks adjacent in the column direction. The source line SL extends, for example, in a straight line in the X direction (direction perpendicular to the paper surface).
[0909]
The gate of the read selection switch (MOS transistor) RSW is a read word line RWLn. The read word line RWLn extends in the X direction. Four TMR elements (MTJ (Magnetic Tunnel Junction) elements) are stacked on the read selection switch RSW.
[0910]
Each of the TMR elements is disposed between the lower electrode and the upper electrode, and is connected in series and parallel to each other by a contact plug. The lower electrode of the lowermost TMR element is connected to the drain of the read selection switch (MOS transistor) RSW. The upper electrode of the uppermost TMR element is connected to a read bit line BL0 extending in the Y direction by a contact plug.
[0911]
In one row, there are three write word lines WWL0, WWL1, WWL2 extending in the X direction, and in one column, there are two write bit lines BL00, BL01 extending in the Y direction.
[0912]
When the cell array structure is viewed from the top of the semiconductor substrate, for example, a plurality of stacked TMR elements are laid out so as to overlap each other. The three write word lines are also laid out so as to overlap each other. Further, the read bit line and the two write bit lines are also laid out so as to overlap each other.
[0913]
A contact plug for connecting a plurality of TMR elements in series is laid out at a position that does not overlap a write word line or a write bit line. The upper and lower electrodes of the TMR element are formed in a pattern that facilitates contact with the contact plug.
[0914]
(2) Each step of manufacturing method 3
Hereinafter, a manufacturing method for realizing the cell array structure of FIG. 172 will be described. Here, since a specific manufacturing method (for example, adoption of a dual damascene process) will be described, it should be noted that elements not included in the cell array structure of FIG. 172 are also described. However, the outline of the finally completed cell array structure is almost the same as the cell array structure of FIG.
[0915]
・ Element separation step
First, as shown in FIG. 173, an element isolation insulating layer 52 having an STI (Shallow Trench Isolation) structure is formed in a semiconductor substrate 51.
[0916]
The element isolation insulating layer 52 can be formed by the following process, for example.
[0917]
A mask pattern (such as silicon nitride) is formed on the semiconductor substrate 51 by PEP (Photo Engraving Process). Using this mask pattern as a mask, the semiconductor substrate 51 is etched using RIE (Reactive Ion Etching) to form a trench in the semiconductor substrate 51. For example, an insulating layer (silicon oxide or the like) is filled in the trench by using a CVD (Chemical Vapor Deposition) method and a CMP (Chemical Mechanical Polishing) method.
[0918]
Thereafter, if necessary, P-type impurities (B, BF) may be formed in the semiconductor substrate by ion implantation, for example.₂Or N-type impurities (P, As, etc.) are implanted to form a P-type well region or an N-type well region.
[0919]
・ MOSFET formation step
Next, as shown in FIG. 174, a MOS transistor that functions as a read selection switch is formed in the surface region of the semiconductor substrate 51.
[0920]
The MOS transistor can be formed by the following process, for example.
[0921]
Impurities for controlling the threshold value of the MOS transistor are ion-implanted into the channel portion in the element region surrounded by the element isolation insulating layer 52. A gate insulating film (such as silicon oxide) 53 is formed in the element region by thermal oxidation. A gate electrode material (such as polysilicon containing impurities) and a cap insulating film (such as silicon nitride) 55 are formed on the gate insulating film 53 by CVD.
[0922]
After the cap insulating film 55 is patterned by PEP, the gate electrode material and the gate insulating film 53 are processed (etched) by RIE using the cap insulating film 55 as a mask. As a result, a gate electrode 54 extending in the X direction is formed on the semiconductor substrate 51.
[0923]
P-type impurities or N-type impurities are implanted into the semiconductor substrate 51 by ion implantation using the cap insulating film 55 and the gate electrode 54 as a mask. Then, a low concentration impurity region (LDD region or extension region) is formed in the semiconductor substrate.
[0924]
An insulating film (such as silicon nitride) is formed on the entire surface of the semiconductor substrate 51 by the CVD method, and then the insulating film is etched by RIE, so that a sidewall insulating layer is formed on the side walls of the gate electrode 54 and the cap insulating film 55. 57 is formed. P-type impurities or N-type impurities are implanted into the semiconductor substrate 51 by ion implantation using the cap insulating film 55, the gate electrode 54, and the sidewall insulating layers 57 as a mask. As a result, a source region 56A and a drain region 56B are formed in the semiconductor substrate 51.
Thereafter, an interlayer insulating film (eg, silicon oxide) 58 that completely covers the MOS transistor is formed on the entire semiconductor substrate 51 by CVD. Further, the surface of the interlayer insulating film 58 is planarized by using the CMP technique.
[0925]
・ Contact hole formation step
Next, as shown in FIGS. 175 and 176, contact holes 59 reaching the source region 56 </ b> A and the drain region 56 </ b> B of the MOS transistor are formed in the interlayer insulating film 58 on the semiconductor substrate 51.
[0926]
The contact hole 59 can be easily formed by forming a resist pattern on the interlayer insulating film 58 by PEP, for example, and etching the interlayer insulating film 58 by RIE using this resist pattern as a mask. After this etching, the resist pattern is removed.
[0927]
・ Wiring groove formation step
Next, as shown in FIG. 177, a wiring trench 60 is formed in the interlayer insulating film 58 on the semiconductor substrate 51. In this example, since the wiring groove 60 extends in the X direction, the wiring groove 60 overlaps the contact hole 59 when viewed in a cross section along the Y direction. Therefore, in the figure, the wiring groove 60 is indicated by a broken line.
[0928]
The wiring trench 60 can be easily formed, for example, by forming a resist pattern on the interlayer insulating film 58 by PEP, and etching the interlayer insulating film 58 by RIE using this resist pattern as a mask. After this etching, the resist pattern is removed.
[0929]
・ First wiring layer formation step
Next, as shown in FIG. 178, for example, a sputtering method is used to form barrier metal layers (lamination of Ti and TiN) on the interlayer insulating film 58, on the inner surface of the contact hole 59, and on the inner surface of the wiring groove 60. Etc.) 61 is formed. Subsequently, a metal layer (W or the like) 62 that completely fills the contact hole 59 and the wiring groove 60 is formed on the barrier metal layer 61 by sputtering, for example.
[0930]
Thereafter, as shown in FIG. 179, the metal layer 62 is polished by using, for example, a CMP method, and the metal layer 62 is left only in the contact hole 59 and the wiring groove 60. The metal layer 62 remaining in the contact hole 59 becomes a contact plug, and the metal layer 62 remaining in the wiring groove 60 becomes a first wiring layer. Further, an interlayer insulating film (such as silicon oxide) 63 is formed on the interlayer insulating film 58 by CVD.
[0931]
Note that a step including a contact hole forming step, a wiring groove forming step, and a first wiring layer forming step is called a dual damascene process.
[0932]
・ Wiring groove formation step
Next, as shown in FIG. 180, a wiring groove 64 is formed in the interlayer insulating film 63. In this example, the wiring trench 64 is a trench for forming a write word line and extends in the X direction. A sidewall insulating layer (such as silicon nitride) 65 for a self-aligned contact process is formed on the side surface of the wiring trench 64.
[0933]
The wiring trench 64 can be easily formed, for example, by forming a resist pattern on the interlayer insulating film 63 by PEP, and etching the interlayer insulating film 63 by RIE using this resist pattern as a mask. After this etching, the resist pattern is removed.
[0934]
The sidewall insulating layer 65 can be easily formed by forming an insulating film (such as silicon nitride) over the entire interlayer insulating film 63 by CVD and then etching the insulating film by RIE. it can.
[0935]
・ Second wiring layer formation step
Next, as shown in FIG. 181, for example, a sputtering method is used to form barrier metal layers (Ta and TaN laminated layers) on the interlayer insulating film 63, the inner surface of the wiring trench 64, and the sidewall insulating layer 65, respectively. Etc.) 66 is formed. Subsequently, a metal layer (such as Cu) 67 that completely fills the wiring trench 64 is formed on the barrier metal layer 66 by, for example, sputtering.
[0936]
Thereafter, as shown in FIG. 182, the metal layer 67 is polished using, for example, a CMP method, and the metal layer 67 is left only in the wiring trench 64. The metal layer 67 remaining in the wiring trench 64 becomes a second wiring layer that functions as a write word line.
[0937]
In addition, an insulating layer (such as silicon nitride) 68 is formed on the interlayer insulating film 63 by CVD. Further, the insulating layer 68 is polished by CMP, and the insulating layer 68 is left only on the metal layer 67 as the second wiring layer. An interlayer insulating film (such as silicon oxide) 69 that completely covers the metal layer 67 as the second wiring layer is formed on the interlayer insulating film 63.
[0938]
Note that a step including a wiring trench forming step and a second wiring layer forming step is called a damascene process.
[0939]
-Step of forming the lower electrode of the first MTJ element
Next, as shown in FIGS. 183 and 184, a contact hole reaching the metal layer 62 as the first wiring layer is formed in the interlayer insulating film 69.
[0940]
This contact hole can be easily formed by forming a resist pattern on the interlayer insulating film 69 by PEP, for example, and etching the interlayer insulating films 63 and 69 by RIE using this resist pattern as a mask. it can. After this etching, the resist pattern is removed.
[0941]
Further, for example, a barrier metal layer (such as a laminate of Ti and TiN) 70 is formed on the inner surface of the contact hole by sputtering. Subsequently, a metal layer (W or the like) 71 that completely fills the contact hole is formed on the barrier metal layer 70 by sputtering, for example.
[0942]
Thereafter, the metal layer 71 is polished using, for example, a CMP method, and the metal layer 71 is left only in the contact hole. The metal layer 71 remaining in the contact hole becomes a contact plug. Further, a metal layer 72 to be the lower electrode of the first MTJ element is formed on the interlayer insulating film 69 by sputtering.
[0943]
Step of forming the first MTJ element and its upper electrode
Next, as shown in FIGS. 185 and 186, the first MTJ element 73 is formed on the metal layer 72. The first MTJ element 73 includes a tunnel barrier, two ferromagnetic layers sandwiching the tunnel barrier, and an antiferromagnetic layer. For example, the first MTJ element 73 has a structure as shown in FIG.
[0944]
In this example, a protective insulating layer (such as silicon oxide) 73 </ b> A that protects the first MTJ element 73 is formed on the side surface of the first MTJ element 73. The protective insulating layer 73A can be easily formed on the side surface of the first MTJ element 73 by using the CVD method and the RIE method.
[0945]
An interlayer insulating film (such as silicon oxide) 75B that completely covers the first MTJ element 73 is formed by CVD. Further, the interlayer insulating film 75B is polished by, for example, a CMP method, and the interlayer insulating film 75B is left only between the first MTJ elements 73.
[0946]
Further, as shown in FIG. 187, a metal layer 74 to be the upper electrode of the first MTJ element 73 is formed on the interlayer insulating film 75B by sputtering. Subsequently, an alumina layer 74A that protects the first MTJ element 73 is formed on the metal layer 74 by a CVD method.
[0947]
Thereafter, a resist pattern is formed by PEP, and the alumina layer 74A, the metal layer 74, and the interlayer insulating film 75B are patterned using the resist pattern as a mask. At the same time, the surface of the metal layer 72 as the lower electrode of the first MTJ element 73 is exposed.
[0948]
When the alumina layer 74A is formed again and the alumina layer 74A is etched by RIE, the alumina layer 74A remains in a form covering the metal layer 74 as the upper electrode and the upper portion and the side wall portion of the first MTJ element 73. .
[0949]
Thereafter, an interlayer insulating film 75 that completely covers the first MTJ element 73 is formed by CVD.
[0950]
・ Wiring groove formation step
Next, as shown in FIG. 188, for example, a wiring groove 75A is formed in the interlayer insulating film 75 by RIE using the resist pattern as a mask. At this time, since the alumina layer 74A functions as an etching stopper, the bottom of the wiring groove 75A does not reach the metal layer 74 and the first MTJ element 73.
[0951]
In this example, the wiring groove 75A is a groove for forming a write bit line and extends in the Y direction. A sidewall insulating layer (such as silicon nitride) for the self-aligned contact process is formed on the side surface of the wiring trench 75A.
[0952]
The wiring trench 75A can be easily formed by forming a resist pattern on the interlayer insulating film 75 by PEP, for example, and etching the interlayer insulating film 75 by RIE using this resist pattern as a mask. After this etching, the resist pattern is removed.
[0953]
The sidewall insulating layer can be easily formed by forming an insulating film (such as silicon nitride) over the entire interlayer insulating film 75 by CVD and then etching the insulating film by RIE. .
[0954]
・ Step of forming the third wiring layer
Next, as shown in FIG. 189, for example, using a sputtering method, a barrier metal layer (such as a stack of Ta and TaN) is formed on the interlayer insulating film 75, on the inner surface of the wiring trench 75A, and on the sidewall insulating layer. ) 76 is formed. Subsequently, a metal layer (such as Cu) 77 that completely fills the wiring trench 75A is formed on the barrier metal layer 76 by, for example, sputtering.
[0955]
Thereafter, the metal layer 77 is polished using, for example, a CMP method, and the metal layer 77 is left only in the wiring groove 75A. The metal layer 77 remaining in the wiring trench 75A becomes a third wiring layer that functions as a write bit line.
[0956]
Further, an insulating layer (such as silicon nitride) 78 is formed on the interlayer insulating film 75 by a CVD method. Further, the insulating layer 78 is polished by the CMP method, and the insulating layer 78 is left only on the metal layer 77 as the third wiring layer. Further, an interlayer insulating film (such as silicon oxide) 79 that completely covers the metal layer 77 as the third wiring layer is formed on the interlayer insulating film 75.
[0957]
-Step of forming the lower electrode of the second MTJ element
Next, as shown in FIGS. 190 and 191, contact holes reaching the upper electrode 74 of the first MTJ element are formed in the interlayer insulating films 75 and 79 and the alumina layer 74A.
[0958]
This contact hole can be easily formed by forming a resist pattern on the interlayer insulating film 79 by PEP, for example, and etching the interlayer insulating films 75 and 79 and the alumina layer 74A by RIE using the resist pattern as a mask. Can be formed. After this etching, the resist pattern is removed.
[0959]
Also, for example, a barrier metal layer (such as a laminate of Ti and TiN) 80 is formed on the inner surface of the contact hole by sputtering. Subsequently, a metal layer (such as W) 81 that completely fills the contact hole is formed on the barrier metal layer 80 by sputtering, for example.
[0960]
Thereafter, the metal layer 81 is polished by using, for example, a CMP method, and the metal layer 81 is left only in the contact hole. The metal layer 81 remaining in the contact hole becomes a contact plug. Further, a metal layer 82 to be the lower electrode of the second MTJ element is formed on the interlayer insulating film 79 by sputtering.
[0961]
Step of forming the second MTJ element and its upper electrode
Next, as shown in FIGS. 192 and 193, the second MTJ element 84 is formed on the metal layer 82. The second MTJ element 84 includes a tunnel barrier and two ferromagnetic layers and an antiferromagnetic layer sandwiching the tunnel barrier, and has a structure as shown in FIG. 46, for example.
[0962]
In this example, a protective insulating layer (such as silicon oxide) 83A that protects the second MTJ element 84 is formed on the side surface of the second MTJ element 84. The protective insulating layer 83A can be easily formed on the side surface of the second MTJ element 84 by using the CVD method and the RIE method.
[0964]
Thereafter, the lower electrode 82 of the second MTJ element 84 is patterned. The lower electrode 82 of the second MTJ element 84 can be easily patterned by forming a resist pattern on the lower electrode 82 by PEP and then etching the lower electrode 82 by RIE using the resist pattern as a mask. . Thereafter, the resist pattern is removed.
[0964]
Next, as shown in FIG. 194, an alumina layer 83B that protects the second MTJ element 84 is formed on the second MTJ element 84 by the CVD method. Thereafter, the alumina layer 83B is etched by RIE, and as a result, the alumina layer 83B remains on the side wall portion of the second MTJ element 84.
[0965]
An interlayer insulating film (such as silicon oxide) 84B that completely covers the second MTJ element 84 is formed by using the CVD method. Further, for example, the interlayer insulating film 84B is polished by the CMP method, and the interlayer insulating film 84B is left only between the second MTJ elements 84.
[0966]
In addition, a contact hole reaching the lower electrode 72 of the first MTJ element is formed in the interlayer insulating films 75, 79, and 84B.
[0967]
This contact hole is easily formed by forming a resist pattern on the interlayer insulating film 84B by PEP, for example, and etching the interlayer insulating films 75, 79, and 84B by RIE using this resist pattern as a mask. be able to. After this etching, the resist pattern is removed.
[0968]
In this etching step, the etching rates of the alumina layers 74A, 83B are set to be sufficiently smaller than the etching rates of the interlayer insulating films 75, 79, 84B.
[0969]
That is, according to this example, even if the contact hole is misaligned, the alumina layers 74A and 83B protect the first and second MTJ elements 73 and 84, and therefore the first and second MTJ elements 73 and 84 are The situation of being etched does not occur.
[0970]
Next, as shown in FIG. 195, for example, a barrier metal layer (such as a laminate of Ti and TiN) 85A is formed on the inner surface of the contact hole by sputtering. Subsequently, a metal layer (such as W) 85B that completely fills the contact hole is formed on the barrier metal layer 85A by sputtering, for example.
[0971]
Thereafter, the metal layer 85B is polished by using, for example, a CMP method, and the metal layer 85B is left only in the contact hole. The metal layer 85B remaining in the contact hole becomes a contact plug. Further, a metal layer 85 to be the upper electrode of the second MTJ element 84 is formed on the interlayer insulating film 84B by sputtering. Subsequently, an alumina layer 85C that protects the second MTJ element 84 is formed on the metal layer 85 by a CVD method.
[0972]
Thereafter, as shown in FIG. 196, a resist pattern is formed by PEP, and the alumina layer 85C and the metal layer 85 are patterned using the resist pattern as a mask. After the alumina layer 85C is formed again, when the alumina layer 85C is etched by RIE, the alumina layer 85C remains in a form covering the metal layer 85 as the upper electrode and the upper and side wall portions of the second MTJ element 84. .
[0973]
Thereafter, an interlayer insulating film 86 that completely covers the second MTJ element 85 is formed by CVD.
[0974]
・ Wiring groove formation step
Next, as shown in FIG. 197, for example, a wiring groove 87 is formed in the interlayer insulating film 86 by RIE using the resist pattern as a mask. At this time, since the alumina layer 85C functions as an etching stopper, the bottom of the wiring groove 87 does not reach the metal layer 85 and the second MTJ element 84.
[0975]
In this example, the wiring groove 87 is a groove for forming a write word line and extends in the X direction. A sidewall insulating layer (such as silicon nitride) 88 for a self-aligned contact process is formed on the side surface of the wiring groove 87.
[0976]
The wiring groove 87 can be easily formed by forming a resist pattern on the interlayer insulating film 86 by PEP, for example, and etching the interlayer insulating film 86 by RIE using this resist pattern as a mask. After this etching, the resist pattern is removed.
[0977]
The sidewall insulating layer 88 can be easily formed by forming an insulating film (such as silicon nitride) over the entire interlayer insulating film 86 by CVD and then etching the insulating film by RIE. it can.
[0978]
・ Step of forming the fourth wiring layer
Next, as shown in FIG. 198, for example, using a sputtering method, a barrier metal layer (a stack of Ta and TaN) is formed on the interlayer insulating film 86, the inner surface of the wiring groove 87, and the sidewall insulating layer 88. Etc.) 89 is formed. Subsequently, a metal layer (such as Cu) 90 that completely fills the wiring trench 87 is formed on the barrier metal layer 89 by, for example, sputtering.
[0979]
Thereafter, the metal layer 90 is polished using, for example, a CMP method, and the metal layer 90 is left only in the wiring groove 87. The metal layer 90 remaining in the wiring trench 87 becomes a fourth wiring layer that functions as a write word line.
[0980]
Further, an insulating layer (such as silicon nitride) 92 is formed on the interlayer insulating film 86 by a CVD method. Further, the insulating layer 92 is polished by CMP, and the insulating layer 92 is left only on the metal layer 90 as the fourth wiring layer. Further, an interlayer insulating film (such as silicon oxide) 93 that completely covers the metal layer 90 as the fourth wiring layer is formed on the interlayer insulating film 86.
[0981]
-Step of forming the lower electrode of the third MTJ element
Next, as shown in FIGS. 199 and 200, a metal layer 96 to be the lower electrode of the third MTJ element is formed on the interlayer insulating film 93 by the CVD method.
[0982]
Here, in the manufacturing method 3, compared with the manufacturing method 2, the step of forming a contact hole reaching the upper electrode 85 of the second MTJ element is omitted in order to connect the TMR elements stacked in four stages in series and parallel. is doing.
[0983]
-Step of forming the third MTJ element and its upper electrode
Next, as shown in FIGS. 201 and 202, the third MTJ element 97 is formed on the metal layer 96. The third MTJ element 97 includes a tunnel barrier, two ferromagnetic layers sandwiching the tunnel barrier, and an antiferromagnetic layer, and has a structure as shown in FIG. 47, for example.
[0984]
In this example, a protective insulating layer (such as silicon oxide) 97A that protects the third MTJ element 97 is formed on the side surface of the third MTJ element 97. The protective insulating layer 97A can be easily formed on the side surface of the third MTJ element 97 by using the CVD method and the RIE method.
[0985]
Thereafter, the lower electrode 96 of the third MTJ element 97 is patterned. The lower electrode 96 of the third MTJ element 97 can be easily patterned by forming a resist pattern on the lower electrode 96 by PEP and then etching the lower electrode 96 by RIE using the resist pattern as a mask. . Thereafter, the resist pattern is removed.
[0986]
Next, as shown in FIG. 203, an interlayer insulating film (such as silicon oxide) 98 that completely covers the third MTJ element 97 is formed by CVD. Further, for example, the interlayer insulating film 98 is polished by the CMP method, and the interlayer insulating film 98 is left only between the third MTJ elements 97.
[0987]
Thereafter, contact holes reaching the lower electrode 82 of the second MTJ element 84 are formed in the interlayer insulating films 86, 93, 98.
[0988]
This contact hole is easily formed by forming a resist pattern on the interlayer insulating film 98 by, for example, PEP, and etching the interlayer insulating films 86, 93, 98 by RIE using this resist pattern as a mask. be able to. After this etching, the resist pattern is removed.
[0989]
Next, as shown in FIG. 204, a barrier metal layer (such as a laminate of Ti and TiN) 99A is formed on the inner surface of the contact hole using, for example, sputtering. Subsequently, a metal layer (such as W) 99B that completely fills the contact hole is formed on the barrier metal layer 99A by, for example, sputtering.
[0990]
Thereafter, the metal layer 99B is polished by using, for example, a CMP method, and the metal layer 99B is left only in the contact hole. The metal layer 99B remaining in the contact hole becomes a contact plug. Further, a metal layer 99 to be the upper electrode of the third MTJ element is formed on the interlayer insulating film 98 by the CVD method.
[0991]
Also, an alumina layer 99C that protects the third MTJ element 97 is formed on the upper electrode 99 of the third MTJ element 97 by CVD.
[0992]
Next, as shown in FIG. 205, a resist pattern is formed by PEP, and the alumina layer 99C and the metal layer 99 are patterned using this resist pattern as a mask. After the alumina layer 99C is formed again, when the alumina layer 99C is etched by RIE, the alumina layer 99C remains in a form covering the metal layer 99 as the upper electrode and the upper part and the side wall part of the third MTJ element 97. .
[0993]
Thereafter, an interlayer insulating film 100 that completely covers the third MTJ element 97 is formed by CVD.
[0994]
・ Wiring groove formation step
Next, as shown in FIGS. 206 and 207, for example, a wiring groove extending in the Y direction is formed in the interlayer insulating film 100 by RIE using the resist pattern as a mask. At this time, since the alumina layer 99C functions as an etching stopper, the bottom of the wiring groove does not reach the metal layer 99 and the third MTJ element 97.
[0995]
In this example, the wiring groove is a groove for forming a write bit line and extends in the Y direction. A sidewall insulating layer (such as silicon nitride) for a self-aligned contact process is formed on the side surface of the wiring trench.
[0996]
The wiring trench can be easily formed, for example, by forming a resist pattern on the interlayer insulating film 100 by PEP, and etching the interlayer insulating film 100 by RIE using this resist pattern as a mask. After this etching, the resist pattern is removed.
[0997]
The sidewall insulating layer can be easily formed by forming an insulating film (such as silicon nitride) over the entire interlayer insulating film 100 by a CVD method and then etching the insulating film by RIE. .
[0998]
・ Fifth wiring layer formation step
Next, as shown in FIGS. 206 and 207, for example, sputtering is used to form barrier metal layers (Ta and TaN layers) on the interlayer insulating film 100, the inner surface of the wiring trench, and the sidewall insulating layer, respectively. 101) is formed. Subsequently, a metal layer (Cu or the like) 102 that completely fills the wiring groove is formed on the barrier metal layer 101 by, for example, sputtering.
[0999]
Thereafter, the metal layer 102 is polished by using, for example, a CMP method, and the metal layer 102 is left only in the wiring trench. The metal layer 102 remaining in the wiring trench becomes a fifth wiring layer functioning as a write bit line.
[1000]
Further, an insulating layer (such as silicon nitride) 103 is formed on the interlayer insulating film 100 by a CVD method. Further, this insulating layer 103 is polished by CMP, and this insulating layer 103 is left only on the metal layer 102 as the fifth wiring layer. Further, an interlayer insulating film (such as silicon oxide) 104 that completely covers the metal layer 102 as the fifth wiring layer is formed on the interlayer insulating film 100.
[1001]
-Step of forming the lower electrode of the fourth MTJ element
Next, as shown in FIGS. 208 and 209, contact holes reaching the upper electrode 99 of the third MTJ element 97 are formed in the interlayer insulating films 100 and 104 and the alumina layer 99C.
[1002]
This contact hole can be easily formed by forming a resist pattern on the interlayer insulating film 104 by PEP and etching the interlayer insulating films 100 and 104 and the alumina layer 99C by RIE using the resist pattern as a mask. Can be formed. After this etching, the resist pattern is removed.
[1003]
Further, for example, a barrier metal layer (such as a laminate of Ti and TiN) 80X is formed on the inner surface of the contact hole by sputtering. Subsequently, a metal layer (such as W) 81X that completely fills the contact hole is formed on the barrier metal layer 80X by sputtering, for example.
[1004]
Thereafter, the metal layer 81X is polished by using, for example, a CMP method, and the metal layer 81X is left only in the contact hole. The metal layer 81X remaining in the contact hole becomes a contact plug. Further, a metal layer 107 to be the lower electrode of the fourth MTJ element is formed on the interlayer insulating film 104 by sputtering.
[1005]
-Step of forming the fourth MTJ element and its upper electrode
Next, as shown in FIGS. 208 and 209, the fourth MTJ element 108 is formed on the metal layer 107. The fourth MTJ element 108 includes a tunnel barrier, two ferromagnetic layers sandwiching the tunnel barrier, and an antiferromagnetic layer, and has a structure as shown in FIG. 48, for example.
[1006]
In this example, a protective insulating layer (such as silicon oxide) 108A that protects the fourth MTJ element 108 is formed on the side surface of the fourth MTJ element 108. The protective insulating layer 108A can be easily formed on the side surface of the fourth MTJ element 108 by using the CVD method and the RIE method.
[1007]
Thereafter, the lower electrode 107 of the fourth MTJ element 108 is patterned. The patterning of the lower electrode 107 of the fourth MTJ element 108 can be easily performed by forming a resist pattern on the lower electrode 107 by PEP and then etching the lower electrode 107 by RIE using this resist pattern as a mask. . Thereafter, the resist pattern is removed.
[1008]
Next, as shown in FIG. 210, an alumina layer 108B that protects the fourth MTJ element 108 is formed on the fourth MTJ element 108 by CVD. Thereafter, the alumina layer 108B is etched by RIE, and as a result, the alumina layer 108B remains on the side wall portion of the fourth MTJ element 108.
[1009]
An interlayer insulating film (such as silicon oxide) 109 that completely covers the fourth MTJ element 108 is formed by CVD. Further, for example, the interlayer insulating film 109 is polished by the CMP method, and the interlayer insulating film 109 is left only between the fourth MTJ elements 108.
[1010]
Further, contact holes reaching the lower electrode 96 of the third MTJ element 97 are formed in the interlayer insulating films 100, 104, and 109.
[1011]
This contact hole is easily formed by forming a resist pattern on the interlayer insulating film 109 by, for example, PEP, and etching the interlayer insulating films 100, 104, and 109 by RIE using this resist pattern as a mask. be able to. After this etching, the resist pattern is removed.
[1012]
In this etching step, the etching rates of the alumina layers 99C and 108B are set to be sufficiently smaller than the etching rates of the interlayer insulating films 100, 104, and 109.
[1013]
That is, according to the present example, even if contact hole misalignment occurs, the alumina layers 99C and 108B protect the third and fourth MTJ elements 97 and 108, so that the third and fourth MTJ elements 97 and 108 are The situation of being etched does not occur.
[1014]
Next, as shown in FIG. 211, for example, a barrier metal layer (such as a laminate of Ti and TiN) 105 is formed on the inner surface of the contact hole by sputtering. Subsequently, a metal layer (such as W) 106 that completely fills the contact hole is formed on the barrier metal layer 105 by sputtering, for example.
[1015]
Thereafter, the metal layer 106 is polished by using, for example, a CMP method, and the metal layer 106 is left only in the contact hole. The metal layer 106 remaining in the contact hole becomes a contact plug. Further, a metal layer 107 to be the upper electrode of the fourth MTJ element 108 is formed on the interlayer insulating film 109 by sputtering. Subsequently, an alumina layer 107A that protects the fourth MTJ element 108 is formed on the metal layer 107 by a CVD method.
[1016]
Next, as shown in FIG. 212, a resist pattern is formed by PEP, and the alumina layer 107A and the metal layer 107 are patterned using the resist pattern as a mask.
[1017]
After the alumina layer 107A is formed again, when the alumina layer 107A is etched by RIE, the alumina layer 107A remains so as to cover the metal layer 107 as the upper electrode and the upper and side wall portions of the fourth MTJ element 108. .
[1018]
Thereafter, an interlayer insulating film 111 that completely covers the fourth MTJ element 108 is formed by CVD.
[1019]
・ Wiring groove formation step
Next, as shown in FIGS. 213 and 214, for example, a wiring trench 112 extending in the X direction is formed in the interlayer insulating film 111 by RIE using the resist pattern as a mask. At this time, since the alumina layer 107A functions as an etching stopper, the bottom of the wiring groove 112 does not reach the metal layer 107 and the fourth MTJ element 108.
[1020]
In this example, the wiring trench 112 is a trench for forming a write word line and extends in the X direction. Sidewall insulating layers (such as silicon nitride) 113 for a self-aligned contact process are formed on the side surfaces of the wiring trench 112.
[1021]
The wiring trench 112 can be easily formed, for example, by forming a resist pattern on the interlayer insulating film 111 by PEP, and etching the interlayer insulating film 111 by RIE using this resist pattern as a mask. After this etching, the resist pattern is removed.
[1022]
The sidewall insulating layer 113 can be easily formed by forming an insulating film (such as silicon nitride) over the entire interlayer insulating film 111 by CVD and then etching the insulating film by RIE. it can.
[1023]
・ Step of forming the sixth wiring layer
Next, as shown in FIGS. 213 and 214, for example, using a sputtering method, barrier metal layers (Ta and Ta) are formed on the interlayer insulating film 111, the inner surface of the wiring trench 112, and the sidewall insulating layer 113, respectively. (TaN stack or the like) 114 is formed. Subsequently, a metal layer (such as Cu) 115 that completely fills the wiring trench 112 is formed on the barrier metal layer 114 by sputtering, for example.
[1024]
Thereafter, the metal layer 115 is polished by using, for example, a CMP method, and the metal layer 115 is left only in the wiring groove 112. The metal layer 115 remaining in the wiring trench 112 becomes a sixth wiring layer that functions as a write word line.
[1025]
In addition, an insulating layer (such as silicon nitride) 116 is formed over the interlayer insulating film 111 by a CVD method. Further, the insulating layer 116 is polished by the CMP method, and the insulating layer 116 is left only on the metal layer 115 as the sixth wiring layer.
[1026]
・ Step of forming the seventh wiring layer
Next, as shown in FIGS. 215 and 216, an interlayer insulating film (such as silicon oxide) 117 that completely covers the metal layer 115 as the sixth wiring layer is formed on the interlayer insulating film 111. A contact hole reaching the upper electrode 107 of the fourth MTJ element is formed in the interlayer insulating films 111 and 117.
[1027]
The contact holes can be easily formed by forming a resist pattern on the interlayer insulating film 117 by, for example, PEP, and etching the interlayer insulating films 111 and 117 by RIE using the resist pattern as a mask. it can. After this etching, the resist pattern is removed.
[1028]
In addition, a wiring trench for forming a read bit line is formed in the interlayer insulating film 117.
[1029]
The wiring trench can be easily formed by forming a resist pattern on the interlayer insulating film 117 by PEP, for example, and etching the interlayer insulating film 117 by RIE using the resist pattern as a mask. After this etching, the resist pattern is removed.
[1030]
Thereafter, for example, a barrier metal layer (such as a laminate of Ti and TiN) 118 is formed on the interlayer insulating film 117, on the inner surface of the contact hole, and on the inner surface of the wiring groove by sputtering, for example. Subsequently, a metal layer (W or the like) 119 that completely fills the contact hole and the wiring groove is formed on the barrier metal layer 118 by sputtering, for example.
[1031]
Further, the metal layer 119 and the barrier metal layer 117 are polished by, for example, a CMP method, and the metal layer 119 and the barrier metal layer 117 are left only in the contact hole and the wiring groove. The metal layer 119 remaining in the contact hole becomes a contact plug. Also, the metal layer 119 remaining in the wiring trench becomes a seventh wiring layer that functions as a read bit line.
[1032]
▲ 3 ▼ Summary
According to this manufacturing method 3, a plurality of TMR elements are stacked in a plurality of stages, and the plurality of TMR elements are connected in series and parallel between a read bit line and a ground terminal (one switch-nMTJ structure). Can be realized.
[1033]
In this example, the damascene process and the dual damascene process are employed in forming the wiring layer. However, instead of this, for example, a process of processing the wiring layer by etching may be employed.
[1034]
9. Other
In the above description, it is assumed that a TMR element is used as the memory cell of the magnetic random access memory. However, even when the memory cell is a GMR (Giant Magneto Resistance) element, the present invention, that is, various cell array structures. Further, a read operation principle, a specific example of a read circuit, and the like can be applied.
[1035]
Further, the structure of the TMR element and the GMR element and the materials constituting them are not particularly limited in applying the present invention.
[1036]
As the read selection switch of the magnetic random access memory, the case of a MOS transistor, a bipolar transistor and a diode has been described. However, other switch elements such as a MIS (Metal Insulator Semiconductor) transistor (including a MOSFET), MES (Metal Semiconductor) ) Transistors and junction transistors can also be used as readout selection switches.
[1037]
【The invention's effect】
As described above, according to the present invention, first, it is possible to provide a magnetic random access memory having a novel cell array structure suitable for increasing the memory capacity and a method for manufacturing the same. Second, a novel read operation principle suitable for the novel cell array structure can be provided. Third, a read circuit for realizing the novel read operation principle can be realized.
[Brief description of the drawings]
FIG. 1 is a circuit diagram relating to Structural Example 1 of a magnetic random access memory according to the present invention.
FIG. 2 is a cross-sectional view related to Structural Example 1 of the magnetic random access memory of the present invention.
FIG. 3 is a cross-sectional view related to Structural Example 1 of the magnetic random access memory of the present invention.
4 is a circuit diagram showing a first modification of Structural Example 1. FIG.
FIG. 5 is a cross-sectional view showing a first modification of Structural Example 1;
6 is a circuit diagram showing a second modification of Structural Example 1. FIG.
7 is a cross-sectional view showing a second modification of Structural Example 1. FIG.
FIG. 8 is a circuit diagram relating to Structural Example 2 of the magnetic random access memory of the present invention.
FIG. 9 is a cross-sectional view related to Structural Example 2 of the magnetic random access memory of the present invention.
FIG. 10 is a cross-sectional view related to Structural Example 2 of the magnetic random access memory according to the present invention.
11 is a cross-sectional view showing a first modification of Structural Example 2. FIG.
12 is a plan view showing a first modification of Structural Example 2. FIG.
13 is a circuit diagram showing a second modification of Structural Example 2. FIG.
14 is a cross-sectional view showing a second modification of Structural Example 2. FIG.
15 is a circuit diagram showing a third modification of Structural Example 2. FIG.
16 is a cross-sectional view showing a third modification of Structural Example 2. FIG.
FIG. 17 is a circuit diagram relating to Structural Example 3 of the magnetic random access memory of the present invention.
18 is a cross-sectional view related to Structural Example 3 of the magnetic random access memory of the present invention. FIG.
FIG. 19 is a circuit diagram showing a first modification of Structural Example 3;
20 is a cross-sectional view showing a first modification of Structural Example 3. FIG.
FIG. 21 is a circuit diagram showing a second modification of Structural Example 3;
FIG. 22 is a cross-sectional view showing a second modification of Structural Example 3;
FIG. 23 is a circuit diagram relating to Structural Example 4 of the magnetic random access memory of the present invention.
FIG. 24 is a circuit diagram relating to Structural Example 4 of the magnetic random access memory of the present invention.
FIG. 25 is a circuit diagram relating to Structural Example 4 of the magnetic random access memory of the present invention.
FIG. 26 is a cross-sectional view related to Structural Example 4 of the magnetic random access memory of the present invention.
FIG. 27 is a cross-sectional view showing a modification of Structural Example 4;
FIG. 28 is a circuit diagram relating to Structural Example 5 of the magnetic random access memory of the present invention.
FIG. 29 is a circuit diagram relating to Structural Example 5 of the magnetic random access memory of the present invention.
FIG. 30 is a circuit diagram related to Structural Example 5 of the magnetic random access memory of the present invention.
FIG. 31 is a cross-sectional view related to Structural Example 5 of the magnetic random access memory of the present invention.
32 is a cross-sectional view showing a modified example of Structural Example 5. FIG.
33 is a diagram showing an equivalent circuit during a read operation in Structural Example 1. FIG.
34 is a diagram showing an equivalent circuit during a read operation in Structural Example 1. FIG.
FIG. 35 is a diagram showing an equivalent circuit during a read operation in Structural Example 1;
36 is a diagram showing an equivalent circuit during a read operation in Structural Example 2. FIG.
FIG. 37 is a diagram showing an equivalent circuit during a read operation in Structural Example 2;
38 is a diagram showing an equivalent circuit during a read operation in Structural Example 2. FIG.
FIG. 39 is a diagram showing an equivalent circuit during a read operation in Structural Example 3;
40 is a diagram showing an equivalent circuit during a read operation in Structural Example 3. FIG.
41 is a diagram showing an equivalent circuit during a read operation in Structural Example 3. FIG.
FIG. 42 is a diagram showing a structural example of a TMR element.
FIG. 43 is a diagram showing a structural example of a TMR element.
FIG. 44 is a diagram showing a structural example of a TMR element.
FIG. 45 is a view showing a structural example of a first TMR element.
FIG. 46 is a view showing a structural example of a second TMR element.
FIG. 47 is a diagram showing a structure example of a third TMR element.
FIG. 48 is a view showing a structural example of a fourth TMR element.
FIG. 49 is a view showing a structural example of a first TMR element.
FIG. 50 is a view showing a structural example of a second TMR element.
FIG. 51 is a view showing a structural example of a third TMR element.
FIG. 52 is a diagram showing a structure example of a fourth TMR element.
FIG. 53 is a diagram showing a circuit example 1 of a reading circuit according to the present invention.
54 is a diagram showing a circuit example 2 of a reading circuit according to the present invention. FIG.
FIG. 55 is a diagram showing a circuit example 3 of a reading circuit according to the present invention.
FIG. 56 is a diagram showing an example of a sense amplifier.
FIG. 57 is a diagram showing an example of a differential amplifier in a sense amplifier.
FIG. 58 is a diagram showing another example of the differential amplifier in the sense amplifier.
FIG. 59 is a diagram showing another example of a sense amplifier.
FIG 60 is a diagram showing an example of an operational amplifier in a reading circuit;
FIG. 61 illustrates another example of an operational amplifier in a reading circuit.
FIG. 62 is a circuit diagram showing an example of an additional current generator.
FIG. 63 is a diagram showing a circuit example 4 of a reading circuit according to the present invention.
FIG. 64 is a diagram showing a logic circuit for determining a data value of a fourth TMR element.
FIG. 65 is a diagram showing a logic circuit for determining a data value of a third TMR element.
FIG. 66 is a diagram showing a logic circuit for determining a data value of a second TMR element.
FIG. 67 is a diagram showing a logic circuit for determining the data value of the first TMR element.
FIG. 68 is a diagram showing a circuit example of a write word line driver / sinker;
FIG. 69 is a diagram showing a circuit example of a write bit line driver / sinker;
FIG. 70 is a diagram showing a circuit example of a read word line driver.
FIG. 71 is a diagram showing a circuit example of a column decoder.
FIG. 72 is a diagram showing a circuit example of a write word line driver / sinker;
FIG. 73 is a diagram showing a circuit example of a write bit line driver / sinker;
FIG. 74 is a diagram showing TMR elements arranged symmetrically with respect to a write line.
FIG. 75 is a diagram showing a TMR element arranged symmetrically with respect to a write line.
FIG. 76 is a diagram showing TMR elements arranged symmetrically with respect to a write line.
FIG. 77 is a diagram showing TMR elements arranged symmetrically with respect to a write line.
FIG. 78 is a diagram showing a TMR element arranged symmetrically with respect to a write line.
FIG. 79 is a diagram showing TMR elements arranged symmetrically with respect to a write line.
FIG. 80 is a diagram showing a circuit example of a write bit line driver / sinker;
FIG. 81 is a view showing a device structure to which the manufacturing method 1 of the present invention is applied;
FIG. 82 is a cross-sectional view showing one step of manufacturing method 1 of the present invention.
FIG. 83 is a cross-sectional view showing one step of manufacturing method 1 of the present invention.
FIG. 84 is a plan view showing one step in the production method 1 of the present invention.
85 is a cross-sectional view taken along line LXXXV-LXXXV in FIG. 84.
FIG. 86 is a cross-sectional view showing one step of manufacturing method 1 of the present invention.
87 is a cross-sectional view showing one step of the production method 1 of the present invention. FIG.
88 is a cross-sectional view showing one step of the production method 1 of the present invention. FIG.
FIG. 89 is a cross-sectional view showing one step of manufacturing method 1 of the present invention.
90 is a cross-sectional view showing one step of production method 1 of the present invention. FIG.
FIG. 91 is a cross-sectional view showing one step of manufacturing method 1 of the present invention.
FIG. 92 is a plan view showing one step in the production method 1 of the present invention.
93 is a sectional view taken along line XCIII-XCIII in FIG. 92. FIG.
FIG. 94 is a cross-sectional view showing one step of manufacturing method 1 of the present invention.
FIG. 95 is a plan view showing one step in the production method 1 of the present invention.
96 is a sectional view taken along line XCVI-XCVI in FIG. 95. FIG.
FIG. 97 is a cross-sectional view showing one step of manufacturing method 1 of the present invention.
FIG. 98 is a cross-sectional view showing one step of production method 1 of the present invention.
99 is a cross-sectional view showing one step of the production method 1 of the present invention. FIG.
FIG. 100 is a plan view showing one step in the production method 1 of the present invention.
101 is a sectional view taken along line CI-CI in FIG. 100. FIG.
102 is a cross-sectional view showing one step of the production method 1 of the present invention. FIG.
FIG. 103 is a plan view showing one step in the production method 1 of the present invention.
104 is a sectional view taken along line CIV-CIV in FIG. 103. FIG.
FIG. 105 is a cross-sectional view showing one step of manufacturing method 1 of the present invention.
FIG. 106 is a cross-sectional view showing one step of manufacturing method 1 of the present invention.
FIG. 107 is a cross-sectional view showing one step of the production method 1 of the present invention.
FIG. 108 is a plan view showing one step in the production method 1 of the present invention.
109 is a sectional view taken along line CIX-CIX in FIG. 108. FIG.
FIG. 110 is a cross-sectional view showing one step of manufacturing method 1 of the present invention.
FIG. 111 is a plan view showing one step in the production method 1 of the present invention.
112 is a sectional view taken along line CXII-CXII in FIG. 111. FIG.
FIG. 113 is a cross-sectional view showing one step of manufacturing method 1 of the present invention.
FIG. 114 is a cross-sectional view showing one step of manufacturing method 1 of the present invention.
FIG. 115 is a cross-sectional view showing one step of manufacturing method 1 of the present invention.
FIG. 116 is a plan view showing one step in the production method 1 of the present invention.
117 is a sectional view taken along line CXVII-CXVII in FIG. 116;
FIG. 118 is a cross-sectional view showing one step of manufacturing method 1 of the present invention.
119 is a plan view showing one step in the manufacturing method 1 of the present invention. FIG.
120 is a sectional view taken along line CXX-CXX in FIG. 119;
121 is a cross-sectional view showing one step of the production method 1 of the present invention. FIG.
122 is a cross-sectional view showing one step of the production method 1 of the present invention. FIG.
FIG. 123 is a plan view showing one step in the production method 1 of the present invention.
124 is a sectional view taken along line CXXIV-CXXIV in FIG. 123. FIG.
FIG. 125 is a plan view showing one step in the production method 1 of the present invention.
126 is a sectional view taken along line CXXVI-CXXVI in FIG. 125. FIG.
127 is a view showing a device structure to which the manufacturing method 2 of the present invention is applied; FIG.
128 is a cross-sectional view showing one step of manufacturing method 2 of the present invention. FIG.
FIG. 129 is a cross-sectional view showing one step of manufacturing method 2 of the present invention;
130 is a plan view showing one step in the production method 2 of the present invention. FIG.
131 is a sectional view taken along line CXXXI-CXXXI in FIG. 130;
132 is a cross-sectional view showing one step of the production method 2 of the present invention. FIG.
133 is a cross-sectional view showing one step of the production method 2 of the present invention. FIG.
FIG. 134 is a cross-sectional view showing one step of manufacturing method 2 of the present invention.
FIG. 135 is a cross-sectional view showing one step of manufacturing method 2 of the present invention.
136 is a cross-sectional view showing one step of the production method 2 of the present invention. FIG.
FIG. 137 is a cross-sectional view showing one step of manufacturing method 2 of the present invention.
138 is a plan view showing one step in manufacturing method 2 of the present invention. FIG.
139 is a cross-sectional view taken along line CXXXIX-CXXXIX in FIG. 138;
FIG. 140 is a plan view showing one step in the production method 2 of the present invention.
141 is a sectional view taken along line CXLI-CXLI in FIG. 140. FIG.
FIG. 142 is a cross-sectional view showing one step of manufacturing method 2 of the present invention.
143 is a cross-sectional view showing one step of manufacturing method 2 of the present invention; FIG.
144 is a cross-sectional view showing one step of manufacturing method 2 of the present invention; FIG.
145 is a plan view showing one step in the production method 2 of the present invention. FIG.
146 is a cross-sectional view taken along line CXLVI-CXLVI in FIG. 145;
147 is a plan view showing one step in the production method 2 of the present invention. FIG.
148 is a sectional view taken along line CXLVIII-CXLVIII in FIG. 147; FIG.
149 is a cross-sectional view showing one step of manufacturing method 2 of the present invention. FIG.
150 is a cross-sectional view showing one step of production method 2 of the present invention. FIG.
151 is a cross-sectional view showing one step of the production method 2 of the present invention. FIG.
FIG. 152 is a cross-sectional view showing one step of manufacturing method 2 of the present invention.
153 is a cross-sectional view showing one step of the production method 2 of the present invention. FIG.
FIG. 154 is a plan view showing one step in the production method 2 of the present invention.
155 is a cross-sectional view taken along line CLV-CLV in FIG. 154;
156 is a plan view showing one step in the production method 2 of the present invention. FIG.
157 is a cross-sectional view taken along the line CLVII-CLVII in FIG. 156. FIG.
FIG. 158 is a cross-sectional view showing one step of the manufacturing method 2 of the present invention.
159 is a cross-sectional view showing one step of the production method 2 of the present invention. FIG.
FIG. 160 is a cross-sectional view showing one step of the production method 2 of the present invention.
FIG. 161 is a plan view showing one step in the production method 2 of the present invention.
162 is a sectional view taken along the line CLXII-CLXII in FIG. 161. FIG.
FIG. 163 is a plan view showing one step in the production method 2 of the present invention.
164 is a cross-sectional view taken along the line CLXIV-CLXIV in FIG. 163;
165 is a cross-sectional view showing one step of manufacturing method 2 of the present invention. FIG.
166 is a sectional view showing one step in manufacturing method 2 of the present invention; FIG.
FIG. 167 is a cross-sectional view showing one step of the production method 2 of the present invention.
168 is a plan view showing one step in manufacturing method 2 of the present invention. FIG.
169 is a cross-sectional view taken along the line CLXIX-CLXIX in FIG. 168;
FIG. 170 is a plan view showing one step in the production method 2 of the present invention.
171 is a cross-sectional view taken along line CLXXVI-CLXXVI in FIG.
FIG. 172 is a view showing a device structure to which the manufacturing method 3 of the present invention is applied;
173 is a sectional view showing one step in manufacturing method 3 of the present invention; FIG.
174 is a cross-sectional view showing one step of manufacturing method 3 of the present invention; FIG.
175 is a plan view showing one step in manufacturing method 3 of the present invention. FIG.
176 is a cross-sectional view taken along the line CLXXVI-CLXXVI of FIG. 175;
177 is a cross-sectional view showing one step of manufacturing method 3 of the present invention. FIG.
178 is a cross-sectional view showing one step of manufacturing method 3 of the present invention. FIG.
179 is a cross-sectional view showing one step of manufacturing method 3 of the present invention. FIG.
FIG. 180 is a cross-sectional view showing one step of manufacturing method 3 of the present invention.
181 is a cross-sectional view showing one step of manufacturing method 3 of the present invention. FIG.
182 is a cross-sectional view showing one step of manufacturing method 3 of the present invention. FIG.
183 is a plan view showing one step in manufacturing method 3 of the present invention. FIG.
184 is a cross-sectional view taken along line CLXXXIV-CLXXXIV in FIG. 183. FIG.
185 is a plan view showing one step in manufacturing method 3 of the present invention. FIG.
186 is a cross-sectional view taken along line CLXXXVI-CLXXXVI in FIG. 185. FIG.
187 is a cross-sectional view showing one step of manufacturing method 3 of the present invention. FIG.
188 is a cross-sectional view showing one step of production method 3 of the present invention. FIG.
189 is a cross-sectional view showing one step of manufacturing method 3 of the present invention. FIG.
FIG. 190 is a plan view showing one step in the production method 3 of the present invention.
191 is a cross-sectional view taken along line CXCI-CXCI in FIG. 190;
FIG. 192 is a plan view showing one step in the production method 3 of the present invention.
193 is a cross-sectional view taken along line CXCIII-CXCIII in FIG.
194 is a cross-sectional view showing one step of production method 3 of the present invention. FIG.
FIG. 195 is a cross-sectional view showing one step of manufacturing method 3 of the present invention.
196 is a cross-sectional view showing one step of production method 3 of the present invention. FIG.
197 is a cross-sectional view showing one step of manufacturing method 3 of the present invention. FIG.
198 is a sectional view showing one step in manufacturing method 3 of the present invention. FIG.
199 is a plan view showing one step in manufacturing method 3 of the present invention. FIG.
200 is a sectional view taken along the line CC-CC in FIG. 199. FIG.
201 is a plan view showing one step in the production method 3 of the present invention. FIG.
202 is a sectional view taken along the line CCII-CCII in FIG. 201. FIG.
203 is a cross-sectional view showing one step of the production method 3 of the present invention. FIG.
204 is a cross-sectional view showing one step of production method 3 of the present invention. FIG.
205 is a cross-sectional view showing one step in the production method 3 of the present invention. FIG.
FIG. 206 is a plan view showing one step in the production method 3 of the present invention.
207 is a sectional view taken along the line CCVII-CCVII in FIG. 206. FIG.
FIG. 208 is a plan view showing one step in the production method 3 of the present invention.
209 is a sectional view taken along the CCIX-CCIX line in FIG. 208. FIG.
FIG. 210 is a cross-sectional view showing one step of manufacturing method 3 of the present invention.
FIG. 211 is a cross-sectional view showing one step of manufacturing method 3 of the present invention.
FIG. 212 is a cross-sectional view showing one step of production method 3 of the present invention.
213 is a plan view showing one step in the manufacturing method 3 of the present invention. FIG.
214 is a sectional view taken along the line CCXIV-CCXIV in FIG. 213. FIG.
FIG. 215 is a plan view showing one step in the production method 3 of the present invention.
216 is a sectional view taken along the line CCXVI-CCXVI in FIG. 215;
217 is a circuit diagram illustrating a structure example in which part of the structure example 1 is changed; FIG.
218 is a circuit diagram showing a structural example in which a part of structural example 1 is changed; FIG.
219 is a circuit diagram showing a structural example in which part of the structural example 2 is changed. FIG.
FIG. 220 is a circuit diagram showing a structural example in which a part of structural example 2 is changed.
221 is a circuit diagram showing a structural example in which a part of structural example 3 is changed; FIG.
FIG. 222 is a circuit diagram showing a structural example in which a part of structural example 3 is changed;
223 is a circuit diagram showing a structural example in which a part of structural example 4 is changed. FIG.
224 is a circuit diagram showing a structural example in which a part of structural example 4 is changed. FIG.
225 is a circuit diagram showing a structural example in which a part of structural example 4 is changed. FIG.
226 is a circuit diagram showing a structural example in which a part of structural example 5 is changed. FIG.
227 is a circuit diagram showing a structural example in which a part of structural example 5 is changed. FIG.
228 is a circuit diagram illustrating a structural example in which part of the structural example 5 is changed. FIG.
[Explanation of symbols]
11: memory cell array,
12: TMR element,
23A-0,... 23A-n: write word line driver,
24-0,..., 24-n: write word line sinker,
25-0,... 25-n: row decoder,
28: Common data line,
29: Write bit line driver / sinker,
29A: Write bit line driver / sinker,
29B: readout circuit,
30A, 30B: Common driver line,
31: Write bit line driver / sinker,
32: column decoder,
41, 51: semiconductor substrate,
41A1,... 41A4: lower electrode,
41B1,... 41B4: upper electrode,
42A,... 42F: contact plug,
43: middle layer,
44A, 44B, 47, 49, 50, 51X, 52X: contact part,
44-0,... 44-14: a reference current generation circuit,
52: element isolation insulating layer,
53: Gate insulating film,
54: a gate electrode,
55: Cap insulating film,
56A: source region,
56B: Drain region,
57, 65, 88: sidewall insulating layers,
58, 63, 69, 75, 75B, 79, 84B, 86, 93, 98, 100, 104, 109, 111, 117: interlayer insulating film,
59: contact hole,
60, 64, 75A, 87, 112: wiring grooves,
61, 66, 70, 76, 80, 85A, 89, 99A, 101, 114, 118: barrier metal layer,
62, 67, 71, 72, 74, 77, 81, 82, 85B, 90, 99B, 102, 115, 119: metal layer,
68, 78, 103: insulating layer,
73, 84, 97, 108: MTJ element,
74A, 83B, 85C: Alumina layer,
83A: protective insulating layer,
MTJ1,... MTJ4: TMR element (MTJ element),
BL00,... BLjn: block,
WWL0,... WWL3n + 2: write word line,
RWL0,... RWLn: Read word line,
BL00,... BLj0, BL01,... BLj1: Write bit line,
BL0,... BLj: Read bit line,
Px1, Px2, Px3, QPx, QP0,... QP21: P channel MOS transistor,
QN00, ... QN140, QN01, ... QN141, QN0, ... QN21: N-channel MOS transistor,
NR1,... NR17: NOR circuit,
AD1,... AD6: AND circuit,
ND1,... ND3: NAND circuit,
Ex-OR1: Exclusive OR circuit,
IV1,... IV20: inverter circuit,
DI0,... DI14: differential amplifier,
Mx: current mirror circuit,
Ix: current source,
SW, SWA, SWB: Column selection switch.

Claims (4)

A plurality of memory cells stacked on a semiconductor substrate and utilizing a magnetoresistive effect connected in series;
A read bit line disposed above all of the plurality of memory cells and connected to one end of the plurality of memory cells;
A read circuit connected to the read bit line;
A plurality of write word lines used to write data to one of the plurality of memory cells , extending in the X direction and stacked in a Z direction perpendicular to the X direction ;
A write bit line used to write data to one of the plurality of memory cells and extending in a Y direction that intersects the X direction and is perpendicular to the X direction and the Z direction ;
Each of the plurality of memory cells is sandwiched between an upper electrode and a lower electrode, and the plurality of memory cells are connected in series with each other by a contact plug that contacts the upper electrode or the lower electrode,
The write word line is disposed above or below the memory cell, and the write bit line is disposed below or above the memory cell opposite to the side on which the write word line is disposed. The magnetic random access memory, wherein the write word line and the write bit line arranged between the memory cells are shared by the memory cells arranged above and below the memory cell . A plurality of memory cells stacked on a semiconductor substrate and using a magnetoresistive effect constituted by a combination of series connection and parallel connection;
A read bit line disposed above all of the plurality of memory cells and connected to one end of the plurality of memory cells;
A read circuit connected to the read bit line;
A plurality of write word lines used to write data to one of the plurality of memory cells , extending in the X direction and stacked in a Z direction perpendicular to the X direction ;
A write bit line used to write data to one of the plurality of memory cells and extending in a Y direction that intersects the X direction and is perpendicular to the X direction and the Z direction ;
Each of the plurality of memory cells is sandwiched between an upper electrode and a lower electrode, and the plurality of memory cells are connected to each other by a combination of series connection and parallel connection by contact plugs that contact the upper electrode or the lower electrode. ,
The write word line is disposed above or below the memory cell, and the write bit line is disposed below or above the memory cell opposite to the side on which the write word line is disposed. The magnetic random access memory, wherein the write word line and the write bit line arranged between the memory cells are shared by the memory cells arranged above and below the memory cell . A plurality of memory cells stacked on a semiconductor substrate and utilizing a magnetoresistive effect connected in series;
A read bit line disposed above all of the plurality of memory cells and connected to one end of the plurality of memory cells;
A read circuit connected to the read bit line;
A plurality of write word lines used to write data to one of the plurality of memory cells, extending in the X direction and stacked in a Z direction perpendicular to the X direction;
A write bit line used to write data to one of the plurality of memory cells and extending in a Y direction that intersects the X direction and is perpendicular to the X direction and the Z direction;
Each of the plurality of memory cells is sandwiched between an upper electrode and a lower electrode, and the plurality of memory cells are connected in series with each other by a contact plug that contacts the upper electrode or the lower electrode,
The write word line is disposed above or below the memory cell, and the write bit line is disposed below or above the memory cell opposite to the side on which the write word line is disposed. In the method of manufacturing a magnetic random access memory, the write word line and the write bit line arranged between the memory cells are shared by the memory cells arranged above and below the memory cell.
Forming a read select switch in a surface region of said semiconductor substrate,
Forming a first write word line extending in the X direction and stacked in the Z direction on the read selection switch;
Forming a first memory cell immediately above the first write word line ;
Forming a first write bit line that intersects the X direction and extends in the Y direction immediately above the first memory cell ;
Forming the right above the first write bit line, a second memory cell to be the first memory cell is symmetrical with respect to the first write bit line,
Forming a second write word line directly above the second memory cell , extending in the X direction and stacked in the Z direction ;
Forming the right above the second write word line, a third memory cell to be the second memory cell and symmetrical with respect to the second write word line,
Forming a second write bit line that intersects the X direction and extends in the Y direction immediately above the third memory cell ;
Forming the right above the second write bit line, a fourth memory cell to be the third memory cell and symmetrical with respect to the second write bit line,
Forming a third write word line directly above the fourth memory cell , extending in the X direction and stacked in the Z direction ;
Forming a read bit line on the third write word line that intersects the X direction and extends in the Y direction . A plurality of memory cells stacked on a semiconductor substrate and using a magnetoresistive effect constituted by a combination of series connection and parallel connection;
A read bit line disposed above all of the plurality of memory cells and connected to one end of the plurality of memory cells;
A read circuit connected to the read bit line;
A plurality of write word lines used to write data to one of the plurality of memory cells, extending in the X direction and stacked in a Z direction perpendicular to the X direction;
A write bit line used to write data to one of the plurality of memory cells and extending in a Y direction that intersects the X direction and is perpendicular to the X direction and the Z direction;
Each of the plurality of memory cells is sandwiched between an upper electrode and a lower electrode, and the plurality of memory cells are connected to each other by a combination of series connection and parallel connection by contact plugs that contact the upper electrode or the lower electrode. ,
The write word line is disposed above or below the memory cell, and the write bit line is disposed below or above the memory cell opposite to the side on which the write word line is disposed. In the method of manufacturing a magnetic random access memory, the write word line and the write bit line arranged between the memory cells are shared by the memory cells arranged above and below the memory cell.
Forming a read select switch in a surface region of said semiconductor substrate,
Forming a first write word line extending in the X direction and stacked in the Z direction on the read selection switch;
Forming a first memory cell immediately above the first write word line ;
Forming a first write bit line that intersects the X direction and extends in the Y direction immediately above the first memory cell ;
Forming the right above the first write bit line, a second memory cell to be the first memory cell is symmetrical with respect to the first write bit line,
Forming a second write word line directly above the second memory cell , extending in the X direction and stacked in the Z direction ;
Forming the right above the second write word line, a third memory cell to be the second memory cell and symmetrical with respect to the second write word line,
Forming a second write bit line that intersects the X direction and extends in the Y direction immediately above the third memory cell ;
Forming the right above the second write bit line, a fourth memory cell to be the third memory cell and symmetrical with respect to the second write bit line,
Forming a third write word line directly above the fourth memory cell , extending in the X direction and stacked in the Z direction ;
Forming a read bit line on the third write word line that intersects the X direction and extends in the Y direction .

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