JP2008085349A - Magnetic random access memory - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To stack TMR (Tunneling Magneto Resistive) elements in multiple steps without increasing transistor density in the periphery of an array. <P>SOLUTION: A magnetic random access memory related to the present invention comprises a plurality of TMR arrays stacked in multiple steps, write lines arranged in the TMR arrays and extending from one end to other end of a first direction of the TMR arrays, contact plugs that commonly connects write lines in the TMR arrays at one end of the first direction, contact plugs that commonly connect the write lines in the TMR arrays at the other end of the first direction, wiring lines arranged in the TMR arrays and extending from one end to the other end in a second direction orthogonal to the first direction of the TMR arrays, and first selection transistors connected to one end of the wiring lines, wherein no selection transistor is individually connected to each TMR element in the plurality of TMR arrays. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a magnetic random access memory (MRAM) in which memory cells are configured using TMR elements that store “1”, “0” -information by a tunneling magnetoresistive effect. .

  In recent years, many memories for storing information based on a new principle have been proposed. One of them is a tunneling magnetoresistive (hereinafter referred to as TMR) proposed by Roy Scheuerlein et.al. ) There is a memory that uses the effect (for example, see ISSCC2000 Technical Digest p.128 “A 10ns Read and Write Non-Volatile Memory Array Using a Magnetic Tunnel Junction and FET Switch in each Cell”).

  The magnetic random access memory stores “1”, “0” -information by the TMR element. The TMR element has a structure in which an insulating layer (tunnel barrier) is sandwiched between two magnetic layers (ferromagnetic layers). Information stored in the TMR element is determined by whether the spin directions of the two magnetic layers are parallel or antiparallel.

  Here, “parallel” means that the spin directions of the two magnetic layers are the same, and “antiparallel” means that the spin directions of the two magnetic layers are opposite.

  Usually, one of the two magnetic layers constituting the TMR element is a fixed layer in which the spin direction is fixed. Therefore, when storing “1”, “0” -information in the TMR element, Depending on the write information, the spin direction of the other one (free layer) of these two magnetic layers may be changed.

  In recent years, MRAMs having various device structures or circuit structures have been proposed, and one of them is a device structure in which a plurality of TMR elements are connected to one switching element (select transistor). This structure is advantageous in increasing the cell density and improving the read margin.

  For example, Japanese Patent Application No. 2000-296082 (filed on Sep. 28, 2000) proposes a cell structure in which a plurality of TMR elements are connected in parallel between an upper wiring and a lower wiring. In this cell structure, as shown in FIG. 8, a plurality of TMR elements 10 are stacked on a substrate in a plurality of stages (in this example, four stages). In each stage, a plurality of TMR elements 10 are connected in parallel between the upper wiring 11 and the lower wiring 12.

  The upper wiring 11 extends in the X direction, and one end thereof is connected to the selection transistor 14. The lower wiring 12 also extends in the X direction, and one end thereof is connected to a peripheral circuit such as a sense amplifier (S / A) 15. In this example, the read current flows along the path of the upper wiring 11, the TMR element 10, and the lower wiring 12, that is, the X direction. The write wiring 13 is disposed adjacent to the TMR element 10 and extends in the Y direction.

  The cell structure in FIG. 9 is an example in which the lower wiring and the write wiring in FIG. 8 are integrated. That is, the lower wiring 12 extends in the Y direction, and one end thereof is connected to the sense amplifier (S / A). At the time of writing, the lower wiring 12 functions as a writing wiring. At the time of reading, the lower wiring 12 functions as a reading wiring. That is, the read current first flows to the upper wiring (X direction) 11, and then flows to the lower wiring (Y direction) 12 via the TMR element 10.

  The basic structure of the magnetic random access memory cell is a one-cell to one-transistor structure in which one switching element (selection transistor) is associated with one TMR element. However, in a device structure in which TMR elements are stacked in a plurality of stages, if one TMR element is associated with one switching element, the number of switching elements increases, which is disadvantageous for increasing the cell density.

  Therefore, in the case of a device structure in which the TMR elements 10 are stacked in a plurality of stages, a device structure that can perform a read operation and a write operation without using one switching element for each TMR element is employed. .

  For example, in the device structure shown in FIGS. 8 and 9, a plurality of TMR elements 10 are connected between the upper wiring 10 and the lower wiring 12 in each stage of the array of TMR elements 10. For example, the selection transistor 14 is connected to one end of the upper wiring 11, and the sense amplifier (S / A) 15 is connected to one end of the lower wiring 12.

  However, in this case, in the example of FIG. 8, a selection transistor is required for each of the upper wirings 11 arranged at each stage of the array of the TMR elements 10. Further, as shown in FIG. 10, the upper wiring 11 extends in the X direction on the array 16 of the TMR elements 10. That is, the selection transistors connected to the upper wiring 11 are concentrated on the area 17 at the end of the array 16.

  Similarly, a sense amplifier (transistor) is required for each lower wiring (readout wiring) 12 arranged in each stage of the array of TMR elements 10. That is, as shown in FIG. 10, since the lower wiring 12 extends in the X direction on the array 16 of the TMR elements 10, the transistors connected to the lower wiring 12 are concentrated in the area 18 at the end of the array 16. Will be placed.

  Similarly, a selection transistor is required for each of the write wirings 13 arranged at each stage of the array of TMR elements 10. That is, as shown in FIG. 10, since the write wiring 13 extends in the Y direction on the array 16 of the TMR elements 10, the selection transistor connected to the write wiring 13 has an area 19A, It will be concentrated on 19B.

  Incidentally, it is known that a large current is required in the data write / read operation for the TMR element due to the characteristics of the TMR element. For this reason, it is expected that the size of the transistors connected to the upper wiring 11, the lower wiring 12, and the writing wiring 13 is necessarily increased.

Accordingly, the areas 17, 18, 19A, and 19B in which the transistors for current drive arranged around the array 16 are arranged are also increased, and it is impossible to reduce the chip size and the manufacturing cost per chip. . In addition, since the number of selection transistors increases in proportion to the number of stages where the TMR elements are stacked, if the number of stacked stages of the TMR elements is very large, the layout of the selection transistors requires a lot of time and the development time becomes long.
JP 2001-236781 A JP 2000-187976 A Japanese Patent Laid-Open No. 10-106255

  An object of the present invention is to propose a novel device structure that can be connected to wiring in an array of TMR elements and can reduce the number of transistors disposed at the end of the array of TMR elements. The purpose is to reduce the manufacturing cost per chip and shorten the development time.

  A magnetic random access memory according to an example of the present invention includes a plurality of TMR arrays stacked in a plurality of stages, a write line disposed in the TMR array and extending from one end to the other end in the first direction of the TMR array, A contact plug for commonly connecting a write line in the TMR array at one end in the first direction; a contact plug for commonly connecting a write line in the TMR array at the other end in the first direction; and the TMR array. A plurality of the TMR arrays including a wiring extending from one end to the other end in a second direction orthogonal to the first direction of the TMR array, and a first selection transistor connected to one end of the wiring. The select transistors are not individually connected to the TMR elements.

  According to the present invention, by proposing a novel device structure capable of reducing the number of transistors connected to the wiring in the array of TMR elements and arranged at the end of the array of TMR elements, It is possible to reduce the manufacturing cost per chip and shorten the development time.

  Hereinafter, the magnetic random access memory of the present invention will be described in detail with reference to the drawings.

  The present invention is applied to a magnetic random access memory having an array structure in which TMR elements are stacked in a plurality of stages.

  In the magnetic random access memory of the present invention, wirings having the same function (for example, writing wirings, reading wirings, etc.) arranged in each stage in one row or one column of the array of TMR elements are connected in series or in parallel. Characterized by points. In this case, since it is only necessary to arrange one transistor at one end or one transistor at each end of the wiring, the number of transistors arranged at the end of the array of TMR elements can be reduced. .

  In addition, according to the device structure of the present invention, the transistor may be connected to the wiring connected in series or in parallel in one row or one column of the array of TMR elements regardless of the number of stacked TMR elements. Even if the number of stacked elements is increased to increase the memory capacity, the number of transistors does not increase and the layout thereof does not become complicated.

  Further, since the number of transistors connected to the wiring having the same function arranged at each stage in one row or one column of the TMR element array is always constant, the TMR element array is made into one small block, and a plurality of blocks A large memory cell array may be configured by collecting the above. In this case, a core circuit such as a transistor or a sense amplifier can be disposed immediately below the array of TMR elements.

[First Embodiment]
FIG. 1 shows an outline of the layout of the cell array portion of the magnetic random access memory according to the first embodiment of the present invention. FIG. 2 shows a cross section along the X direction of the cell array portion of FIG. 1, that is, a cross section taken along the line II-II of FIG.

  A plurality of TMR elements 10 are stacked in a plurality of stages (in this example, three stages) on the semiconductor substrate. In each stage, the TMR elements 10 form an array in the XY plane.

  Both the upper wiring 11 and the lower wiring 12 extend in the X direction, and a plurality of TMR elements 10 arranged in the X direction are disposed between the wirings 11 and 12. A selection transistor 14 is connected to one end of the upper wiring 11. A peripheral circuit such as a sense amplifier (S / A) 15 is connected to one end of the lower wiring 12.

  In the present embodiment, the upper wiring 11 and the lower wiring 12 function as readout wiring. That is, when reading data, the read current flows along the path of the upper wiring 11, the TMR element 10, and the lower wiring 12, that is, the X direction.

  As a specific reading method, first, a read current is supplied to the upper wiring 11 and the lower wiring 12, and for example, the potential of the lower wiring 12 at this time is detected by a sense amplifier. Next, predetermined data (“0” or “1”) is written to the selected TMR element (memory cell), and thereafter, a read current is supplied to the upper wiring 11 and the lower wiring 12 again. 12 potentials are detected by a sense amplifier. If the potential detected by the sense amplifier is the same in the first read and the second read, the data of the selected TMR element is determined to be the same as the predetermined data, and if different, the data of the selected TMR element is It is judged that it is different from the predetermined data. Finally, correct data is rewritten to the selected TMR element.

  The write wiring 13 is disposed on the TMR element 10 in each stage of the array of the TMR elements 10 and extends in the Y direction. Further, the write wiring 13 is disposed in the vicinity of the free layer of the TMR element 10. Further, in this example, when a group of a plurality of TMR elements arranged in the X direction is one column and a group of a plurality of TMR elements arranged in the Y direction is one row, in this example, the array of TMR elements 10 is In one row, write wirings 13 arranged in each stage are connected in series.

  That is, as shown in FIG. 3, at the end of the array of the TMR elements 10, the upper write wiring 13 and the lower write wiring 13 are electrically connected to each other through the contact plug. In FIG. 3, the upper wiring and the lower wiring are omitted for simplification.

  As a specific writing method, for example, a write current flowing in one direction or the other direction is caused to flow through the lower wiring 12 in one selected column functioning as a writing wiring in accordance with the value of writing data. At the same time, a write current flowing in one direction is supplied to the write wiring 13 in one selected row. As a result, predetermined data is written into the TMR element (memory cell) 10 disposed between the lower wiring 12 and the write wiring 13.

  As described above, in this embodiment, by connecting the wirings having the same function, that is, the writing wirings arranged in each stage in one row of the array of the TMR elements 10 in series, As shown in FIG. 3, one transistor may be arranged at both ends thereof. For this reason, the number of transistors arranged in the end areas 19A and 19B of the array 16 of the TMR elements 10 can be greatly reduced.

  In addition, according to such a device structure, a transistor may be connected to a wiring connected in series within one row of the array 16 of the TMR elements 10 regardless of the number of stacked stages of the TMR elements 10. Even if the number of stacked stages is increased to increase the memory capacity, the number of transistors is not increased and the layout is not complicated.

  Furthermore, since the number of transistors connected to the write wiring 13 arranged in each stage in one row of the array 16 of the TMR element 10 is always constant, the array 16 of the TMR element 10 is made into one small block, and a plurality of blocks are arranged. A large memory cell array may be configured by collecting them. In this case, for example, as shown in FIG. 3, a core circuit such as a transistor or a sense amplifier can be disposed immediately below the TMR element 10 in each block.

  In FIG. 1, the stacked TMR elements, the wiring extending in the X direction, and the wiring extending in the Y direction are described so as to be shifted from each other in each stage, but this makes the explanation easy to understand. Actually, they may be shifted from each other or completely overlapped.

[Second Embodiment]
FIG. 4 shows an outline of the cell array portion of the magnetic random access memory according to the second embodiment of the present invention.

  The magnetic random access memory according to the present embodiment is characterized in that the number of stacking stages of the TMR element 10 in FIG. 2 is four compared to the magnetic random access memory in FIG. This is the same as the magnetic random access memory 2.

  A plurality of TMR elements 10 are stacked in a plurality of stages (in this example, four stages) on the semiconductor substrate. In each stage, the TMR elements 10 form an array in the XY plane.

  Both the upper wiring 11 and the lower wiring 12 extend in the X direction, and a plurality of TMR elements 10 arranged in the X direction are disposed between the wirings 11 and 12. A selection transistor 14 is connected to one end of the upper wiring 11. A peripheral circuit such as a sense amplifier (S / A) 15 is connected to one end of the lower wiring 12.

  The upper wiring 11 and the lower wiring 12 function as readout wiring. That is, when reading data, the read current flows along the path of the upper wiring 11, the TMR element 10, and the lower wiring 12, that is, the X direction.

  The write wiring 13 is disposed on the TMR element 10 in each stage of the array of the TMR elements 10 and extends in the Y direction. Further, the write wiring 13 is disposed in the vicinity of the free layer of the TMR element 10. Further, in this example, when a group of a plurality of TMR elements arranged in the X direction is one column and a group of a plurality of TMR elements arranged in the Y direction is one row, in this example, the array of TMR elements 10 is In one row, write wirings 13 arranged in each stage are connected in series.

  That is, as shown in FIG. 5, at the end of the array of TMR elements 10, the upper write wiring 13 and the lower write wiring 13 are electrically connected to each other through the contact plug. In FIG. 5, the upper wiring and the lower wiring are omitted for simplification.

  In the present embodiment, the number of stacking stages of the TMR element 10 is four. That is, when the number of stacked stages of the TMR element 10 is an even number (2, 4, 6,...), Two contacts for connecting the write wiring 13 and the transistor as shown in FIG. Both parts are disposed at one end of the array part of the TMR element 10.

  In this case, for example, as shown in FIG. 5, a transistor connected to one end of the write wiring 13 in the block BK0 is arranged immediately below the array of the block BK1 adjacent to the block BK0, and the write in the block BK0 is performed. A transistor connected to the other end of the wiring 13 is arranged immediately below the array of the block BK0.

  If the number of stacked stages of the TMR elements 10 is an odd number (3, 5, 7,...) As in the first embodiment, the write wiring 13 is shown in FIG. A contact portion for connecting one end of the transistor and the transistor is disposed at one end portion of the array portion of the TMR element 10, and a contact portion for connecting the other end of the write wiring 13 and the transistor is the array portion of the TMR element 10. It arrange | positions at the other end part which opposes the one end part of a part.

  Therefore, in this case, for example, as shown in FIG. 3, the transistors connected to one end and the other end of the write wiring 13 in the block BK0 are respectively arranged immediately below the array of the block BK0.

  As described above, in this embodiment, by connecting the wirings having the same function, that is, the writing wirings arranged in each stage in one row of the array of the TMR elements 10 in series, As shown in FIG. 5, one transistor may be arranged at both ends thereof. Therefore, the number of transistors arranged at the end of the array of TMR elements 10 can be greatly reduced.

  In addition, according to such a device structure, the transistors may be connected to the wirings connected in series in one row of the array of TMR elements 10 regardless of the number of stacked TMR elements. Even if the number of stages is increased to increase the memory capacity, the number of transistors does not increase and the layout is not complicated.

  Furthermore, since the number of transistors connected to the write wiring 13 arranged in each stage in one row of the array of TMR elements 10 is always constant, the array of TMR elements 10 is made into one small block, and a plurality of blocks are collected. A large memory cell array may be configured. In this case, for example, as shown in FIG. 5, a core circuit such as a transistor or a sense amplifier can be disposed immediately below the TMR element 10 in each block.

[Third Embodiment]
FIG. 6 shows an outline of the cell array portion of the magnetic random access memory according to the third embodiment of the present invention.

  Compared with the magnetic random access memory of FIG. 4, the magnetic random access memory of this embodiment is characterized in that the magnetization direction of the fixed layer of the TMR element 10 of FIG. This point is the same as the magnetic random access memory of FIG.

  A plurality of TMR elements 10 are stacked in a plurality of stages (in this example, four stages) on the semiconductor substrate. In each stage, the TMR elements 10 form an array in the XY plane.

  Both the upper wiring 11 and the lower wiring 12 extend in the X direction, and a plurality of TMR elements 10 arranged in the X direction are disposed between the wirings 11 and 12. A selection transistor 14 is connected to one end of the upper wiring 11. A peripheral circuit such as a sense amplifier (S / A) 15 is connected to one end of the lower wiring 12.

  The upper wiring 11 and the lower wiring 12 function as readout wiring. That is, when reading data, the read current flows along the path of the upper wiring 11, the TMR element 10, and the lower wiring 12, that is, the X direction.

  The write wiring 13 is disposed on the TMR element 10 in each stage of the array of the TMR elements 10 and extends in the Y direction. Further, the write wiring 13 is disposed in the vicinity of the free layer of the TMR element 10. Further, in this example, when a group of a plurality of TMR elements arranged in the X direction is one column and a group of a plurality of TMR elements arranged in the Y direction is one row, in this example, the array of TMR elements 10 is In one row, write wirings 13 arranged in each stage are connected in series.

  That is, as shown in FIG. 5, at the end of the array of TMR elements 10, the upper write wiring 13 and the lower write wiring 13 are electrically connected to each other through the contact plug.

  Incidentally, in the second embodiment described above, the write wirings 13 meander in the YZ plane, as is apparent from FIG. In this case, as shown in FIG. 6, when a current in one direction flows through the write wiring 13, the direction of the current flowing through the write wiring 13 is opposite to each other in each stage.

  In the case of FIG. 6, a write current flows from the front to the back of the page through the odd-numbered write wirings 13, that is, the first-stage write wiring 13 and the third-stage write wiring 13 closest to the semiconductor substrate. In the even-numbered write wiring 13, that is, the second and fourth write wirings 13, a write current flows from the back of the paper surface to the front.

  In such a situation, for example, if the magnetization directions of the fixed layers of all the TMR elements 10 are the same, for example, when the same data is written to the odd-numbered TMR elements and the even-numbered TMR elements. In this case, a write current having a different direction must be supplied to the write wiring 13.

  That is, when the magnetization directions of the fixed layers of all the TMR elements 10 are the same and the direction of the write current of the lower wiring 12 is constant, if only one direction of the write current is passed through the write wiring 13, each stage The magnetization direction of the free layer of the TMR element 10 is reversed every stage. In other words, the magnetization state of each stage of the TMR element 10 is parallel and anti-parallel for each stage, and different data is written to the TMR element 10 of each stage despite the same operation.

  As described above, in the second embodiment, when a current in one direction is supplied to the write wiring 13, the currents flowing in the write wiring 13 are opposite to each other in each stage. The control method may be complicated.

  Therefore, in this embodiment, in order to solve such a situation, it is proposed to change the magnetization direction of the fixed layer of the TMR element 10 for each stage as shown in FIG. In this case, if only a write current in one direction is passed through the write wiring 13, the direction of magnetization of the free layer of the TMR element 10 at each stage is reversed for each stage, but the magnetization of the TMR element 10 at each stage is reversed. The state is the same (parallel or antiparallel) at each stage. That is, the same data is written to the TMR elements 10 at each stage.

  The magnetization direction of the fixed layer of the TMR element 10 can be easily changed for each stage by a conventional process. That is, in order to change the magnetization direction of the fixed layer of the TMR element 10 step by step, the direction of the magnetic field may be adjusted when depositing the material constituting the fixed layer.

  In this embodiment, the problem caused by the meandering of the write wiring 13 is solved by changing the magnetization direction of the fixed layer of the TMR element 10 for each stage. There is a solution.

  For example, although write control is complicated, as described above, it is possible to pass a current in a different direction through the write wiring 13 or to change the direction of the write current through the lower wiring 12. In addition, the same data may be stored in different magnetization states at each stage, and the data determination condition may be changed for each stage.

  Thus, in this embodiment, the magnetization direction of the fixed layer of the TMR element is changed for each stage. In this case, when only a write current in one direction is passed through the write wiring, the magnetization direction of the free layer of each stage of the TMR element is reversed in each stage, but the magnetization state of each stage of the TMR element is It is the same (parallel or antiparallel) at each stage.

  Therefore, according to the present embodiment, the same effect as the magnetic random access memory of the second embodiment described above can be obtained, and the control method of the write operation is not complicated.

[Fourth embodiment]
FIG. 7 shows an outline of a cell array portion of a magnetic random access memory according to the fourth embodiment of the present invention. In FIG. 7, the upper wiring and the lower wiring connected to the TMR element are omitted for simplification.

  Compared with the magnetic random access memory of FIG. 4, the magnetic random access memory of the present embodiment is different from the magnetic random access memory of FIG. 4 in that the write wirings 13 arranged in each stage of the TMR element 10 of FIG. The other features are the same as those of the magnetic random access memory of FIG.

  A plurality of TMR elements 10 are stacked in a plurality of stages (in this example, four stages) on the semiconductor substrate. In each stage, the TMR elements 10 form an array in the XY plane.

  Also in this embodiment, as shown in FIG. 4, the upper wiring 11 and the lower wiring 12 both extend in the X direction, and a plurality of TMR elements arranged in the X direction between both the wirings 11 and 12. 10 is arranged. A selection transistor 14 is connected to one end of the upper wiring 11. A peripheral circuit such as a sense amplifier (S / A) 15 is connected to one end of the lower wiring 12.

  As shown in FIG. 7, the write wiring 13 is disposed on the TMR element 10 in each stage of the array of the TMR elements 10 and extends in the Y direction. Further, the write wiring 13 is disposed in the vicinity of the free layer of the TMR element 10. Further, in this example, when a group of a plurality of TMR elements arranged in the X direction is one column and a group of a plurality of TMR elements arranged in the Y direction is one row, in this example, the array of TMR elements 10 is In one row, write wirings 13 arranged in each stage are connected in parallel.

  That is, at the end of the array of the TMR elements 10, the upper write wiring 13 and the lower write wiring 13 are electrically connected to each other through the contact plug.

  Incidentally, in the second embodiment described above, the write wirings 13 at each stage are connected in series with each other. Therefore, as is apparent from FIG. 5, the write wirings 13 meander in the YZ plane. The On the other hand, in the present embodiment, the write wirings 13 at the respective stages are connected in parallel to each other. Therefore, as apparent from FIG. 7, the write wiring 13 has a ladder shape in the YZ plane.

  In the present embodiment, when a current in one direction flows through the write wiring 13, unlike the second embodiment, the directions of the current flowing through the write wiring 13 are the same in each stage.

  Therefore, according to the present embodiment, the same effect as the magnetic random access memory of the second embodiment described above can be obtained, and the magnetization of the fixed layer of the TMR element can be obtained as in the third embodiment described above. The writing operation can be easily controlled without taking a measure of changing the direction for each stage.

  In the present embodiment, since the write wirings at each stage are connected in parallel, the write wiring and the contact portion of the transistor are provided one each at two opposite ends of the array of TMR elements. For this reason, the array of TMR elements may be made into one small block, and a large memory cell array may be configured by collecting a plurality of blocks. In this case, a core circuit such as a transistor or a sense amplifier can be easily arranged immediately below the TMR element in each block.

[Others]
In the first to fourth embodiments described above, in the array structure in which the TMR elements are stacked in a plurality of stages, the write wirings (write-only wirings) arranged in each stage in one row are connected in series or in parallel. As described above, the present invention can be applied to wiring arranged in an array of TMR elements other than the write wiring. For example, the present invention can be applied to the upper wiring 11 and the lower wiring 12 shown in FIG. 8 and the upper wiring 11 and the lower wiring 12 shown in FIG.

  In the first to fourth embodiments described above, the wiring arranged in each stage of the TMR elements stacked in a plurality of stages has been described as an example. For example, the wiring is shared between the upper and lower TMR elements. In such a case, wirings having the same function are not arranged in each stage but arranged every other stage. Even in such a case, the present invention can be configured by connecting wirings arranged every other stage in series or in parallel.

  Furthermore, in the first to fourth embodiments described above, the transistor connected to the wiring in the array of TMR elements is generally a MOS transistor, but may be a bipolar transistor or a diode.

  The present invention can be applied to any structure as long as the magnetic random access memory has a cell array structure in which TMR elements are stacked in a plurality of stages.

  As described above, according to the magnetic random access memory of the present invention, in an array structure in which TMR elements are stacked in a plurality of stages, wirings having the same function arranged in each stage are connected in series or in parallel. Therefore, it is only necessary to arrange one transistor at one end or one transistor at each end of the wiring, and the number of transistors arranged at the end of the array of TMR elements can be reduced.

  Regardless of the number of stacked TMR elements, the transistors may be connected to wirings connected in series or in parallel in one row or one column of the array of TMR elements. Therefore, even if the number of stacked TMR elements is increased to increase the memory capacity, the number of transistors does not increase and the layout thereof does not become complicated.

  Furthermore, since the number of transistors connected to the wiring having the same function arranged in each stage of the TMR element array is constant, the TMR element array is made into one small block, and a large memory cell array is formed by collecting a plurality of blocks. May be. In this case, a core circuit such as a transistor or a sense amplifier can be disposed immediately below the array of TMR elements.

The top view which shows the principal part of the memory in connection with 1st Embodiment of this invention. FIG. 2 is a diagram showing a cross section in the X direction of the memory of FIG. 1. FIG. 2 is a diagram showing a cross section in the Y direction of the memory of FIG. The figure which shows the cross section of the X direction of the memory in connection with 2nd Embodiment of this invention. FIG. 5 is a diagram showing a cross section in the Y direction of the memory of FIG. The figure which shows the cross section of the X direction of the memory in connection with 3rd Embodiment of this invention. The figure which shows the cross section of the Y direction of the memory in connection with 4th Embodiment of this invention. The figure which shows the cell structure of the conventional memory. The figure which shows the cell structure of the conventional memory. The figure which shows the cell structure of the conventional memory.

Explanation of symbols

  10: TMR element, 11: upper wiring, 12: lower wiring, 13: write wiring, 14: switching element, 15: sense amplifier, 16: array of TMR elements, 17, 18, 19A, 19B: array of TMR elements Edge area.

Claims (4)

  A plurality of TMR arrays stacked in a plurality of stages, a write line disposed in the TMR array and extending from one end to the other end in the first direction of the TMR array, and one end in the first direction in the TMR array A contact plug for commonly connecting a write line; a contact plug for commonly connecting a write line in the TMR array at the other end in the first direction; and the first plug of the TMR array. A wiring extending from one end to the other end in a second direction orthogonal to the direction, and a first selection transistor connected to one end of the wiring, and each of the TMR elements in the plurality of TMR arrays has a selection transistor individually. Magnetic random access memory characterized in that it is not connected.   2. The write line in the TMR array is connected to a second selection transistor on one end side in the first direction and connected to a third selection transistor on the other end side in the first direction. Magnetic random access memory according to 1.   3. The magnetic random access memory according to claim 1, wherein the magnetization direction of the fixed layer of the TMR element is the same in all of the plurality of TMR arrays.   4. The apparatus according to claim 1, further comprising a plurality of blocks each having a plurality of the TMR arrays and the write lines, wherein the plurality of blocks are arranged adjacent to each other in the first direction. The magnetic random access memory according to claim 1.

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