JP4140169B2 - Non-contact power transmission device - Google Patents

Non-contact power transmission device Download PDF

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Publication number
JP4140169B2
JP4140169B2 JP2000124565A JP2000124565A JP4140169B2 JP 4140169 B2 JP4140169 B2 JP 4140169B2 JP 2000124565 A JP2000124565 A JP 2000124565A JP 2000124565 A JP2000124565 A JP 2000124565A JP 4140169 B2 JP4140169 B2 JP 4140169B2
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Japan
Prior art keywords
element
drive signal
synchronous rectification
current
rectification
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JP2001309580A (en
Inventor
秀明 安倍
元治 武藤
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松下電工株式会社
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Description

[0001]
BACKGROUND OF THE INVENTION
  The present invention relates to a non-contact power transmission device.
[0002]
[Prior art]
  Examples that have been put into practical use by applying non-contact power technology are charging applications such as shavers and electric toothbrushes, and are limited to low outputs of about several watts. A diode rectification method has been used as a rectification method for the secondary circuit.
[0003]
[Problems to be solved by the invention]
  Non-contact / contactless power transmission technology using magnetic induction with a separate detachable transformer can take a fundamental measure of electric shock due to its feature of no metal contact, so its use as a power source around water is drawing attention. . In order to use it as a safe and reliable power supply, the output voltage is low and the efficiency of the equipment does not decrease. The power supply of about 12V, which has already been proven in automobiles, and more than 50W can be used. Higher output is required. However, as the output is increased at a lower voltage, the output current increases, and the diode rectification method used in the secondary side circuit of the conventional contactless power supply device increases the rectification loss and increases the size of the heat sink such as a diode. As a result, there was a problem that it could not fit in a practical size.
[0004]
  Therefore, the application of the synchronous rectification technique, which has been conventionally used for reducing the loss of the rectification unit of the switching power supply whose output voltage is 5 V or less, to the non-contact power transmission device was examined. Synchronous rectification technology uses FET switching elements and FET parasitic diodes as switching elements for synchronous rectification, switches the FET switching elements according to the rectification cycle, and allows the rectified current to flow through the FET switching elements. In this technique, the loss of the rectification unit is reduced by utilizing the low on-resistance of the FET. Of course, the same operation is performed even if a diode in the reverse direction is connected in parallel to the switching element instead of the FET incorporating the parasitic diode.
[0005]
  The non-contact power transmission device outputs power received from a power source that supplies DC power, an inverter that converts DC power to high frequency power, a primary coil that is supplied with high frequency power from the inverter, and a primary coil Primary circuit composed of a primary coil of a separate detachable transformer that can be separated from the secondary coil to be separated, a secondary coil, a load matching capacitor connected in parallel to the secondary coil, and a secondary coil And a secondary side circuit composed of a rectifying unit for rectifying the output voltage of the output. At this time, in order to maximize the effective power that can be extracted to the secondary side to increase the efficiency of the entire circuit and to reduce the size of the separation / removable transformer, the leakage magnetic flux between the primary coil and the secondary coil of the separation / removable transformer The power factor of the entire circuit is improved by the leakage inductance caused by the above and the load matching capacitor connected in parallel to the secondary coil.
[0006]
  However, when load matching is performed by the load matching capacitor, the output waveform of the secondary coil is different from the output waveform of the secondary coil of the switching power supply and becomes a sine wave shape or a more distorted waveform. In the conventional drive signal generation method for the synchronous rectification switching element using the voltage or the auxiliary winding, since the on-time of the synchronous rectification switching element is short, the rectification efficiency is poor, and the efficiency cannot be increased as compared with the diode rectification method.
[0007]
  This invention is made | formed in view of the said reason, The objective is to provide the non-contact electric power transmission apparatus which raised the rectification efficiency of the secondary side circuit.
[0008]
[Means for Solving the Problems]
  The invention according to claim 1 is a power supply section that supplies a DC power supply, an inverter section that converts the DC power supply to a high-frequency power supply, a primary coil that is supplied with high-frequency power from the inverter section, and power that is received from the primary coil A secondary side circuit configured to be separable from the primary coil of the transformer, the secondary coil, a load matching capacitor connected in parallel to the secondary coil, and the Non-contact power having a secondary side circuit composed of a rectifying unit that rectifies the output voltage of the secondary coilTransmissionIn the deviceThe secondary coil of the transformer includes a center tap, and includes first and second synchronous rectification elements including a switching element and a diode reversely connected in parallel to the switching element, and the secondary coil of the transformer Full-wave rectification by connecting each other end not connected to the secondary coil of the transformer of the first and second synchronous rectification elements connected in series and in opposite directions to both output ends which are not center taps The current flowing through the first synchronous rectification element that has been conducted earlier and has finished rectification, and the rectification section that constitutes a section, a current detection section that detects a current flowing through the first and second synchronous rectification elements The switching element of the first synchronous rectification element is turned off at a time when the value and the current value starting to flow through the diode of the second synchronous rectification element to be conducted for the next rectification become equal to each other That has a first drive signal generator for outputting a driving signal, and a second drive signal generator for outputting a driving signal to turn on the switching elements of the second synchronous rectifierThe rectification loss of the secondary side circuit can be reduced, the size of the heat sink of the rectification unit can be reduced, and the efficiency of the entire circuit can be increased.Further, full-wave rectification enables efficient rectification with less loss than half-wave rectification. Furthermore, the rectification loss of the secondary circuit can be reduced, the size of the heat sink of the rectification unit can be reduced, and the efficiency of the entire circuit can be increased.
[0009]
  The invention of claim 2 is the invention of claim 1,A drive signal for the switching element of the first synchronous rectification element is generated from a detection signal of the one current detection unit, and the drive signal for the switching element of the second synchronous rectification element is the switching signal of the first synchronous rectification element. It is characterized in that it is an inverted signal of the drive signal of the element, and the drive signal generation unit can be simplified, and the cost and size can be reduced.
[0010]
  The invention of claim 3 is the invention of claim 1 or 2,The current detection unit includes a current detection resistor connected in series to the synchronous rectification element, and the drive signal generation unit switches the switching element of the synchronous rectification element based on a voltage generated at both ends of the current detection resistor. The current detection unit can be configured with a simple circuit configuration.
[0011]
  The invention of claim 4 is the invention of claim 3,The resistance value of the current detection resistor is such that the voltage across the current detection resistor generated with respect to the current flowing through the current detection resistor can drive the switching element of the synchronous rectification element in the drive signal generation unit The resistance value is a minimum voltage that can be amplified to a voltage, and loss in the current detection unit can be reduced.
[0012]
  The invention of claim 5 is the invention of claim 1 or 2, whereinThe current detection unit includes a current transformer including a primary coil and a secondary coil connected in series to the synchronous rectification element, a resistor connected in parallel to both ends of the secondary coil of the current transformer, and both ends of the resistor A rectifier diode connected in series with a secondary coil of the current transformer to rectify the voltage between the current transformer and the drive signal generator based on the output of the current detector output from the rectifier diode. A drive signal for the switching element of the synchronous rectification element is generated, and the rectification loss of the secondary side circuit can be reduced.
[0013]
  The invention of claim 6 is the invention according to any one of claims 1 to 5,The drive signal generation unit compares the output of the current detection unit with a reference voltage, and generates a drive signal of the switching element of the synchronous rectification element based on the comparison result. The rectification loss can be reduced, the size of the heat sink of the rectification unit can be reduced, and the efficiency of the entire circuit can be increased.
[0014]
  The invention of claim 7 is the invention according to any one of claims 1 to 6,The first and second drive signal generation units include a current value flowing through the first synchronous rectification element that has been turned on and has finished rectification, and a second synchronous rectification that should be turned on for the next rectification. A reference voltage that is the same voltage as the output voltage of the current detection unit at a time when current values that start to flow through the element diodes are equal to each other, and a detection signal of the current detection unit are compared, and based on the comparison result, A drive signal for the switching element of the synchronous rectification element is generated, and the rectification loss of the secondary circuit can be reduced, the size of the heat sink of the rectification unit can be reduced, and the efficiency of the entire circuit can be increased.
[0015]
  The invention according to claim 8 is the invention according to any one of claims 1 to 6,The second drive signal generation unit includes a current value flowing through the first synchronous rectification element that has been turned on and finished rectification, and a diode of the second synchronous rectification element that should be turned on for the next rectification. And output a drive signal amplified to a voltage that can turn on the switching element of the second synchronous rectification element at a time when the current value starting to flow is equal to each other. By reducing the size, the size of the heat sink of the rectifying unit can be reduced, and the efficiency of the entire circuit can be increased.
[0016]
  The invention of claim 9 is the invention according to any one of claims 1 to 8,The inverter part is composed of a half-bridge inverter having a switching element, and the switching element performs zero volt switching, and the rectification loss of the secondary side circuit can be reduced and the size of the heat sink of the rectification part can be reduced. The efficiency of the entire circuit can be increased.
[0017]
DETAILED DESCRIPTION OF THE INVENTION
  Hereinafter, embodiments of the present invention will be described with reference to the drawings.
[0018]
    (Reference example 1)
  Figure 1Reference example 1The circuit configuration of is shown. The power supply unit A, the inverter unit B, and the primary coil L1 of the transformer T1 constitute a primary side circuit G1, and the secondary coil L2 of the transformer T1, the load matching capacitor C1, and the FET Q1 constituting a synchronous rectification element and current detection The part H1, the drive signal generation part E1, and the smoothing part F constitute a secondary circuit G2.
[0019]
  The power supply unit A supplies DC power to the inverter unit B and is converted into high-frequency power by the inverter unit B, and the high-frequency power is supplied to the primary coil L1 of the transformer T1. The secondary coil L2 of the transformer T1 receives power from the primary coil L1 by electromagnetic coupling. The voltage across the secondary coil L2 is half-wave rectified by the FET Q1, and the half-wave rectified voltage is smoothed by the smoothing unit F. Output a DC voltage.
[0020]
  The primary coil L1 and the secondary coil L2 of the transformer T1 are separated from each other by a predetermined gap length by an insulator, and can be separated and detached.
[0021]
  The capacitor C1 connected in parallel with the secondary coil L2 is for load matching, and maximizes the effective power that can be extracted by the secondary side circuit G2 to increase the efficiency of power transmission from the primary side circuit G1 to the secondary side circuit G2. Raised.
[0022]
  Next bookReference exampleThe synchronous rectification operation will be described.
[0023]
  The FET Q1 includes an FET element P1 and a parasitic diode D1 connected in parallel to the FET element P1 in the reverse direction. The current detection unit H1 connected in series with the FET Q1 detects the current flowing through the FET Q1, and outputs the detection signal to the drive signal generation unit E1. The drive signal generation unit E1 outputs a drive signal for turning on the FET element P1 if the detection signal from the current detection unit H1 is equal to or greater than a predetermined threshold, and the signal from the current detection unit H1 is a predetermined threshold. If the value is less than the value, a drive signal for turning off the FET element P1 is output.
[0024]
  When the polarity of the electromotive force induced from the primary coil L1 to the secondary coil L2 by electromagnetic induction matches the forward direction of the parasitic diode D1 of the FET Q1, a forward current flows through the parasitic diode D1, and the forward current is When detected by the current detection unit H1, the drive signal generation unit E1 outputs an ON signal to the FET element P1 when the detection signal from the current detection unit H1 exceeds the threshold value, and the FET element P1 is turned on.
[0025]
  When the FET element P1 is turned on, the current initially flowing through the parasitic diode D1 flows in the direction from the source of the FET Q1 to the drain via the ON resistance of the FET element P1 because the resistance of the FET element P1 is smaller than that of the parasitic diode D1. At this time, if the ON time of the FET element is made as long as possible during the cycle in which the rectified current flows in the FET Q1, the loss in the FET Q1 can be reduced and the rectified loss can be reduced.
[0026]
  When the electromotive force induced from the primary coil L1 to the secondary coil L2 is changed by electromagnetic induction and the electromotive force induced in the secondary coil L2 is reduced, the detection signal output from the current detection unit H1 is also reduced. When the detection signal from the current detection unit H1 falls below the threshold value, the signal generation unit E1 outputs an off signal to the FET element P1, and the FET element P1 is turned off.
[0027]
  Further, when the polarity of the electromotive force induced in the secondary coil L2 is inverted, a reverse voltage is applied to the parasitic diode D1 of the FET element P1, so that the polarity of the electromotive force induced in the secondary coil L2 is inverted again. Until this time, no current flows through the parasitic diode D1, and the input of the smoothing section F has a half-wave rectified waveform. The half-wave rectified output is smoothed by the smoothing unit F.
[0028]
  Figure 2 shows the bookReference exampleA current waveform S1 flowing through the FET Q1 is shown, and the current waveform S1 has a gently rising and distorted waveform.
[0029]
  The loss at the time of synchronous rectification is the time t1 when the current waveform S1 exceeds the ON threshold value K of the FET element P1 and the FET element P1 is turned on, and the current waveform S1 is the ON threshold of the FET element P1. The time when the FET element P1 falls below the value K is t2 is OFF, the time when the current waveform S1 is 0 is t3, the ON resistance of the FET element P1 during the synchronous rectification is Ron, and the current flowing through the FET Q1 is I, Assuming that the forward voltage of the parasitic diode D1 is Vf, the total loss W in one cycle is expressed by the following formula 1.
[0030]
[Expression 1]
[0031]
  Thus, if the current flowing through the FET Q1 is detected and the FET element P1 is driven by a signal synchronized with the detection signal, the time during which the current flows through the parasitic diode D1 of the FET Q1 can be shortened, and the loss in the FET Q1 is reduced. Can be reduced. As a result, since the size of the heat sink can be reduced, the secondary circuit G2 can be reduced in size.
[0032]
    (Reference example 2)
  Figure 3Reference example 2The circuit configuration of is shown. The configuration and operation of the primary side circuit G1 including the power source A, the inverter B, and the primary coil L1 of the transformer T1 are as follows.Reference example 1Since it is the same as that, it is omitted.
[0033]
  The secondary coil L2 of the transformer T1 has a center tap system with three output terminals, and has three terminals, terminals 1 and 3 at both ends of the secondary coil L2 and a center tap terminal 2, and the secondary coil L2. A load matching capacitor C1 is connected between the terminal 1 and the terminal 3 in parallel. The drain of the FET Q1 constituting the synchronous rectification element is connected in series to the terminal 1 of the secondary coil L2 via the current detection unit H1, and the synchronous rectification element is connected in series to the terminal 3 of the secondary coil L2 via the current detection unit H3. Is connected to the drain of the FET Q2. The sources of the FETs Q1 and Q2 are connected to each other and connected to the negative side of the smoothing capacitor C8, and the terminal 3 of the secondary coil L2 is connected to the positive side of the smoothing capacitor C8 via the choke coil L3.
[0034]
  Then bookReference exampleWill be described. The FET Q1 includes an FET element P1 and a parasitic diode D1 connected in parallel to the FET element P1 in the reverse direction. The current detection unit H1 connected in series with the FET Q1 detects the current flowing through the FET Q1, and outputs the detection signal to the drive signal generation unit E1. The drive signal generation unit E1 outputs a drive signal for turning on the FET element P1 if the detection signal from the current detection unit H1 is equal to or greater than a predetermined threshold, and the signal from the current detection unit H1 is a predetermined threshold. If the value is less than the value, a drive signal for turning off the FET element P1 is output.
[0035]
  Similarly, the FET Q2 includes an FET element P2 and a parasitic diode D2 connected in parallel to the FET element P2 in the reverse direction. The current detection unit H2 connected in series to the FET Q2 detects the current flowing through the FET Q2, and outputs the detection signal to the drive signal generation unit E2. The drive signal generation unit E2 outputs a drive signal for turning on the FET element P2 if the detection signal from the current detection unit H2 is equal to or greater than a predetermined threshold, and the signal from the current detection unit H2 is a predetermined threshold. If it is less than the value, a drive signal for turning off the FET element P2 is output.
[0036]
  When the polarity of the electromotive force induced between the primary coil L1 and the terminal 2-1 of the secondary coil L2 by electromagnetic induction matches the forward direction of the parasitic diode D1 of the FET Q1, a forward current flows through the parasitic diode D1, The forward current is detected by the current detection unit H1, and the drive signal generation unit E1 outputs an ON signal to the FET element P1 when the detection signal of the current detection unit H1 exceeds the threshold value, and the FET element P1 is turned on. To do.
When the FET element P1 is turned on, the current initially flowing through the parasitic diode D1 flows in the direction from the source of the FET Q1 to the drain via the on-resistance of the FET element P1 because the resistance of the FET element P1 is smaller than that of the parasitic diode D1. At this time,Reference example 1Similarly, the loss in the FET Q1 can be reduced and the rectification loss can be reduced by increasing the ON time of the FET element as much as possible during the cycle in which the rectification current flows in the FET Q1.
[0037]
  When the electromotive force induced from the primary coil L1 to the secondary coil L2 is changed by electromagnetic induction and the electromotive force induced in the secondary coil L2 is reduced, the detection signal output from the current detection unit H1 is also reduced. When the detection signal from the current detection unit H1 falls below the threshold value, the signal generation unit E1 outputs an off signal to the FET element P1, and the FET element P1 is turned off.
[0038]
  Further, when the polarity of the electromotive force induced in the secondary coil L2 is reversed, a reverse voltage is applied to the parasitic diode D1 of the FET element P1, so that the polarity of the electromotive force induced in the secondary coil L2 is reversed again. No current flows through the parasitic diode D1.
[0039]
  On the other hand, since the polarity of the electromotive force induced between the primary coil L1 and the terminal 2-3 of the secondary coil L2 by electromagnetic induction coincides with the forward direction of the parasitic diode D2 of the FET Q2, the parasitic diode D2 A forward current flows through the FET Q2, the FET element P2, the parasitic diode D2, the current detection unit H2, and the drive signal generation unit E2. The FET Q1, the FET element P1, the parasitic diode D1, the current detection unit H1, and the drive signal generation unit E1 The same operation is performed.
[0040]
  By repeating the above operation, a full-wave rectified voltage is generated between the sources of the FETs Q1 and Q2 and the terminal 2 of the secondary coil L2, and is smoothed by the choke coil L3 and the smoothing capacitor C8.
[0041]
  FIG. 4 shows an induced electromotive force waveform S2 between the terminals 1-3 of the secondary coil L2, a current waveform S3 flowing through the secondary coil L2, and an ON threshold value K of the FETs Q1 and Q2. Due to the influence of the load matching capacitor C1, the current waveform S3 of the secondary coil L2 becomes a distorted waveform, and the voltage waveform S2 induced between the terminals 1-3 of the secondary coil L2 sandwiches a section where the constant section is 0V. The waveform vibrates positively and negatively. For this reason, in the conventional FET driving method using the auxiliary winding or the voltage between the secondary coils, when the on threshold value K of the FETs Q1 and Q2 is compared with the voltage waveform S2, the driving signal of the FET is as shown by the waveform S4. Therefore, the rectification efficiency does not increase because the time for turning on the FETs Q1 and Q2 is short.
[0042]
  However, as shown in FIG. 5, the current waveform S5 flowing through the FET Q1 is compared with the ON threshold value K of the FETs Q1 and Q2, and the current waveform S6 flowing through the FET Q2 is compared with the ON threshold value K of the FETs Q1 and Q2. Thus, the drive signals of the FETs Q1 and Q2 have waveforms S7 and S8, respectively, and the on-time of the FET elements P1 and P2 of the FETs Q1 and Q2 becomes longer than the waveform S4 of FIG. Therefore, the time during which the rectified current flows through the FET elements P1 and P2 becomes longer, and the rectification efficiency increases.
[0043]
  Also bookReference exampleA full-wave rectifier circuit using a transformer T1 in which the secondary coil shown in FIG.Reference example 1When the same output current is passed, the full-wave rectifier circuit can reduce the maximum value of the current passed through the FET as compared with the half-wave rectifier circuit. Since the loss when the FET elements P1 and P2 are turned on is proportional to the square of the current,Reference exampleThen, the current flowing through the FET elements P1 and P2 can be made smaller than that of the half-wave rectifier circuit, and the loss can be reduced.
[0044]
  As in the circuit configuration shown in FIG. 6, the load matching capacitor C1 is connected in parallel between the terminal 1 and the terminal 2 of the secondary coil L2, and the load matching capacitor C9 is connected to the terminal 2 of the secondary coil L2. The same effect as the load matching capacitor C1 of FIG. Further, the same effect can be obtained by connecting the capacitor C1 in parallel to the FET Q1 and connecting the capacitor C9 in parallel to the FET Q2.
[0045]
  In FIG. 1, the same effect can be obtained by connecting the load matching capacitor C1 in parallel to the FET Q1.
[0046]
    (Reference example 3)
  FIG.Reference example 3The power supply unit A that converts the AC power source to the DC power source, the inverter unit B that converts the DC input from the power source unit A to the high frequency power source, the control circuit J of the inverter unit B, and the inverter unit B The primary side circuit G1 is composed of the primary coil L1 of the transformer T1 to which power is supplied, a center tap type secondary coil L2 of the transformer T1, a load matching capacitor C1, current detection units H1 and H2, The drive signal generators E1 and E2, a secondary circuit G2 including FETs Q1 and Q2, a choke coil L3, and a smoothing capacitor C8.
[0047]
  The configuration and operation of the secondary side circuit G2 are as follows:Reference example 2Since it is the same as that of FIG. 3, description is abbreviate | omitted.
[0048]
  The configuration and operation of the primary side circuit G1 will be described. The power supply unit A is composed of an AC power supply Vs and a rectifier D3 for full-wave rectification of the AC power supply Vs, and the inverter unit B is a series circuit of capacitors C2 and C3 connected in parallel to the output terminal of the rectifier D3, and a rectifier D3. And a half-bridge inverter circuit comprising a series circuit of switching elements Q3 and Q4 connected in parallel to the output terminals of the capacitors and capacitors C4 and C5 connected in parallel to the switching elements Q3 and Q4, respectively. An electronic circuit for controlling the switching operation of the switching elements Q3 and Q4 is configured. One end of the primary coil L1 of the transformer T1 is connected to the midpoint of the capacitors C1 and C2, and the other end is connected to the switching elements Q1 and Q2. Connected to a point.
[0049]
  The voltage that has been full-wave rectified by the rectifier D3 is divided by the capacitors C2 and C3, and the switching elements Q3 and Q4 are alternately turned on and off by a drive signal having a certain dead time from the control circuit J to turn on and off the primary coil. A high frequency voltage is applied to L1.
[0050]
  Further, the capacitors C4 and C5 connected in parallel to the switching elements Q3 and Q4 can make the switching operation of the switching elements Q3 and Q4 a zero voltage switching operation, thereby reducing the switching loss in the switching elements Q3 and Q4. be able to.
[0051]
  Further, since the drive signals of the switching elements Q3 and Q4 have a certain dead time, the voltage between the terminal 1 and the terminal 3 of the secondary coil L2 of the transformer T1 is as shown by the waveform S2 in FIG.Reference example 2As in the case of synchronous rectification by FETs Q1 and Q2 with the drive signal generated from the detection signals of the current detection circuits H1 and H2,Reference example 2Similarly, the rectification loss of the secondary side circuit G2 can be reduced.
[0052]
  Further, when the capacitor C4 is connected in parallel to the primary coil L1 of the transformer T1 as in the circuit configuration shown in FIG. 8, zero voltage switching can be performed as in the circuit of FIG. Except for the above, the configuration and operation of the circuit of FIG. 8 are the same as the configuration and operation of the circuit of FIG.
[0053]
  Book like thisReference exampleAccording to this, it is possible to reduce the loss not only in the secondary side circuit G2 but also in the primary side circuit G1, increase the efficiency of the entire circuit, and reduce the size of the entire circuit.
[0054]
    (Reference example 4)
  Figure 9Reference example 4The circuit configuration of is shown. Basic circuit configuration and operationReference example 37 differs from the circuit configuration shown in FIG. 7 in that a signal obtained by inverting the drive signal of the drive signal generation unit E1 of the FET element P1 through the inverter INV1 is used as the drive signal of the FET element P2. For circuit configurations and operations other than those described aboveReference example 3Since this is the same as FIG.
[0055]
  As shown in the circuit configuration diagram of FIG. 9, in the synchronous rectifier circuit using the center tap method for the secondary coil L2 of the transformer T1, the drive signals of the FETs Q1 and Q2 are controlled so that current flows alternately to the FETs Q1 and Q2. Therefore, each drive signal of the FETs Q1 and Q2 is an inverted signal of one drive signal. Therefore, by driving the FET Q2 using the signal obtained by inverting the drive signal of the drive signal generation unit E1 of the FET Q1 via the inverter INV1 as the drive signal of the FET Q2, the drive circuit of the FET Q2 can be simplified. Cost and size can be reduced.
[0056]
  In addition, even when a forward method using synchronous rectification is adopted as the rectifier circuit of the secondary side circuit G2, the present invention can be similarly applied to two rectifier and commutation switching elements.
[0057]
    (Reference Example 5)
  FIG.Reference Example 5The circuit block diagram of is shown. Basic circuit configuration and operationReference example 3FIG. 10 differs from FIG. 7 in that the current detection units H1 and H2 in FIG. 7 are replaced with current detection units H3 and H4 including resistors R1 and R2 connected in series to the FETs Q1 and Q2, respectively. . For circuit configurations and operations other than those described aboveReference example 3Since this is the same as FIG.
[0058]
  BookReference exampleThen, voltages proportional to the currents flowing through the FETs Q1 and Q2 are generated at both ends of the resistors R1 and R2 respectively connected in series to the FETs Q1 and Q2. The voltages at both ends of the resistors R1 and R2 are input to drive signal generators E1 and E2, respectively. The drive signal generators E1 and E2 are FETs if the voltages at both ends of the resistors R1 and R2 are equal to or higher than a predetermined threshold value. A drive signal for turning on the elements P1 and P2 is output, and a drive signal for turning off the FET elements P1 and P2 is output if the voltage across the resistors R1 and R2 is equal to or lower than a predetermined threshold value.
[0059]
  Book like thisReference exampleCan detect the currents of the FETs Q1 and Q2 by a simple method and generate the drive signals of the FETs Q1 and Q2 using the detection signal.Reference example 2Similarly, the rectification loss can be reduced by turning on the FET elements P1 and P2 for as long as possible during each rectification cycle in which current flows in the FETs Q1 and Q2.
[0060]
    (Reference Example 6)
  Figure 11 is a bookReference Example 6Shows the circuit configuration diagram of the basic circuit configuration and operationReference Example 5In FIG. 11, the resistors R1 and R2 in FIG. 10 are replaced with current detectors H5 and H6 each having resistors R3 and R4 each having a minute resistance value (for example, 10 mΩ), and the drive signal generator E1 is replaced. , E2 is replaced with drive signal generation units E3, E4 each composed of operational amplifiers OP1, OP2. For circuit configurations and operations other than those described aboveReference Example 5Since this is the same as FIG.
[0061]
  BookReference exampleThen, by setting the resistance values of the resistors R3 and R4 connected in series to the FETs Q1 and Q2 to be very small (for example, 10 mΩ),Reference Example 5Compared to the above, the loss at the resistors R3 and R4 is reduced. However, by reducing the resistance values of the resistors R3 and R4, the voltages at both ends of the resistors R3 and R4 are also reduced. Therefore, the voltages at both ends of the resistors R3 and R4 are input to the inverting input terminal and the non-inverting input terminal of the operational amplifiers OP1 and OP2, respectively. Then, the operational amplifiers OP1 and OP2 differentially amplify the voltages at both ends of the resistors R3 and R4 to voltages that can sufficiently drive the FETs Q1 and Q2, and the outputs of the differentially amplified operational amplifiers OP1 and OP2 are applied to the FET elements P1 and P2. Let it be a drive signal.
[0062]
  Book like thisReference exampleThen, the loss in the current detection units H5 and H6 can be reduced.
[0063]
    (Reference Example 7)
  FIG.Reference Example 7The circuit block diagram of is shown. Basic circuit configuration and operationReference example 37 is substantially the same as FIG. 7, and in FIG. 12, the current detection units H1 and H2 of FIG. 7 are replaced with primary coils L4 and L5 and secondary coils L6 and L7, and current transformers CT1 and CT2 secondary coils L6 and L7. Resistors R5 and R6 are respectively connected in parallel, diodes D3 and D4 are respectively connected in series to the secondary coils L6 and L7, and capacitors C6 and C7 are connected in parallel to the resistors R5 and R6 via the diodes D3 and D4. Resistors R7 and R8 and constant voltage diodes ZD1 and ZD2 are replaced with current detection units H7 and H8, respectively, and drive signal generation units E1 and E2 of FIG. 7 are connected in series with diodes D3 and D4, respectively. The difference is that the drive signal generators E5 and E6 are made of AMP2. For circuit configurations and operations other than those described aboveReference example 3Since this is the same as FIG.
[0064]
  Currents flowing through the primary coils L4 and L5 of the current transformers CT1 and CT2 are detected by the secondary coils L6 and L7 of the current transformers CT1 and CT2, respectively, and voltages are generated at both ends of the resistors R5 and R6. Half-wave rectification is performed by diodes D3 and D4. Capacitors C6 and C7 are for noise cut. Resistors R7 and R8 discharge charges accumulated in the capacitors C6 and C7 to make the fall of the input signals of AMP1 and AMP2 steep. The constant voltage diodes ZD1 and ZD2 clamp the half-wave rectified voltage at a constant voltage so that a voltage exceeding the rated voltage of the amplifiers AMP1 and AMP2 is not input to the inputs of the amplifiers AMP1 and AMP2.
[0065]
  Since the FET coils P1 and P2 cannot be driven because the output currents of the secondary coils L6 and L7 of the current transformers CT1 and CT2 are small, they are amplified by the amplifiers AMP1 and AMP2, and the FETs Q1 and Q2 are driven by the amplified drive signals. To do.
[0066]
  Book like thisReference exampleCan detect the currents flowing through the FETs Q1 and Q2, and generate the drive signals for the FETs Q1 and Q2 using the detection signal.Reference example 2Similarly, the rectification loss can be reduced by turning on the FET elements P1 and P2 for as long as possible during each rectification cycle in which current flows in the FETs Q1 and Q2.
[0067]
    (Reference Example 8)
  Using the circuit configuration diagram of FIG.Reference Example 8Will be explained. Basic circuit configuration and operationReference Example 712. In FIG. 13, the amplifiers AMP1 and AMP2 of FIG. 12 are connected to comparators CP1 and CP2 and comparators CP1 and CP2 with reference voltage sources E1 and E2 connected to the inverting input terminals, respectively. The point of replacement is different. For circuit configurations and operations other than those described aboveReference Example 7Since this is the same as FIG.
[0068]
  In this reference example, the outputs of the secondary coils L6 and L7 of the current transformers CT1 and CT2 half-wave rectified by the diodes D3 and D4 are connected to the non-inverting input terminals of the comparators CP1 and CP2, respectively, and the reference voltage source E1 , E2 to the inverting input terminals of the comparators CP1 and CP2, respectively, and by appropriately setting the reference voltages of the reference voltage sources E1 and E2, as long as possible during each rectification cycle in which current flows in the FETs Q1 and Q2. The FET elements P1 and P2 can be turned on to reduce rectification loss.
[0069]
  Figure 14 shows the bookReference exampleShows the current waveform S9 flowing through the FET Q1, the reference voltage M1 of the reference voltage source E1, and the output waveform S10 of the comparator CP1. When the waveform S9 exceeds the reference voltage M1, the waveform S10 becomes H level, When the waveform S9 falls below the reference voltage M1, the waveform S10 becomes L level. Therefore, by appropriately setting the reference voltage M1, the section where the output waveform S10 of the comparator CP1 is at the H level can be widened. The same applies to the FET Q2.
[0070]
  That is, the rectification loss can be reduced by turning on the FET elements P1 and P2 for as long as possible during each rectification cycle in which current flows in the FETs Q1 and Q2.
[0071]
    (Embodiment 1)
  Using the circuit configuration diagram of FIG.Embodiment 1Will be explained. For basic circuit configuration and operationReference Example 8Since it is the same as that, it is omitted.
[0072]
  The current of the FET Q1 having the FET element P1 that has been turned on to perform synchronous rectification smoothly decreases in accordance with the induced electromotive force generated in the secondary coil L2 due to the load matching capacitor C6. . Similarly, the FET Q2 having the FET element P2 that is turned on to perform the next half-cycle synchronous rectification similarly starts to flow through the parasitic diode D2 before the current flowing through the FET Q1 becomes zero because of the capacitor C6. Therefore, the FET elements P1 and P2 may be turned on at the same time, and rectification may not be performed.
[0073]
  So this embodimentIn stateOutputs a drive signal from the comparator CP1 to turn off the FET element P1 that has been turned on until each current flowing through the FETs Q1 and Q2 becomes equal, and turns on the FET element P2 that has been turned off until then. A drive signal is output from the comparator CP2. Similarly, in the reverse half cycle, when the currents flowing through the FETs Q1 and Q2 become equal, a driving signal for turning off the FET element P2 that has been turned on is output from the comparator CP2, and has been turned off until then. A drive signal for turning on the FET element P1 is output from the comparator CP1.
[0074]
  In this way, this embodimentStateAccordingly, the FET elements P1 and P2 are not turned on at the same time, and the secondary side circuit G2 including the heat sink can be reduced in size by reducing the rectification loss.
[0075]
    (Embodiment 2)
  Using the circuit configuration diagram of FIG.Embodiment 2Will be explained. For basic circuit configuration and operationEmbodiment 1Since it is the same as that, it is omitted.
[0076]
  Embodiment 1As described above, when the currents flowing through the FETs Q1 and Q2 become equal, the comparator CP1 outputs a drive signal for turning off the FET element P1 that has been turned on, and the FET element P2 that has been turned off until then. A drive signal for turning on is output from the comparator CP2. Similarly, in the reverse half cycle, when the currents flowing through the FETs Q1 and Q2 become equal, a driving signal for turning off the FET element P2 that has been turned on is output from the comparator CP2, and has been turned off until then. If the driving signal for turning on the FET element P1 is output from the comparator CP1, the FET elements P1 and P2 are not turned on at the same time, and the rectification loss can be reduced.
[0077]
  Therefore, this embodimentIn state13 represents the output voltages obtained by half-wave rectifying the detection signals detected by the current transformers CT1 and CT2 with the diodes D3 and D4 in the circuit configuration of FIG. 13, that is, the output voltages of the constant voltage diodes ZD1 and ZD2, respectively. Reference voltage sources E1 and E2 having reference voltages as output voltages of constant voltage diodes ZD1 and ZD2 when input to the inverting input terminal and the currents flowing through the FETs Q1 and Q2 become equal are the inverting inputs of the comparators CP1 and CP2. By connecting each of the terminals to the input and using the outputs of the comparators CP1 and CP2 as drive signals for the FET elements P1 and P2, the FET elements P1 and P2 are not simultaneously turned on, reducing rectification loss and radiating heat. The secondary circuit G2 including the plate can be reduced in size.
[0078]
  FIG. 15 shows the present embodiment.StateCurrent waveform S11 flowing through FET Q1, reference voltage M2 of reference voltage source E1, output waveform S12 of comparator CP1, current waveform S13 flowing through FET Q2, reference voltage M3 of reference voltage source E2, output waveform S14 of comparator CP2 and Indicates. At time t4 when the magnitude of the current waveform S11 flowing through the FET Q1 is equal to the magnitude of the current waveform S13 flowing through the FET Q2, the output of the comparator CP1 is set to L, the FET element P1 is turned off, and the output of the comparator CP2 is set to H. By turning on the element P2, the FET elements P1 and P2 are not turned on at the same time, and the secondary side circuit G2 including the heat sink can be reduced in size by reducing the rectification loss.
[0079]
    (Embodiment 3)
  Using the circuit configuration diagram of FIG.Embodiment 3Will be explained. For basic circuit configuration and operationReference Example 7Since it is the same as that, it is omitted.
[0080]
  Embodiment 1As described in the above, when the currents flowing through the FETs Q1 and Q2 become equal, the driving signal for turning off the FET Q1 that has been turned on is output from the comparator CP1, and the FET Q2 that has been turned off is turned on. A drive signal is output from the comparator CP2. Similarly, in the reverse half cycle, when the currents flowing through the FETs Q1 and Q2 become equal, a driving signal for turning off the FET Q2 that has been turned on is output from the comparator CP2, and the FET Q1 that has been turned off until then is output. If the driving signal to be turned on is output from the comparator CP1, the FETs Q1 and Q2 are not turned on at the same time, and rectification loss can be reduced.
[0081]
  Therefore, this embodimentIn state12 is an output voltage obtained by half-wave rectifying the detection signals detected by the current transformers CT1 and CT2 with the diodes D3 and D4 when the currents flowing through the FETs Q1 and Q2 become equal in the circuit configuration of FIG. 12, that is, constant voltage diodes ZD1 and ZD2. The output voltages of the FETs P1 and P2 obtained by amplifying the output voltages of the amplifiers AMP1 and AMP2 respectively become voltages that can sufficiently turn on the FET elements P1 and P2, and the primary coil L4 and the secondary of the current transformer CT1. The winding ratio with the coil L6 and the winding ratio between the primary coil L5 and the secondary coil L7 of the current transformer CT2 are set.
[0082]
  FIG. 16 shows the present embodiment.StateDrive signal waveform S15 of FET element P1, current waveform S16 flowing through FET Q1, clamp voltage N1 of constant voltage diode ZD1, drive signal waveform S17 of FET element P2, current waveform S18 flowing through FET Q2, clamp voltage of constant voltage diode ZD2 N2 and a voltage K that can sufficiently turn on the FET elements P1 and P2. At time t5 when the magnitude of the current waveform S16 flowing through the FET Q1 is equal to the magnitude of the current waveform S18 flowing through the FET Q2, the drive signal waveform S15 of the FET element P1 drops below the voltage K that can sufficiently turn on the FET elements P1 and P2, and the FET element. P1 is turned off, and the drive signal waveform S17 of the FET element P2 exceeds the voltage K that can sufficiently turn on the FET elements P1 and P2, and the FET element P2 is turned on so that the FET elements P1 and P2 are not turned on at the same time. The secondary side circuit G2 including the heat sink can be reduced in size by reducing the rectification loss.
[0083]
  The waveforms S15 and S17 are clamped to the clamp voltages N1 and N2 of the constant voltage diodes ZD1 and ZD2.
[0084]
    (Reference Example 9)
  As shown in the circuit configuration diagram of FIG. 1, when half-wave rectification is performed using one synchronous rectification FET Q1, in order to reduce the rectification loss in FET Q1, as long as possible during the rectification cycle in which current flows in FET Q1. It is necessary to turn on the FET element P1 of the FET Q1.
[0085]
  The current detection unit H1 and the drive signal generation unit E1 in FIG. 1 are respectively replaced with the current detection unit H9 and the drive signal generation unit E7 in FIG. 13, and connected to the inverting input terminal of the comparator CP1 of the drive signal generation unit E7. By making the reference voltage of the reference voltage source E1 close to 0V, the comparator CP1 outputs a drive signal for turning on the FET element P1 for as long as possible during the rectification cycle, thereby reducing the rectification loss in the FET Q1. Thus, the secondary circuit G2 including the heat sink can be reduced in size.
[0086]
  For circuit configurations and operations other than the above,Reference Examples 1 and 8The explanation is omitted here.
[0087]
    (Reference Example 10)
  As shown in the circuit configuration diagram of FIG. 1, when half-wave rectification is performed using one synchronous rectification FET Q1, in order to reduce the rectification loss in FET Q1, as long as possible during the rectification cycle in which current flows in FET Q1. It is necessary to turn on the FET element P1 of the FET Q1.
[0088]
  The current detection unit H1 and the drive signal generation unit E1 in FIG. 1 are respectively replaced with the current detection unit H7 and the drive signal generation unit E5 in FIG. 12, and the primary coil L4 and the secondary coil of the current transformer CT1 of the current detection unit H7 are replaced. By increasing the turn ratio of the coil L5, even when the current flowing through the primary coil L4 of the current transformer CT1 is small, the induced voltage of the secondary coil L5 increases, and the drive signal that can turn on the FET element P1 of the FET Q1 is an amplifier AMP1. Is output from. Therefore, the rectifying element P1 is turned on as long as possible during the rectification cycle, and the secondary side circuit G2 including the heat sink can be reduced in size by reducing the rectification loss in the FET Q1.
[0089]
  For circuit configurations and operations other than the above,Reference Examples 1 and 7The explanation is omitted here.
[0090]
【The invention's effect】
  The invention according to claim 1 is a power supply section that supplies a DC power supply, an inverter section that converts the DC power supply to a high-frequency power supply, a primary coil that is supplied with high-frequency power from the inverter section, and power that is received from the primary coil A secondary side circuit configured to be separable from the primary coil of the transformer, the secondary coil, a load matching capacitor connected in parallel to the secondary coil, and the Non-contact power having a secondary side circuit composed of a rectifying unit that rectifies the output voltage of the secondary coilTransmissionIn the deviceThe secondary coil of the transformer includes a center tap, and includes first and second synchronous rectification elements including a switching element and a diode reversely connected in parallel to the switching element, and the secondary coil of the transformer Full-wave rectification by connecting each other end not connected to the secondary coil of the transformer of the first and second synchronous rectification elements connected in series and in opposite directions to both output ends which are not center taps The current flowing through the first synchronous rectification element that has been conducted earlier and has finished rectification, and the rectification section that constitutes a section, a current detection section that detects a current flowing through the first and second synchronous rectification elements The switching element of the first synchronous rectification element is turned off at a time when the value and the current value starting to flow through the diode of the second synchronous rectification element to be conducted for the next rectification become equal to each other That has a first drive signal generator for outputting a driving signal, and a second drive signal generator for outputting a driving signal to turn on the switching elements of the second synchronous rectifierThis is advantageous in that the rectification loss of the secondary circuit can be reduced, the size of the heat sink of the rectification unit can be reduced, and the efficiency of the entire circuit can be increased.In addition, full-wave rectification has an effect of performing efficient rectification with less loss than half-wave rectification. Furthermore, there is an effect that the rectification loss of the secondary circuit can be reduced, the size of the heat sink of the rectification unit can be reduced, and the efficiency of the entire circuit can be increased.
[0091]
  The invention of claim 2 is the invention of claim 1,A drive signal for the switching element of the first synchronous rectification element is generated from a detection signal of the one current detection unit, and the drive signal for the switching element of the second synchronous rectification element is the switching signal of the first synchronous rectification element. It is characterized in that it is an inverted signal of the drive signal of the element, and it is possible to simplify the drive signal generation unit, and there is an effect that the cost can be reduced and the size can be reduced.
[0092]
  The invention of claim 3 is the invention of claim 1 or 2,The current detection unit includes a current detection resistor connected in series to the synchronous rectification element, and the drive signal generation unit switches the switching element of the synchronous rectification element based on a voltage generated at both ends of the current detection resistor. The driving signal is generated, and the current detection unit can be configured with a simple circuit configuration.
[0093]
  The invention of claim 4 is the invention of claim 3,The resistance value of the current detection resistor is such that the voltage across the current detection resistor generated with respect to the current flowing through the current detection resistor can drive the switching element of the synchronous rectification element in the drive signal generation unit The resistance value is a minimum voltage that can be amplified to a voltage, and there is an effect that the loss in the current detection unit can be reduced.
[0094]
  The invention of claim 5 is the invention of claim 1 or 2, whereinThe current detection unit includes a current transformer including a primary coil and a secondary coil connected in series to the synchronous rectification element, a resistor connected in parallel to both ends of the secondary coil of the current transformer, and both ends of the resistor A rectifier diode connected in series with a secondary coil of the current transformer to rectify the voltage between the current transformer and the drive signal generator based on the output of the current detector output from the rectifier diode. A drive signal for the switching element of the synchronous rectification element is generated, and the rectification loss of the secondary side circuit can be reduced.
[0095]
  The invention of claim 6 is the invention according to any one of claims 1 to 5,The drive signal generation unit compares the output of the current detection unit with a reference voltage, and generates a drive signal of the switching element of the synchronous rectification element based on the comparison result. There is an effect that the rectification loss can be reduced, the size of the heat sink of the rectification unit can be reduced, and the efficiency of the entire circuit can be increased.
[0096]
  The invention of claim 7 is the invention according to any one of claims 1 to 6,The first and second drive signal generation units include a current value flowing through the first synchronous rectification element that has been turned on and has finished rectification, and a second synchronous rectification that should be turned on for the next rectification. A reference voltage that is the same voltage as the output voltage of the current detection unit at a time when the current values that start to flow through the element diodes are equal to each other, and a detection signal of the current detection unit are compared, and based on the comparison result, It is characterized in that it generates a drive signal for the switching element of the synchronous rectifying element, reduces the rectification loss of the secondary side circuit, reduces the size of the heat sink of the rectifying unit, and increases the efficiency of the entire circuit There is.
[0097]
  The invention of claim 8 is the invention according to any one of claims 1 to 6,The second drive signal generation unit includes a current value flowing through the first synchronous rectification element that has been turned on and finished rectification, and a diode of the second synchronous rectification element that should be turned on for the next rectification. And output a drive signal amplified to a voltage that can turn on the switching element of the second synchronous rectification element at a time when the current value starting to flow is equal to each other. This reduces the size of the radiating plate of the rectifying unit, and can increase the efficiency of the entire circuit.
[0098]
  The invention of claim 9 is the invention according to any one of claims 1 to 8,The inverter part is composed of a half-bridge inverter having a switching element, and the switching element performs zero volt switching, and the rectification loss of the secondary side circuit can be reduced and the size of the heat sink of the rectification part can be reduced. There is an effect that the efficiency of the entire circuit can be increased.
[Brief description of the drawings]
FIG. 1 of the present inventionReference examples 1, 9, 10FIG.
FIG. 2 of the present inventionReference example 1It is a figure which shows the current waveform which flows into FET of this.
FIG. 3 of the present inventionReference example 2FIG.
FIG. 4 of the present inventionReference example 2FIG.
FIG. 5 shows the present invention.Reference example 2It is a figure which shows the switching operation | movement of FET element.
FIG. 6 of the present inventionReference example 2FIG.
[Fig. 7] of the present invention.Reference example 3FIG.
[Fig. 8] of the present inventionReference example 3FIG.
FIG. 9 shows the present invention.Reference example 4FIG.
FIG. 10 shows the present invention.Reference Example 5FIG.
FIG. 11 shows the present invention.Reference Example 6FIG.
FIG. 12 shows the present invention.Embodiment 3, Reference Example 7FIG.
FIG. 13 shows the present invention.Embodiments 1 and 2, Reference Example 8FIG.
FIG. 14 shows the present invention.Reference Example 8It is a figure which shows the switching operation | movement of.
FIG. 15 shows the present invention.Embodiment 2It is a figure which shows the switching operation | movement of.
FIG. 16 shows the present invention.Embodiment 3It is a figure which shows no switching operation.
[Explanation of symbols]
  A Power supply
  B Inverter part
  C1 capacitor
  D1 Parasitic diode
  E1 Drive signal generator
  F Smoothing part
  G1 Primary side circuit
  G2 secondary circuit
  H1 Current detector
  L1 primary coil
  L2 secondary coil
  P1 FET element
  Q1 FET
  T1 transformer

Claims (9)

  1. A power supply unit that supplies a DC power supply, an inverter unit that converts the DC power supply to a high-frequency power source, a primary coil that is supplied with high-frequency power from the inverter unit, and a secondary coil that outputs the power received from the primary coil; A primary circuit composed of the primary coil of the separable transformer, the secondary coil, a load matching capacitor connected in parallel to the secondary coil, and an output voltage of the secondary coil. In a non-contact power transmission device having a secondary circuit composed of a rectifying unit that rectifies,
    The secondary coil of the transformer includes a center tap,
    The first and second synchronous rectifying elements, each of which includes a switching element and a diode reversely connected in parallel to the switching element, are connected in series to both output ends that are not center taps of the secondary coil of the transformer, and to each other. The rectification unit configured by connecting the other ends not connected to the secondary coil of the transformer of the first and second synchronous rectification elements connected in the reverse direction to form a full-wave rectification unit;
    A current detection unit for detecting a current flowing through the first and second synchronous rectification elements;
    The current value that flows through the first synchronous rectification element that has been turned on first and ends rectification, and the current value that starts to flow through the diode of the second synchronous rectification element that should be turned on for the next rectification A drive signal generating section for outputting a drive signal for turning off the switching element of the first synchronous rectification element, and a drive signal for turning on the switching element of the second synchronous rectification element at the same time; A non-contact power transmission device comprising: a second drive signal generation unit for outputting.
  2. A drive signal for the switching element of the first synchronous rectification element is generated from a detection signal of the one current detection unit, and the drive signal for the switching element of the second synchronous rectification element is the switching signal of the first synchronous rectification element. The non-contact power transmission device according to claim 1, wherein the non-contact power transmission device is an inverted signal of an element drive signal.
  3. The current detection unit includes a current detection resistor connected in series to the synchronous rectification element, and the drive signal generation unit switches the switching element of the synchronous rectification element based on a voltage generated at both ends of the current detection resistor. The non-contact power transmission device according to claim 1, wherein the driving signal is generated.
  4. The resistance value of the current detection resistor is such that the voltage across the current detection resistor generated with respect to the current flowing through the current detection resistor can drive the switching element of the synchronous rectification element in the drive signal generation unit The non-contact power transmission device according to claim 3, wherein the resistance value is a minimum voltage that can be amplified to a voltage.
  5. The current detection unit includes a current transformer including a primary coil and a secondary coil connected in series to the synchronous rectification element, a resistor connected in parallel to both ends of the secondary coil of the current transformer, and both ends of the resistor A rectifier diode connected in series with a secondary coil of the current transformer to rectify the voltage between the current transformer and the drive signal generator based on the output of the current detector output from the rectifier diode. The non-contact power transmission device according to claim 1, wherein a driving signal for the switching element of the synchronous rectification element is generated.
  6. 6. The drive signal generation unit compares the output of the current detection unit and a reference voltage, and generates a drive signal of a switching element of the synchronous rectification element based on the comparison result. The non-contact power transmission device described in any one.
  7. The first and second drive signal generation units include a current value flowing through the first synchronous rectification element that has been turned on and has finished rectification, and a second synchronous rectification that should be turned on for the next rectification. A reference voltage that is the same voltage as the output voltage of the current detection unit at a time when current values that start to flow through the element diodes are equal to each other, and a detection signal of the current detection unit are compared, and based on the comparison result, 7. The non-contact power transmission device according to claim 1, wherein a drive signal for the switching element of the synchronous rectification element is generated.
  8. The second drive signal generation unit includes a current value flowing through the first synchronous rectification element that has been turned on and finished rectification, and a diode of the second synchronous rectification element that should be turned on for the next rectification. 7. The drive signal amplified to a voltage at which the switching element of the second synchronous rectification element can be turned on is output at a time when the current value starting to flow is equal to each other. Non-contact power transmission device.
  9. The non-contact power transmission apparatus according to claim 1, wherein the inverter unit includes a half-bridge inverter having a switching element, and the switching element performs zero-volt switching.
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