JPH10164837A - Power supply - Google Patents

Power supply

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Publication number
JPH10164837A
JPH10164837A JP31504996A JP31504996A JPH10164837A JP H10164837 A JPH10164837 A JP H10164837A JP 31504996 A JP31504996 A JP 31504996A JP 31504996 A JP31504996 A JP 31504996A JP H10164837 A JPH10164837 A JP H10164837A
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mos
power supply
fet
voltage
connected
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JP31504996A
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Japanese (ja)
Inventor
Akihiko Kikuchi
Masanobu Takahama
昭彦 菊池
昌信 高濱
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Sony Corp
ソニー株式会社
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    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02BCLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
    • Y02B70/00Technologies for an efficient end-user side electric power management and consumption
    • Y02B70/10Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion
    • Y02B70/14Reduction of losses in power supplies
    • Y02B70/1458Synchronous rectification
    • Y02B70/1475Synchronous rectification in galvanically isolated DC/DC converters

Abstract

PROBLEM TO BE SOLVED: To significantly reduce loss by using MOS-FETs for secondary-side rectification.
SOLUTION: The positive end of a direct current 100 obtained by rectifying an AC input is connected with the negative end through the collectors and emitters of switching transistors 1, 2. The middle point is connected with one end of the primary-side coil 5A of voltage changing transformer 5 through the coil 3A of a saturable reactor transformer 3 and a resonance capacitor 4. One and the other ends of the secondary-side coil 5B of the voltage changing transformer 5 are connected with each other through the sources and drains of N-channel MOS-FETs 19, 20, respectively. A capacitor 21 for smoothing is connected between the connecting point and the middle tap of the secondary- side coil 5B. The MOS-FETs 19, 20 are on/off-controlled by drive circuits 24, 25, respectively, and synchronously controlled, so that they will be on only when current flows from the capacitor 21 side to the coil 5B, for example.
COPYRIGHT: (C)1998,JPO

Description

【発明の詳細な説明】 DETAILED DESCRIPTION OF THE INVENTION

【0001】 [0001]

【発明の属する技術分野】本発明は、例えばAC入力を整流したDCで駆動されるパーソナルコンピュータの電源等に使用して好適な電源装置に関するものである。 The present invention relates to relates to a suitable power supply, for example, using an AC input to a power supply or the like of a personal computer driven by rectified DC.

【0002】 [0002]

【従来の技術】例えばAC入力を整流したDCで駆動されるパーソナルコンピュータの電源においては、内部で必要な駆動電圧を得るために、いわゆるDC−DCコンバータ等の電源装置が用いられている。 In the power supply BACKGROUND OF THE INVENTION Personal computers driven by DC rectified, for example AC input, in order to obtain the necessary driving voltage within the so-called DC-DC converter power supply or the like is used. すなわち図9には、そのような電源装置の一例の構成を示す。 That is, FIG. 9 shows an example of the configuration of such a power supply.

【0003】この図9において、DC70の+端が、直列に接続された2石のスイッチングトランジスタ71、 [0003] In FIG. 9, + end of DC70 is a 2 stone connected in series switching transistor 71,
72のコレクタ・エミッタ間を通じてDC70の−端に接続される。 72 collector-emitter through DC70 of - is connected to an end. これらのトランジスタ71、72の中点が過飽和リアクタトランス73のコイル3A、共振コンデンサ74を通じて電圧変換トランス75の1次側コイル5Aの一端に接続される。 Midpoint of these transistors 71 and 72 coils 3A supersaturation reactor transformer 73 is connected to one end of the primary coil 5A of the voltage conversion transformer 75 through the resonance capacitor 74. またこの1次側コイル5Aの他端がDC70の−端に接続される。 The other end of the primary coil 5A is DC70 of - is connected to an end. さらにトランジスタ71、72の中点がコンデンサ76を通じてDC70 Furthermore, the midpoint of the transistors 71 and 72 through the capacitor 76 DC70
の−端に接続される。 Bruno - is connected to an end.

【0004】また、トランジスタ71のコレクタが抵抗器77を通じてトランジスタ71のベースに接続され、 [0004] The collector of the transistor 71 is connected to the base of the transistor 71 via a resistor 77,
このトランジスタ71のベースが順方向のツェナーダイオード78と逆方向のダイオード79の直列回路を通じてトランジスタ71のエミッタに接続される。 The base of the transistor 71 is connected to the emitter of the transistor 71 via a series circuit of a forward Zener diode 78 and the reverse direction of the diode 79. さらにトランジスタ71のベースが抵抗器80、コンデンサ81 Further base resistor 80 of a transistor 71, a capacitor 81
と、過飽和リアクタトランス73のコイル3B及びコンデンサ82の並列回路との直列回路を通じてトランジスタ71のエミッタに接続される。 When, it is connected to the emitter of the transistor 71 via a series circuit of a parallel circuit of a coil 3B and the capacitor 82 of the supersaturated reactor transformer 73.

【0005】さらにトランジスタ72のコレクタが抵抗器83を通じてトランジスタ72のベースに接続され、 [0005] further the collector of the transistor 72 is connected to the base of the transistor 72 via a resistor 83,
このトランジスタ72のベースが順方向のツェナーダイオード84と逆方向のダイオード85の直列回路を通じてトランジスタ72のエミッタに接続される。 The base of the transistor 72 is connected to the emitter of the transistor 72 via a series circuit of the reverse direction of the diode 85 and forward of the Zener diode 84. さらにトランジスタ72のベースが抵抗器86、コンデンサ87 Base resistor 86 further transistor 72, a capacitor 87
と、過飽和リアクタトランス73のコイル3C及びコンデンサ88の並列回路との直列回路を通じてトランジスタ72のエミッタに接続される。 When, it is connected to the emitter of the transistor 72 via a series circuit of a parallel circuit of a coil 3C and the capacitor 88 of the supersaturated reactor transformer 73.

【0006】また、上述の電圧変換トランス75の2次側コイル5Bの一端及び他端が、それぞれ整流用の順方向のダイオード89、90を通じて互いに接続される。 [0006] One end and the other end of the secondary coil 5B voltage conversion transformer 75 described above, are connected to each other through a forward diode 89 and 90, respectively for rectification.
さらにこの接続点と2次側コイル5Bの中間タップとの間に平滑用のコンデンサ91が接続される。 Capacitor 91 for smoothing is connected between the further intermediate tap of the connection point and the secondary side coil 5B. そしてこのコンデンサ91の両端から出力端子92の+端及び−端が導出される。 The + end and the output terminal 92 from both ends of the capacitor 91 - end is derived. さらにこの出力端子92の+端がエラーアンプ93を通じて過飽和リアクタトランス73の制御コイル3Dに接続される。 Furthermore + end of this output terminal 92 is connected to the control coil 3D of supersaturation reactor transformer 73 through the error amplifier 93.

【0007】そしてこの装置において、上述のスイッチングトランジスタ71、72が自励発振によって交互にオンオフされることによって、電圧変換トランス75の1次側コイル5Aには略正弦波の電流が流され、2次側コイル5Bには所望の電圧が取り出される。 [0007] Then, in this apparatus, by switching transistors 71 and 72 described above is alternately turned on and off by the self-oscillation, substantially sinusoidal current is applied to the primary side coil 5A of the voltage conversion transformer 75, 2 the next coil 5B desired voltage is taken out. さらにこの取り出された電圧がダイオード89、90を通じて両波整流され、整流された電圧がコンデンサ91で平滑されて出力端子92に取り出される。 Furthermore the retrieved voltage is full-wave rectified through the diode 89 and 90, rectified voltage is obtained from an output terminal 92 is smoothed by a capacitor 91.

【0008】また、出力端子92の+端に取り出された電圧の、所望の電圧からの変動分がエラーアンプ93で検出され、この変動分が過飽和リアクタトランス73の制御コイル3Dに供給される。 Further, the voltage taken out to + end of the output terminal 92, the variation from the desired voltage is detected by the error amplifier 93, the variation is supplied to the control coil 3D of supersaturation reactor transformer 73. これによってこの過飽和リアクタトランス73のコイル3A〜3Cに取り出される信号の波形が変化され、トランジスタ71、72のスイッチング周波数が変化されて、出力端子92の+端に取り出される電圧が所望の電圧に等しくなるように制御が行われる。 This waveform of the signal taken out to the coil 3A~3C the supersaturated reactor transformer 73 is changed, is changed switching frequency of the transistors 71 and 72, the voltage is taken out to the + end of the output terminal 92 is equal to the desired voltage control is performed in such a way that.

【0009】このようにして、上述の装置において、安定化された所望の電圧を出力端子92に取り出すことができる。 [0009] Thus, in the apparatus described above, it is possible to retrieve a desired regulated voltage to an output terminal 92. そしてこの取り出された電圧は、例えばDCで駆動されるパーソナルコンピュータの電源として使用されるものである。 And this retrieved voltage, for example is used as a power source of the personal computer is driven by the DC.

【0010】 [0010]

【発明が解決しようとする課題】ところが上述の電源装置において、電圧変換トランス75の2次側整流用のダイオード89、90の順方向降下電圧Vf によって損失が発生する。 [SUMMARY OF THE INVENTION However in the power supply apparatus, loss caused by the forward voltage drop Vf of the diode 89 and 90 for the secondary side rectifying the voltage conversion transformer 75. すなわちこのようなダイオードの順方向降下電圧Vf は、一般的0.45V程度であるが、この順方向降下電圧Vf によって上述の装置では、 1.11×Io ×Vf 〔W〕 (但し、Io は出力電流〔A〕) の損失が発生する。 That forward voltage drop Vf of such diode is a common 0.45V approximately, in the apparatus described above by the forward voltage drop Vf is 1.11 × Io × Vf [W] (however, Io loss of output current [a]) is generated.

【0011】そしてこのような2次側整流用のダイオード89、90による損失が、例えば出力電流Io が10 [0011] The loss due to diode 89, 90 in such a secondary side rectifier, for example, the output current Io 10
〔A〕では5〔W〕、20〔A〕では10〔W〕にもなってしまい、特にパーソナルコンピュータのように低電圧、大電流が要求される電源では、出力に対する損失の割合が大きくなってしまうものである。 [A] in 5 [W], 20 become in the [A] 10 [W], a low voltage as in particular personal computers, the power supply a large current is required, increased percentage of loss to output and those would.

【0012】この出願はこのような点に鑑みて成されたものであって、解決しようとする問題点は、従来の装置では、特にパーソナルコンピュータのように低電圧、大電流の電源が要求される場合に、2次側整流用ダイオードの順方向降下電圧によって、出力に対する損失の割合が大きくなってしまうというものである。 [0012] be one This application has been made in view of the above problems, problem to be solved is that, in the conventional apparatus, particularly a low voltage as a personal computer, the request source a large current If that, the forward voltage drop of the secondary-side rectifier diode, is that the ratio of the loss to the output increases.

【0013】 [0013]

【課題を解決するための手段】このため本発明においては、電圧変換用トランスの2次側整流としてMOS−F Means for Solving the Problems] In the present invention for this, MOS-F as the secondary side rectifying the voltage conversion transformer
ETを用いて同期整流を行うようにしたものであって、 It is those which to perform synchronous rectification with ET,
これによれば、特に低オン抵抗のMOS−FETを用いることで、2次側整流での損失を大幅に減少させることができる。 According to this, in particular by using a low on-resistance MOS-FET, it is possible to greatly reduce the loss in the secondary side rectification.

【0014】 [0014]

【発明の実施の形態】すなわち本発明においては、スイッチング素子を2石用いたハーフブリッジ構成を有し、 In DETAILED DESCRIPTION OF THE INVENTION Namely, the present invention has a half-bridge configuration using a switching element 2 stone,
2石のスイッチング素子の中点に共振コンデンサと電圧変換用トランスが設けられると共に、電圧変換用トランスの2次側整流としてMOS−FETを用いて同期整流を行うものである。 Resonant capacitor and voltage converting transformer with provided the midpoint of the switching elements 2 stone, and performs synchronous rectification using the MOS-FET as the secondary side rectifying the voltage conversion transformer. 以下、図面を参照して本発明を説明するに、図1は本発明を適用した電源装置の一例の構成を示すブロック図である。 Hereinafter, to explain the invention with reference to the drawings, FIG. 1 is a block diagram showing an example of the configuration of a power supply device according to the present invention.

【0015】この図1において、AC入力を整流したD [0015] In FIG. 1, D obtained by rectifying the AC input
C100の+端が、直列に接続された2石のスイッチングトランジスタ1、2のコレクタ・エミッタ間を通じてDC100の−端に接続される。 C100 of + end, through the collector-emitter of the switching transistor 1 of 2 stone connected in series DC100 of - is connected to an end. これらのトランジスタ1、2の中点が過飽和リアクタトランス3のコイル3 Coil 3 midpoint of the transistors 1 and 2 supersaturated reactor transformer 3
A、共振コンデンサ4を通じて電圧変換トランス5の1 A, 1 of the voltage conversion transformer 5 through the resonant capacitor 4
次側コイル5Aの一端に接続される。 It is connected to one end of the next coil 5A. またこの1次側コイル5Aの他端がDC100の−端に接続される。 The other end of the primary coil 5A is DC100 of - is connected to an end. さらにトランジスタ1、2の中点がコンデンサ6を通じてD D through capacitor 6 further midpoint of the transistor 1 and 2
C100の−端に接続される。 C100 of - is connected to an end.

【0016】また、トランジスタ1のコレクタが抵抗器7を通じてトランジスタ1のベースに接続され、このトランジスタ1のベースが順方向のツェナーダイオード8 [0016] The collector of the transistor 1 is connected to the base of the transistor 1 via a resistor 7, the base of the transistor 1 is forward Zener diode 8
と逆方向のダイオード9の直列回路を通じてトランジスタ1のエミッタに接続される。 It is connected to the emitter of the transistor 1 via the series circuit of the reverse direction of the diode 9 and. さらにトランジスタ1のベースが抵抗器10、コンデンサ11と、過飽和リアクタトランス3のコイル3B及びコンデンサ12の並列回路との直列回路を通じてトランジスタ1のエミッタに接続される。 Further base resistor 10 of the transistor 1, a capacitor 11, is connected to the emitter of the transistor 1 via the series circuit of the parallel circuit of the coil 3B and the capacitor 12 of the supersaturated reactor transformer 3.

【0017】さらにトランジスタ2のコレクタが抵抗器13を通じてトランジスタ2のベースに接続され、このトランジスタ2のベースが順方向のツェナーダイオード14と逆方向のダイオード15の直列回路を通じてトランジスタ2のエミッタに接続される。 The further the collector of the transistor 2 is connected to the base of the transistor 2 via a resistor 13, the base of the transistor 2 is connected to the emitter of the transistor 2 through the series circuit of the forward of the Zener diode 14 and the reverse direction of the diode 15 that. さらにトランジスタ2のベースが抵抗器16、コンデンサ17と、過飽和リアクタトランス3のコイル3C及びコンデンサ18の並列回路との直列回路を通じてトランジスタ2のエミッタに接続される。 Base resistor 16 further transistor 2, a capacitor 17, is connected to the emitter of the transistor 2 through the series circuit of the parallel circuit of supersaturation reactor transformer third coil 3C and a capacitor 18.

【0018】また、上述の電圧変換トランス5の2次側コイル5Bの一端及び他端が、それぞれNチャンネルのMOS−FET19、20のソース・ドレイン間を通じて互いに接続される。 [0018] One end and the other end of the secondary coil 5B voltage conversion transformer 5 described above, are connected to each other through between the source and the drain of the MOS-FET19,20 of N channels, respectively. さらにこの接続点と2次側コイル5Bの中間タップとの間に平滑用のコンデンサ21が接続される。 Capacitor 21 for smoothing is connected between the further intermediate tap of the connection point and the secondary side coil 5B. そしてこのコンデンサ21の両端から出力端子22の+端及び−端が導出される。 The + end and the output terminal 22 from both ends of the capacitor 21 - end is derived. さらにこの出力端子22の+端が制御回路23を通じて過飽和リアクタトランス3の制御コイル3Dに接続される。 Furthermore + end of the output terminal 22 is connected to the control coil 3D of supersaturation reactor transformer 3 through the control circuit 23.

【0019】そしてこの装置において、上述のスイッチングトランジスタ1、2が自励発振によって交互にオンオフされることによって、電圧変換トランス5の1次側コイル5Aには略正弦波の電流が流され、2次側コイル5Bには所望の電圧が取り出される。 In [0019] Then the device, by the switching transistors 1 and 2 described above are alternately turned on and off by the self-oscillation, substantially sinusoidal current is applied to the primary side coil 5A of the voltage conversion transformer 5, 2 the next coil 5B desired voltage is taken out. さらにこの取り出された電圧が、MOS−FET19、20を通じて互いに接続される。 Furthermore the retrieved voltage, are connected to each other via MOS-FET19,20.

【0020】ここでこれらのMOS−FET19、20 [0020] Here, of these MOS-FET19,20
はそれぞれ駆動回路24、25によってオンオフが制御され、例えば図示の例ではコンデンサ21側からコイル5Bに向かって電流が流れている期間にのみオンされるように同期制御される。 Are on-off by respective drive circuits 24 and 25 control, for example, in the illustrated example are synchronized controlled as turned only during a period in which the current flows from the capacitor 21 side coil 5B. これによって2次側コイル5B This secondary coil 5B
に取り出された電圧が両波整流され、整流された電圧がコンデンサ21で平滑されて出力端子22に取り出される。 Voltage taken is full-wave rectified, the rectified voltage is obtained from an output terminal 22 is smoothed by the capacitor 21.

【0021】また、出力端子22の+端に取り出された電圧の、所望の電圧からの変動分が制御回路23で検出され、この変動分が過飽和リアクタトランス3の制御コイル3Dに供給される。 Further, the voltage taken out to + end of the output terminal 22, variation from the desired voltage is detected by the control circuit 23, the variation is supplied to the control coil 3D of supersaturation reactor transformer 3. これによってこの過飽和リアクタトランス3のコイル3A〜3Cに取り出される信号の波形が変化され、トランジスタ1、2のスイッチング周波数が変化されて、出力端子22の+端に取り出される電圧が所望の電圧に等しくなるように制御が行われる。 This waveform of the signal taken out to the coil 3A~3C the supersaturated reactor transformer 3 is changed, is changed switching frequency of the transistors 1 and 2, the voltage is taken out to the + end of the output terminal 22 is equal to the desired voltage control is performed in such a way that.

【0022】このようにして、上述の装置において、安定化された所望の電圧を出力端子22に取り出すことができる。 [0022] Thus, in the apparatus described above, it is possible to retrieve a desired regulated voltage to an output terminal 22. さらにこの取り出された電圧は、例えばDCで駆動されるパーソナルコンピュータの電源として使用されるものである。 Furthermore the retrieved voltage, for example is used as a power source of the personal computer is driven by the DC.

【0023】そして上述の装置において、電圧変換トランス5の2次側の整流が、MOS−FET19、20のそれぞれ同期制御による同期整流によって行われている。 [0023] Then, in the apparatus described above, the rectification of the secondary side of the voltage conversion transformer 5, has been performed by the synchronous rectification by each synchronization control MOS-FET19,20. 従ってこの場合には、2次側整流用のMOS−FE Therefore, in this case, MOS-FE for the secondary side rectifier
T19、20のオン抵抗Ronによって損失が発生する。 Loss occurs by T19,20 the on-resistance Ron.

【0024】すなわちこのようなオン抵抗Ronは、例えば低オン抵抗のMOS−FETでは7mΩ程度である。 [0024] That such on-resistance Ron is, for example, about 7mΩ the MOS-FET of the low on-resistance.
そしてこのオン抵抗Ronによって上述の装置では、 1.11×Io ×1.11×Io ×Ron〔W〕 の損失が発生する。 And this on-resistance Ron in the above apparatus, the loss of 1.11 × Io × 1.11 × Io × Ron [W] is generated.

【0025】そしてこのような2次側整流用のMOS− [0025] and of such secondary side rectification MOS-
FET19、20による損失は、例えば出力電流Io が10〔A〕では約0.86〔W〕、20〔A〕では約3.45〔W〕に留めることができ、特にパーソナルコンピュータのように低電圧、大電流が要求される電源で、出力に対する損失の割合を大幅に削減することができるものである。 Loss due FET19,20, for example the output current Io is 10 [A] at about 0.86 [W], 20 it can be kept to [A] in about 3.45 [W], low in particular as a personal computer voltage, in which the power supply of a large current is required, the ratio of loss to the output can be significantly reduced.

【0026】すなわち図2において、直線Aは、従来の2次側整流用の素子に例えば順方向降下電圧Vf =0. [0026] That is, in FIG. 2, the straight line A, for example the elements of the conventional secondary rectifier forward voltage drop Vf = 0.
45Vのダイオードを用いた場合の、電流〔A〕に対する損失〔W〕の発生の状況を示す。 When using a 45V diode shows the status of occurrence of loss [W] for the current [A]. また、曲線Bは、2 In addition, the curve B, 2
次側整流用の素子に例えばオン抵抗Ron=7mΩのMO MO follows side element, for example, the ON resistance Ron = 7 m for rectification
S−FETを用いた場合の、電流〔A〕に対する損失〔W〕の発生の状況を示している。 In the case of using the S-FET, it shows the situation of the occurrence of loss [W] for the current [A].

【0027】従ってこの装置において、電圧変換用トランスの2次側整流としてMOS−FETを用いて同期整流を行うことによって、特に低オン抵抗のMOS−FE [0027] Therefore, in this apparatus, by performing synchronous rectification using the MOS-FET as the secondary side rectifying the voltage converting transformer, in particular a low on-resistance MOS-FE
Tを用いることで、2次側整流での損失を大幅に減少させることができる。 By using T, it is possible to greatly reduce the loss in the secondary side rectification.

【0028】これによって、従来の装置では、2次側整流用ダイオードの順方向降下電圧によって、出力に対する損失の割合が大きくなっていたものを、本発明によれば、特にパーソナルコンピュータのように低電圧、大電流の電源が要求される場合に、2次側整流での損失を大幅に減少させ、効率の良いスイッチング電源を実現することができるものである。 [0028] Thus, in the conventional device, the forward voltage drop of the secondary side rectifying diode, what percentage of the loss to the output was increased, according to the present invention, low in particular as a personal computer voltage, when the power supply of a large current is required, significantly reducing the loss in the secondary side rectification, in which it is possible to realize a switching power supply efficiency.

【0029】ところで上述の装置において、2次側整流素子は、本来は電圧変換用トランス5の2次側コイル5 By the way in the apparatus described above, the secondary side rectifying element is originally a secondary coil 5 of the voltage conversion transformer 5
Bから平滑用コンデンサ21を充電する方向のみに電流を流さなければならない。 Shall only current flows in a direction to charge the smoothing capacitor 21 from B. ところが上述の装置において、MOS−FETは、ゲートにオン電圧が印加されるとドレイン・ソース間は抵抗体と同等になるため、電流は双方向に流れることができる。 However in the apparatus described above, MOS-FET, since the ON voltage to the gate is applied between the drain and the source becomes equal to the resistor, a current can flow bidirectionally.

【0030】従って上述の装置において、MOS−FE [0030] Thus, in the apparatus described above, MOS-FE
Tのゲートにオン電圧を印加するタイミングを悪くすると、コンデンサ21から2次側コイル5Bへ放電電流が流れ、負荷側にエネルギーを有効に伝達できないばかりか、逆電流によるMOS−FETの発熱やノイズの発生、1次側スイッチング損失の増大にもつながる恐れがある。 With bad timing of applying the ON voltage to the gate T, then from the capacitor 21 to the secondary side coil 5B discharge current flows, not only can not effectively transfer energy to the load side, the heat generation and noise MOS-FET according to the reverse current generation of, which may lead to an increase of the primary side switching losses.

【0031】そこで、このようなMOS−FETのゲートにオン電圧を印加するタイミングを正確に制御するために、例えば図3に示すような回路が用いられる。 [0031] Therefore, in order to accurately control the timing of applying the ON voltage to the gate of such a MOS-FET, for example, a circuit as shown in FIG. 3 is used. なお以下の説明では、2次側整流用のMOS−FET19、 In the following description, MOS-FET 19 for the secondary side rectifier,
20の下側の片方の回路についてのみ示すが、上下両方のMOS−FETについての回路構成、及びその作用動作は同じである。 Although shown only for the lower half of a circuit 20, the circuit configuration for both the upper and lower MOS-FET, and its action operation is the same.

【0032】この図3において、MOS−FET20に直列に電流検出用トランス31の1次側コイル31Aが設けられる。 [0032] In FIG. 3, the primary coil 31A of the current detecting transformer 31 is provided in series with the MOS-FET 20. そしてこの電流検出用トランス31の2次側コイル31Bの両端間に検出用の抵抗器32が接続され、この抵抗器32の電圧がコンパレータ33で検出される。 And this resistor 32 for detecting across the secondary coil 31B of the current detection transformer 31 is connected, the voltage of the resistor 32 is detected by the comparator 33.

【0033】すなわち上述の抵抗器32の一端が電圧源34に接続され、この電圧源34の電圧と抵抗器32の他端の電圧がコンパレータ33で比較されて、他端の電圧が所定値以上になったときに検出が行われる。 [0033] That end of the above-described resistor 32 is connected to the voltage source 34, the voltage and voltage at the other end of the resistor 32 of the voltage source 34 is compared by the comparator 33, the voltage of the other end than the predetermined value detection is carried out when it is. そしてこの検出信号がバッファ回路35を通じてMOS−FE The MOS-FE detection signal through a buffer circuit 35
T20のゲートに供給される。 It is supplied to the gate of T20.

【0034】従ってこの回路において、例えば上述の1 [0034] Accordingly, in this circuit, for example, the above 1
次側のトランジスタ1のコレクタ電流I Cが、図4のA The collector current I C of the transistor 1 of the following side, A of FIG. 4
に示すようであった場合には、電圧変換用トランス5の2次側コイル5Bには図4のBの電圧が誘起される。 If was as shown in, the secondary side coil 5B voltage conversion transformer 5 voltage B of Figure 4 is induced. そしてこの電圧がコンデンサ21の充電電圧より大きくなると、MOS−FET20の寄生ダイオード20Aを通じてコンデンサ21に充電電流が流される。 When this voltage becomes larger than the charging voltage of the capacitor 21, charging current flows to the capacitor 21 through the parasitic diode 20A of MOS-FET 20.

【0035】さらにこの充電電流が電流検出用トランス31の1次側コイル31Aを流れることによって、2次側コイル31Bには電圧が誘起される。 Furthermore by this charging current flowing through the primary coil 31A of the current detecting transformer 31, the secondary side coil 31B a voltage is induced. そしてこの出力電圧がコンパレータ33で検出され、この出力電圧が所定値以上になると、即座にバッファ回路35を通じて例えば図4のCに示すようなゲート電圧VgsがMOS−F And this output voltage is detected by the comparator 33, when the output voltage becomes equal to or greater than a predetermined value, the gate voltage as immediately shown in C of example FIG. 4 through the buffer circuit 35 Vgs is MOS-F
ET20に印加される。 It is applied to the ET20.

【0036】また、上述の充電電流が減少すると、コンパレータ33の出力が反転され、バッファ回路35を通じてMOS−FET20のゲート容量が放電されて、M Further, the charging current described above is decreased, the output of the comparator 33 is inverted, and is discharged the gate capacitance of the MOS-FET 20 is through the buffer circuit 35, M
OS−FET20がオフされる。 OS-FET20 is turned off. なおこの時点でコンデンサ21の充電電流はゼロにはなっていないが、この電流はMOS−FET20の寄生ダイオード20Aを通じて流される。 Note the charging current of the capacitor 21 at this point has not become zero, this current flows through the parasitic diode 20A of MOS-FET 20.

【0037】これによって、MOS−FET20には、 [0037] In this way, the MOS-FET20 is,
例えば図4のDに示すようなドレイン電流I Dが流される。 For example the drain current I D as shown in D of FIG. 4 is flowed. すなわちこのMOS−FET20は、コンデンサ2 That this MOS-FET 20, the capacitor 2
1への充電電流が流れ始めた後でオンされ、充電電流がゼロになる前にオフされる。 Is turned on after the charge current to 1 starts flowing, are turned off before the charging current becomes zero. そしてこのMOS−FET And this MOS-FET
20がオンされている期間に、低オン抵抗を介して損失の少ない充電が行われるものである。 The period 20 is turned on, in which a small charge loss through a low on-resistance is performed.

【0038】なお、上述のMOS−FET19においても作用動作は全く同じに行われる。 It should be noted, it is carried out in exactly the effects operate in MOS-FET 19 above the same. すなわち例えば図5 That example 5
のA、Bに示すMOS−FET20の動作に反転した形で、図5のC、Dに示すようにMOS−FET19の動作が行われる。 Of A, in the form of inverted operation of the MOS-FET 20 shown in B, the operation of the MOS-FET 19 is performed as shown C in FIG. 5, the D. そしてこの場合も、MOS−FET19 And even in this case, MOS-FET19
は、コンデンサ21への充電電流が流れ始めた後でオンされ、充電電流がゼロになる前にオフされるものである。 Is turned on after the charging current to the capacitor 21 begins to flow, is intended to be turned off before the charging current becomes zero.

【0039】従ってこの回路において、MOS−FET [0039] Thus, in this circuit, MOS-FET
は充電電流がゼロになる前にオフされるので、例えばターンオフのタイミングが遅れて逆電流が流されるようなことがない。 Since is turned off before the charging current becomes zero, there is no possibility for example that a delay in the timing of the turn-off reverse current flows. これにより、いかなる動作条件でもMOS MOS As a result, in any operating condition
−FETのオン期間が充電電流の方向のみの電流だけ流せるようにでき、逆電流の発生による不具合を解消することができる。 ON period of -FET can be so flown only current in only a direction of the charging current, it is possible to eliminate the inconvenience due to the occurrence of the reverse current.

【0040】さらに図6、図7は、MOS−FETのゲートにオン電圧を印加するタイミングを正確に制御するための回路の他の例を示す。 [0040] Further, FIG. 6, FIG. 7 shows another example of a circuit for accurately controlling the timing of applying the ON voltage to the gate of the MOS-FET. すなわち図6は充電電流の検出方法として検出抵抗41を用いる場合であって、この検出抵抗41で検出された電圧をコンパレータ42で電圧源43の電圧と比較し、この比較出力をバッファ回路44を通じてMOS−FET20のゲートに印加している。 That is, FIG. 6 is a case of using a detection resistor 41 as the detection method of the charging current, the detected voltage in this detection resistor 41 is compared with the voltage of the voltage source 43 by a comparator 42, via a buffer circuit 44 to the comparison output It is applied to the gate of the MOS-FET20.

【0041】また、図7は検出抵抗としてMOS−FE [0041] In addition, MOS-FE as 7 is the detection resistor
T20のオン抵抗を用いるものである。 It is to use the on-resistance of T20. すなわちこの例では、MOS−FET20のオン抵抗で検出された電圧をコンパレータ51で電圧源52の電圧と比較し、この比較出力をバッファ回路53を通じてMOS−FET2 That is, in this example, the voltage detected by the on-resistance of MOS-FET 20 is compared with the voltage of the voltage source 52 by a comparator 51, MOS-FET2 the comparison output through a buffer circuit 53
0のゲートに印加している。 It is applied to the 0 of the gate. なおこの図7の回路は、もっとも損失が少なくなる構成である。 Incidentally circuit of FIG. 7 is a configuration in which most loss is reduced.

【0042】こうして上述の電源装置によれば、スイッチング素子を2石用いたハーフブリッジ構成を有し、2 [0042] Thus, according to the power supply apparatus, comprising a half-bridge configuration using a switching element 2 stone, 2
石のスイッチング素子の中点に共振コンデンサと電圧変換用トランスが設けられると共に、電圧変換用トランスの2次側整流としてMOS−FETを用いて同期整流を行うことにより、2次側整流での損失を大幅に減少させ、効率の良いスイッチング電源を実現することができるものである。 With midpoint resonant capacitor voltage conversion transformer switching elements of the stone are provided, by performing synchronous rectification using the MOS-FET as the secondary side rectifying the voltage converting transformer, loss on the secondary side rectification greatly reduces, in which it is possible to realize a switching power supply efficiency.

【0043】なお、上述の説明では、いずれも2次側整流用のMOS−FET19、20を電圧変換トランス5 [0043] In the above description, both the voltage converting the MOS-FET19,20 for the secondary side rectifier transformer 5
の2次側コイル5Bの−側に設ける場合について行ったが、例えば従来の装置で述べたダイオードのように+側に設けても同様の作用効果を得ることができる。 Of the secondary side coil 5B - has been performed in the case of providing the side, for example, it is possible to obtain the same effect be provided on the positive side as the diode described in the conventional device. ただし、−側に設けた方がMOS−FETの駆動には適正である。 However, - those who provided on the side is appropriate to drive the MOS-FET.

【0044】また、例えば図8に示すように1次側のスイッチング素子が他励発振によってオンオフ駆動される場合においても本発明を適用することができる。 [0044] Further, it is also possible to apply the present invention in the case where for example the switching element on the primary side as shown in FIG. 8 is driven to turn on and off by a separate excitation oscillation. すなわち図8においては、コントロール回路60からの制御信号がドライブ回路61、62を通じてそれぞれスイッチング素子63、64に供給され、これらのスイッチング素子63、64がオンオフ駆動されて、上述の電圧変換トランス5の1次側コイル5Aに略正弦波の電流が流される。 That is, in FIG. 8 are respectively supplied to the switching elements 63 and 64 control signals from the control circuit 60 through the drive circuit 61, the switching elements 63 and 64 are driven to turn on and off, the voltage conversion transformer 5 described above substantially sinusoidal current flows to the primary coil 5A.

【0045】さらにこの装置において、出力端子22の+端に取り出された電圧の、所望の電圧からの変動分がフィードバック回路65を通じてコントロール回路60 [0045] Further in this device, the voltage taken out to + end of the output terminal 22, the control circuit through the variation feedback circuit 65 from the desired voltage 60
に供給され、これによってスイッチング素子63、64 It is supplied to, thereby switching element 63 and 64
のスイッチング周波数が変化されて、出力端子22の+ Switching frequency is changed, the output terminal 22 of +
端に取り出される電圧が所望の電圧に等しくなるように制御が行われる。 Control is performed so that the voltage to be taken out to the edge is equal to the desired voltage.

【0046】そしてさらにこの装置においても、電圧変換用トランスの2次側整流としてMOS−FETを用いて同期整流を行うことによって、特に低オン抵抗のMO [0046] and further also in this apparatus, by performing synchronous rectification using the MOS-FET as the secondary side rectifying the voltage converting transformer, in particular a low on-resistance MO
S−FETを用いることで、2次側整流での損失を大幅に減少させることができ、効率の良いスイッチング電源を実現することができるものである。 The use of S-FET, a loss in the secondary side rectification can be greatly reduced, in which it is possible to realize a switching power supply efficiency.

【0047】 [0047]

【発明の効果】この発明によれば、電圧変換用トランスの2次側整流としてMOS−FETを用いて同期整流を行うことによって、特に低オン抵抗のMOS−FETを用いることで、2次側整流での損失を大幅に減少させることができるようになった。 Effects of the Invention According to the present invention, by performing synchronous rectification using the MOS-FET as the secondary side rectifying the voltage converting transformer, by particularly using a MOS-FET of the low on-resistance, the secondary side began to losses in the rectifier can be greatly reduced.

【0048】これによって、従来の装置では、2次側整流用ダイオードの順方向降下電圧によって、出力に対する損失の割合が大きくなっていたものを、本発明によれば、特にパーソナルコンピュータのように低電圧、大電流の電源が要求される場合に、2次側整流での損失を大幅に減少させ、効率の良いスイッチング電源を実現することができるものである。 [0048] Thus, in the conventional device, the forward voltage drop of the secondary side rectifying diode, what percentage of the loss to the output was increased, according to the present invention, low in particular as a personal computer voltage, when the power supply of a large current is required, significantly reducing the loss in the secondary side rectification, in which it is possible to realize a switching power supply efficiency.

【図面の簡単な説明】 BRIEF DESCRIPTION OF THE DRAWINGS

【図1】本発明の適用される電源装置の一例の構成図である。 1 is a configuration diagram of an example of the applied power supply of the present invention.

【図2】その説明のための図である。 FIG. 2 is a diagram for the explanation.

【図3】本発明の適用される電源装置の要部の一例の構成図である。 3 is a configuration diagram of an example of a main portion of the applied power supply of the present invention.

【図4】その動作の説明のための図である。 4 is a diagram for explaining the operation thereof.

【図5】その動作の説明のための図である。 FIG. 5 is a diagram for explaining the operation thereof.

【図6】本発明の適用される電源装置の要部の他の例の構成図である。 6 is a block diagram of another example of the main part of the applied power supply of the present invention.

【図7】本発明の適用される電源装置の要部の他の例の構成図である。 7 is a block diagram of another example of the main part of the applied power supply of the present invention.

【図8】本発明の適用される電源装置の他の例の構成図である。 8 is a configuration diagram of another example of the applied power supply of the present invention.

【図9】従来の電源装置の構成図である。 9 is a configuration diagram of a conventional power supply device.

【符号の説明】 DESCRIPTION OF SYMBOLS

100 AC入力を整流したDC、1,2 スイッチングトランジスタ、3過飽和リアクタトランス、4 共振コンデンサ、5 電圧変換トランス、6 コンデンサ、 DC rectified the 100 AC input, 1,2 switching transistor 3 supersaturation reactor transformer, 4 resonant capacitor, fifth voltage conversion transformer, 6 a capacitor,
7 抵抗器、8 ツェナーダイオード、9 ダイオード、10 抵抗器、11,12 コンデンサ、13 抵抗器、14 ツェナーダイオード、15ダイオード、1 7 resistors, 8 Zener diode, 9 a diode, 10 a resistor, 11, 12 condenser, 13 a resistor, 14 Zener diode, 15 a diode, 1
6 抵抗器、17,18 コンデンサ、19,20 M 6 resistors, 17 and 18 capacitors, 19, 20 M
OS−FET、21 コンデンサ、22 出力端子、2 OS-FET, 21 capacitors, 22 output terminals, 2
3 制御回路、24,25 駆動回路 3 control circuit, 24 and 25 drive circuit

Claims (5)

    【特許請求の範囲】 [The claims]
  1. 【請求項1】 スイッチング素子を2石用いたハーフブリッジ構成を有し、 上記2石のスイッチング素子の中点に共振コンデンサと電圧変換用トランスが設けられると共に、 上記電圧変換用トランスの2次側整流としてMOS−F [Claim 1, further comprising a half-bridge configuration using a switching element 2 stone, with the midpoint on the resonant capacitor voltage conversion transformer of the switching elements 2 stone above is provided, the secondary side of the voltage conversion transformer as the rectifying MOS-F
    ETを用いて同期整流を行うことを特徴とする電源装置。 Power supply and performs a synchronous rectification with ET.
  2. 【請求項2】 請求項1記載の電源装置において、 上記2次側整流用のMOS−FETの駆動信号として上記MOS−FETを流れる電流を検出した信号を用いることを特徴とする電源装置。 2. A power supply device according to claim 1, the power supply apparatus characterized by using a signal obtained by detecting a current flowing through the MOS-FET as a drive signal of MOS-FET for the secondary side rectifier.
  3. 【請求項3】 請求項2記載の電源装置において、 上記MOS−FETに直列に電流検出トランスを接続して上記MOS−FETを流れる電流を検出することを特徴とする電源装置。 3. A power supply apparatus according to claim 2, power supply unit and detecting a current flowing through the MOS-FET connected to the current detection transformer in series with the MOS-FET.
  4. 【請求項4】 請求項2記載の電源装置において、 上記MOS−FETに直列に電流検出抵抗を接続してその電圧降下により上記MOS−FETを流れる電流を検出することを特徴とする電源装置。 4. A power supply apparatus according to claim 2, power supply unit and detecting a current flowing through the MOS-FET by the voltage drop by connecting a current detecting resistor in series with the MOS-FET.
  5. 【請求項5】 請求項2記載の電源装置において、 上記MOS−FETのオン抵抗による電圧降下により上記MOS−FETを流れる電流を検出することを特徴とする電源装置。 5. A power supply apparatus according to claim 2, power supply unit and detecting a current flowing through the MOS-FET by a voltage drop due to the on resistance of the MOS-FET.
JP31504996A 1996-11-26 1996-11-26 Power supply Pending JPH10164837A (en)

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