JP4137454B2 - Light emitting device, electronic device, and method for manufacturing light emitting device - Google Patents

Light emitting device, electronic device, and method for manufacturing light emitting device Download PDF

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JP4137454B2
JP4137454B2 JP2002008184A JP2002008184A JP4137454B2 JP 4137454 B2 JP4137454 B2 JP 4137454B2 JP 2002008184 A JP2002008184 A JP 2002008184A JP 2002008184 A JP2002008184 A JP 2002008184A JP 4137454 B2 JP4137454 B2 JP 4137454B2
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insulating film
formed
emitting device
film
electrode
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JP2002311857A5 (en
JP2002311857A (en
Inventor
潤 小山
舜平 山崎
宗広 浅見
達也 荒尾
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株式会社半導体エネルギー研究所
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Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to an OLED panel in which an OLED formed on a substrate is enclosed between the substrate and a sealing material. The present invention also relates to an OLED module in which an IC is mounted on the OLED panel. In this specification, the OLED panel and the OLED module are collectively referred to as a light emitting device. The present invention further relates to an electronic apparatus using the light emitting device.
[0002]
[Prior art]
The OLED emits light by itself and has high visibility, is not required for a backlight necessary for a liquid crystal display device (LCD), is optimal for thinning, and has no restriction on the viewing angle. Therefore, in recent years, light emitting devices using OLEDs (Organic Light Emitting Diodes) have attracted attention as display devices that replace CRTs and LCDs.
[0003]
The OLED has a layer containing an organic compound (hereinafter, referred to as an organic light emitting layer) from which luminescence generated by applying an electric field is obtained, an anode layer, and a cathode layer. Luminescence in an organic compound includes light emission (fluorescence) when returning from the singlet excited state to the ground state and light emission (phosphorescence) when returning from the triplet excited state to the ground state. In the light emitting device of the present invention, , Fluorescence and / or phosphorescence can be used.
[0004]
In this specification, all layers provided between the anode and the cathode of the OLED are defined as organic light emitting layers. Specifically, the organic light emitting layer includes a light emitting layer, a hole injection layer, an electron injection layer, a hole transport layer, an electron transport layer, and the like. Basically, the OLED has a structure in which an anode / light emitting layer / cathode is laminated in this order. In addition to this structure, the anode / hole injection layer / light emitting layer / cathode and the anode / hole injection layer / The light emitting layer / electron transport layer / cathode may be stacked in this order.
[0005]
Incidentally, as a driving method of a light emitting device having an OLED, there is a driving method called analog driving using an analog video signal (hereinafter referred to as an analog video signal).
[0006]
In analog driving, an analog video signal (analog video signal) is input to a gate electrode of a TFT (driving TFT) that controls a current flowing through the OLED. The magnitude of the drain current of the driving TFT is controlled by the potential of the analog video signal, and when the drain current flows to the OLED, the OLED emits light with a luminance corresponding to the magnitude of the current, and the gradation is Is displayed.
[0007]
The manner in which the amount of current supplied to the OLED is controlled by the gate voltage of the driving TFT in the analog driving described above will be described in detail with reference to FIG.
[0008]
FIG. 19 is a graph showing transistor characteristics of the driving TFT. DS -V GS Characteristic (or I DS -V GS Curve). Where I DS Is the drain current and V GS Is the voltage between the gate electrode and the source region (gate voltage). Also, V TH Is the threshold voltage and V∞ is V GS Means infinite. From this graph, the amount of current flowing for an arbitrary gate voltage can be known.
[0009]
I shown in FIG. DS -V GS According to the characteristics, the drain current is determined one-to-one with respect to the gate voltage. That is, a drain current is determined corresponding to the potential of the analog video signal input to the gate electrode of the driving TFT, the drain current flows to the OLED, and the OLED emits light with a luminance corresponding to the amount of the current.
[0010]
[Problems to be solved by the invention]
The voltage between the source region and the drain region is V DS Then, the transistor characteristics of the driving TFT shown in FIG. GS And V DS It is divided into two areas according to the value of. | V GS -V TH | <| V DS | Is the saturation region, | V GS -V TH | > | V DS A region that is | is a linear region.
[0011]
In the saturation region, the following formula 1 is established. Β = μC 0 W / L, μ is mobility, C 0 Is the gate capacitance per unit area, and W / L is the ratio of the channel width W to the channel length L of the channel formation region.
[0012]
[Formula 1]
I DS = Β (V GS -V TH ) 2 / 2
[0013]
As can be seen from Equation 1, the current value is V in the saturation region. DS Hardly changes by V GS The current value is determined only by this. Therefore, since it is relatively easy to control the gradation based on the potential of the analog signal, in general, in the analog drive, the driving TFT is operated mainly in the saturation region.
[0014]
However, in the saturation region, as is apparent from FIG. 19, the drain current changes exponentially with respect to the change in the gate voltage. Therefore, in the analog drive, when the gate voltage changes even a little due to leakage between the input of the analog video signal and the input of the next analog video signal, the drain current may change greatly. . When the change in drain current is large, the luminance of the OLED is also greatly changed accordingly. Therefore, depending on the frame frequency, there may be a problem that the screen appears to flicker.
[0015]
In order to avoid the above problem, it is important to reliably maintain the gate voltage. As a means for more reliably holding the gate voltage, a method of increasing the capacitance value of the holding capacitor can be considered. However, when the storage capacitor is increased, the aperture ratio is reduced, and the area where the pixel can actually emit light (effective light emission area) is reduced. Note that the effective light emission area refers to the area of a pixel electrode of the OLED in which the light emitted from the OLED is not obstructed by a TFT, wiring, or the like that does not transmit light, such as a TFT formed on the substrate.
[0016]
Particularly in recent years, there has been an increasing demand for high-definition images, and how to suppress a decrease in aperture ratio associated with high-definition pixels has become a problem. Therefore, it is not preferable to increase the area occupied by the storage capacitor in the pixel.
[0017]
The present invention has been made in view of the above problems, and an object of the present invention is to provide a light-emitting device that simultaneously suppresses a change in gate voltage due to leakage and the like and suppresses a decrease in aperture ratio.
[0018]
[Means for Solving the Problems]
In the present invention, in order to solve the above-described problem, a wiring (connection wiring) formed on the gate electrode and the active layer of the TFT included in the pixel and connected to the active layer, and formed on the connection wiring A storage capacitor was formed by the insulating film and a wiring (capacitive wiring) formed on the insulating film. Note that the capacitor wiring may be formed on the same interlayer insulating film together with the pixel electrode. In this case, the capacitor wiring and the pixel electrode may be formed from the same conductive film. Further, a power supply line may be used as a capacitor wiring.
[0019]
With the above structure, since the TFT and the storage capacitor can be formed to overlap each other, the capacitance value of the storage capacitor can be increased while suppressing a decrease in the aperture ratio. Accordingly, a change in gate voltage due to leakage or the like can be suppressed, so that a change in luminance of the OLED can be suppressed and a screen flicker can be suppressed in analog driving.
[0020]
Further, suppressing the decrease in the aperture ratio leads to suppressing the reduction of the effective light emission area of the pixel. The larger the effective light emitting area, the higher the luminance of the screen. Therefore, the power consumption can be suppressed by the configuration of the present invention.
[0021]
Note that the structure of the present invention can be used even in the case of digital driving.
[0022]
DETAILED DESCRIPTION OF THE INVENTION
The configuration of the present invention will be described below.
[0023]
In the light-emitting device of the present invention, a plurality of pixels are provided in a matrix in the pixel portion. A connection configuration of a TFT included in a pixel of the present invention will be described with reference to FIG.
[0024]
A region having one source line (S), one gate line (G), and one power supply line (V) corresponds to the pixel 100. Each pixel has a switching TFT 101, a driving TFT 102, an OLED 103, and a storage capacitor 104.
[0025]
The gate electrode of the switching TFT 101 is connected to the gate line (G). One of the source region and the drain region of the switching TFT 101 is connected to the source line (S), and the other is connected to the gate electrode of the driving TFT 102.
[0026]
One of the source region and the drain region of the driving TFT is connected to the power supply line (V), and the other is connected to the pixel electrode of the OLED 103. In addition, when using the anode of OLED103 as a pixel electrode, a cathode is called a counter electrode. Conversely, when the cathode of the OLED 103 is used as a pixel electrode, the anode is called a counter electrode.
[0027]
Note that the switching TFT 101 may be either a p-channel TFT or an n-channel TFT. The driving TFT 102 may be either a p-channel TFT or an n-channel TFT. However, when the anode is used as the pixel electrode, the driving TFT is preferably a p-channel TFT. Conversely, when the cathode is used as the pixel electrode, the driving TFT is preferably an n-channel TFT.
[0028]
Of the two electrodes of the storage capacitor, one is electrically connected to the gate electrode of the driving TFT 102 and the other is electrically connected to the power supply line (V).
[0029]
Next, a specific structure of the storage capacitor in the light-emitting device of the present invention will be described with reference to FIG. Reference numeral 101 denotes a switching TFT, and reference numeral 102 denotes a driving TFT, which are formed on an insulating surface.
[0030]
The active layer 130 of the switching TFT 101 has impurity regions 110 and 111 that function as a source region or a drain region. A gate electrode 114 is formed on the active layer 130 with the gate insulating film 116 interposed therebetween.
[0031]
The active layer 131 of the driving TFT 102 includes impurity regions 112 and 113 that function as a source region or a drain region. A gate electrode 115 is formed on the active layer 131 with the gate insulating film 116 interposed therebetween.
[0032]
A first interlayer insulating film 133 and a second interlayer insulating film 117 are formed to cover the active layers 130 and 131 of the switching TFT 101 and the driving TFT 102, the gate electrodes 114 and 115, and the gate insulating film 116. In FIG. 2, a two-layer interlayer insulating film of the first interlayer insulating film 133 and the second interlayer insulating film 117 is formed, but the interlayer insulating film may be a single layer. On the second interlayer insulating film 117, a source line (S), connection wirings 118 and 119, and a power supply line (V) are formed.
[0033]
The source line (S) is connected to the impurity region 110 through contact holes formed in the first interlayer insulating film 133, the second interlayer insulating film 117, and the gate insulating film 116. The connection wiring 118 is connected to the impurity region 111 through contact holes formed in the first interlayer insulating film 133, the second interlayer insulating film 117, and the gate insulating film 116.
[0034]
The connection wiring 119 is connected to the impurity region 112 through contact holes formed in the first interlayer insulating film 133 and the second interlayer insulating film 117. The power supply line (V) is connected to the impurity region 113 through a contact hole formed in the first interlayer insulating film 133 and the second interlayer insulating film 117.
[0035]
The connection wiring 118 overlaps the active layer 130 with the second interlayer insulating film 117, the first interlayer insulating film 133, and the gate insulating film 116 interposed therebetween.
[0036]
A third interlayer insulating film 120 is formed on the second interlayer insulating film 117 so as to cover the source line (S), the connection wirings 118 and 119, and the power supply line (V). A capacitor wiring 121 and a pixel electrode 122 are formed on the third interlayer insulating film 120.
[0037]
The pixel electrode 122 is connected to the connection wiring 119 through a contact hole formed in the third interlayer insulating film 120.
[0038]
In the present invention, the storage capacitor 104 is formed in a portion where the third interlayer insulating film 120 is formed between the connection wiring 118 and the capacitor wiring 121. Since the capacitor wiring 121 can be formed using the same conductive film as the pixel electrode 122, a storage capacitor can be formed without increasing the number of steps. In addition, since the storage capacitor 104 is formed so as to overlap with the active layer 130 of the switching TFT 101, a decrease in the aperture ratio can be suppressed even if the storage capacitor is formed.
[0039]
A fourth interlayer insulating film 125 is formed on the third interlayer insulating film 120 so as to cover the capacitor wiring 121 and the pixel electrode 122. The fourth interlayer insulating film 125 is partially etched, and the pixel electrode 122 is exposed.
[0040]
The organic light emitting layer 123 and the counter electrode 124 are sequentially stacked so as to cover the pixel electrode 122 and the fourth interlayer insulating film 125, and the pixel electrode 122, the organic light emitting layer 123, and the counter electrode 124 overlap each other. Corresponds to the OLED 103.
[0041]
In the present invention, the TFT is not limited to the structure shown in FIG. In the present invention, in addition to the storage capacitor 104 formed using the connection wiring 118 and the capacitor wiring 121, a storage capacitor having another configuration may be provided.
[0042]
In the pixel structure disclosed in the present invention, since the connection wiring 118 is formed so as to overlap with the active layer of the switching TFT 101, light emitted from the OLED or light incident from the outside of the light emitting device is active layer 130. , The off-current can be prevented from flowing to the switching TFT 101.
[0043]
Note that although FIG. 2 shows the case where the switching TFT 101 is an n-channel TFT and the driving TFT 102 is a p-channel TFT, the present invention is not limited to this. The switching TFT 101 and the driving TFT 102 may be either a p-channel TFT or an n-channel TFT. However, since the anode is used as the pixel electrode 122 in FIG. 2, the driving TFT is preferably a p-channel TFT.
[0044]
Further, although an example in which two TFTs are provided in a pixel is described in this embodiment mode, the present invention is not limited to this structure. A storage capacitor having the structure of the present invention can be formed regardless of the number of TFTs included in the pixel. In the present invention, a wiring (connection wiring) formed on the gate electrode and the active layer of the TFT included in the pixel and connected to the active layer, an insulating film formed on the connection wiring, and the insulating film It is only necessary to form a storage capacitor with the formed wiring (capacitive wiring).
[0045]
According to the present invention, since the TFT and the storage capacitor can be formed with the above structure, the capacitance value of the storage capacitor can be increased while suppressing the aperture ratio. Accordingly, a change in gate voltage due to leakage or the like can be suppressed, so that a change in luminance of the OLED can be suppressed and a screen flicker can be suppressed in analog driving.
[0046]
Further, suppressing the decrease in the aperture ratio leads to suppressing the reduction of the effective light emission area of the pixel. The larger the effective light emitting area, the higher the luminance of the screen. Therefore, the power consumption can be suppressed by the configuration of the present invention.
[0047]
【Example】
Examples of the present invention will be described below.
[0048]
(Example 1)
An example of a method for manufacturing a light-emitting device of the present invention will be described with reference to FIGS. Here, a method for manufacturing the pixel TFT shown in FIG. 1 will be described in detail according to the steps.
[0049]
First, in this embodiment, a substrate 200 made of glass such as barium borosilicate glass typified by Corning # 7059 glass or # 1737 glass or aluminoborosilicate glass is used. Note that the substrate 200 may be a light-transmitting substrate, and may be a quartz substrate. Further, a plastic substrate having heat resistance that can withstand the processing temperature of this embodiment may be used.
[0050]
Next, as illustrated in FIG. 3A, a base film 201 formed of an insulating film such as a silicon oxide film, a silicon nitride film, or a silicon oxynitride film is formed over the substrate 200. Although a two-layer structure is used as the base film 201 in this embodiment, a single-layer film of the insulating film or a structure in which two or more layers are stacked may be used. As the first layer of the base film 201, a plasma CVD method is used, and SiH Four , NH Three And N 2 A silicon oxynitride film 201a formed using O as a reactive gas is formed to a thickness of 10 to 200 nm (preferably 50 to 100 nm). In this embodiment, a silicon oxynitride film 201a (composition ratio Si = 32%, O = 27%, N = 24%, H = 17%) having a thickness of 50 nm is formed. Next, as the second layer of the base film 201, a plasma CVD method is used, and SiH Four And N 2 A silicon oxynitride film 201b formed using O as a reactive gas is stacked to a thickness of 50 to 200 nm (preferably 100 to 150 nm). In this embodiment, a silicon oxynitride film 201b (composition ratio Si = 32%, O = 59%, N = 7%, H = 2%) having a thickness of 100 nm is formed.
[0051]
Next, semiconductor layers 202 to 204 are formed over the base film 201. The semiconductor layers 202 to 204 are formed by forming a semiconductor film having an amorphous structure by a known means (a sputtering method, an LPCVD method, a plasma CVD method, or the like) and then a known crystallization treatment (laser crystallization method, heat A crystalline semiconductor film obtained by performing a crystallization method or a thermal crystallization method using a catalyst such as nickel) is formed by patterning into a desired shape. The semiconductor layers 202 to 204 are formed to a thickness of 25 to 80 nm (preferably 30 to 60 nm). The material of the crystalline semiconductor film is not limited, but is preferably silicon (silicon) or silicon germanium (Si X Ge 1-X (X = 0.0001 to 0.02)) It may be formed of an alloy or the like. In this example, a 55 nm amorphous silicon film was formed by plasma CVD, and then a solution containing nickel was held on the amorphous silicon film. This amorphous silicon film is dehydrogenated (500 ° C., 1 hour), then thermally crystallized (550 ° C., 4 hours), and further laser annealed to improve crystallization. Thus, a crystalline silicon film was formed. Then, semiconductor layers 202 to 204 were formed by patterning the crystalline silicon film using a photolithography method.
[0052]
In addition, after the semiconductor layers 202 to 204 are formed, the semiconductor layers 202 to 204 may be doped with a trace amount of impurity elements (boron or phosphorus) in order to control the threshold value of the TFT.
[0053]
When a crystalline semiconductor film is formed by laser crystallization, a pulse oscillation type or continuous emission type excimer laser, YAG laser, YVO Four A laser can be used. When these lasers are used, it is preferable to use a method in which laser light emitted from a laser oscillator is linearly collected by an optical system and irradiated onto a semiconductor film. Crystallization conditions are appropriately selected by the practitioner, but when an excimer laser is used, the pulse oscillation frequency is 300 Hz and the laser energy density is 100 to 400 mJ / cm. 2 (Typically 200-300mJ / cm 2 ). When a YAG laser is used, the second harmonic is used and the pulse oscillation frequency is set to 30 to 300 kHz, and the laser energy density is set to 300 to 600 mJ / cm. 2 (Typically 350-500mJ / cm 2 ) Then, if the laser beam condensed linearly with a width of 100 to 1000 μm, for example 400 μm, is irradiated over the entire surface of the substrate, the superposition ratio (overlap ratio) of the linear laser light at this time is 50 to 98%. Good.
[0054]
Next, a gate insulating film 205 that covers the semiconductor layers 202 to 204 is formed. The gate insulating film 205 is formed of an insulating film containing silicon with a thickness of 40 to 150 nm by using a plasma CVD method or a sputtering method. In this embodiment, a silicon oxynitride film (composition ratio: Si = 32%, O = 59%, N = 7%, H = 2%) with a thickness of 110 nm is formed by plasma CVD. Needless to say, the gate insulating film is not limited to the silicon oxynitride film, and another insulating film containing silicon may be used as a single layer or a stacked structure.
[0055]
When a silicon oxide film is used, TEOS (Tetraethyl Orthosilicate) and O 2 The reaction pressure is 40 Pa, the substrate temperature is 300 to 400 ° C., and the high frequency (13.56 MHz) power density is 0.5 to 0.8 W / cm. 2 And can be formed by discharging. The silicon oxide film thus manufactured can obtain good characteristics as a gate insulating film by thermal annealing at 400 to 500 ° C. thereafter. Through the steps so far, the cross-sectional view shown in FIG.
[0056]
Next, a resist mask 206 is formed, and an n-type impurity element (phosphorus in this embodiment) is added to form impurity regions 207 to 209 containing phosphorus at a high concentration. In this region, phosphorus is 1 × 10 20 ~ 5x10 twenty one atoms / cm Three , Typically 2 × 10 20 ~ 1x10 twenty two atoms / cm Three The concentration of. (Fig. 3 (B))
[0057]
Then, a heat-resistant conductive layer for forming a gate electrode is formed over the gate insulating film 205 (FIG. 3C). The heat-resistant conductive layer 210 may be formed as a single layer, or may have a laminated structure including a plurality of layers such as two layers or three layers as necessary. In this embodiment, a stacked film including the conductive film (A) 210a and the conductive film (B) 210b is formed. The heat resistant conductive layer has an element selected from tantalum (Ta), titanium (Ti), molybdenum (Mo), tungsten (W), chromium (Cr), and silicon (Si), or a conductive material containing the element as a main component. A film (typically a tantalum nitride film, a tungsten nitride film, a titanium nitride film, or the like), or an alloy film (typically, a Mo—W alloy film, a Mo—Ta alloy film, a tungsten silicide film, or the like) that combines the above elements. ) Can be used. In this embodiment, a TaN film is used as the conductive film (A) 210a, and a W film is used as the conductive film (B) 210b. These heat-resistant conductive layers are formed by a sputtering method or a CVD method, and it is preferable to reduce the concentration of impurities contained in order to reduce the resistance. Particularly, the oxygen concentration is preferably 30 ppm or less. The W film may be formed by sputtering using W as a target, or tungsten hexafluoride (WF 6 Can also be formed by a thermal CVD method. In any case, in order to use as a gate electrode, it is necessary to reduce the resistance, and the resistivity of the W film is desirably 20 μΩcm or less. The resistivity of the W film can be reduced by increasing the crystal grains. However, when there are many impurity elements such as oxygen in W, crystallization is hindered and the resistance is increased. Therefore, when sputtering is used, a W target having a purity of 99.99% or 99.9999% is used, and a W film is formed with sufficient consideration so that impurities are not mixed in the gas phase during film formation. By doing so, a resistivity of 9 to 20 μΩcm can be realized.
[0058]
On the other hand, when a Ta film is used for the heat resistant conductive layer 210, it can be similarly formed by sputtering. The Ta film uses Ar as a sputtering gas. In addition, when an appropriate amount of Xe or Kr is added to the gas during sputtering, the internal stress of the film to be formed can be relaxed and the film can be prevented from peeling. The resistivity of the α-phase Ta film is about 20 μΩcm and can be used as a gate electrode, but the resistivity of the β-phase Ta film is about 180 μΩcm and is not suitable for a gate electrode. Since the TaN film has a crystal structure close to an α phase, an α phase Ta film can be easily obtained by forming a TaN film under the Ta film. Although not shown, it is effective to form a silicon film doped with phosphorus (P) with a thickness of about 2 to 20 nm under the heat-resistant conductive layer 210. This improves adhesion and prevents oxidation of the conductive film formed thereon, and at the same time, the alkali metal element contained in a trace amount in the heat-resistant conductive layer 210 diffuses into the first shape gate insulating film 205. Can be prevented. In any case, the heat resistant conductive layer 210 preferably has a resistivity in the range of 10 to 50 μΩcm.
[0059]
After that, the conductive film (A) 210a and the conductive film (B) 210b are patterned into desired shapes to form the gate electrodes 211 and 212 and the capacitor electrode 213 (FIG. 3D). Note that although not shown in FIG. 3D, the capacitor electrode 213 is connected to the gate electrode 212.
[0060]
FIG. 4 shows a top view of the pixel at the time when the step of FIG. 3D is completed. FIG. 3D corresponds to a cross-sectional view taken along the line AA ′ of the pixel shown in FIG. Note that the gate insulating film 205 is omitted for easy understanding of the drawing. Reference numeral 250 denotes a gate line, which is connected to the gate electrode 211.
[0061]
Next, using the gate electrode 211 as a mask, an impurity element imparting n-type conductivity (hereinafter referred to as an n-type impurity element) is added to the semiconductor layers 202 and 203 to be active layers of the subsequent TFT. As the n-type impurity element, an element belonging to Group 15 of the periodic table, typically phosphorus or arsenic can be used. Through this step, first impurity regions 215 to 217, 220, and 221, second impurity regions 218, and channel formation regions 219 and 222 are formed. One of the first impurity regions 215 and 217 functions as a source region and the other functions as a drain region. The second impurity region 218 is a low-concentration impurity region for functioning as an LDD region, and an n-type impurity element is 1 × 10 6. 16 ~ 5x10 18 atoms / cm Three (Typically 1x10 17 ~ 5x10 18 atoms / cm Three ) (FIG. 5A).
[0062]
Next, a region to be a later n-channel TFT is covered with a mask 223, and boron as a p-type impurity element is added to the semiconductor layer 203 to be an active layer of the later p-channel TFT at 3 × 10. 20 ~ 3x10 twenty one atoms / cm Three , Typically 5 × 10 20 ~ 1x10 twenty one atoms / cm Three (FIG. 5B). Through this step, third impurity regions 224 and 225 are formed in the semiconductor layer 203.
[0063]
Next, a first interlayer insulating film 226 is formed over the gate electrodes 211 and 212, the capacitor electrode 213, and the gate insulating film 205. The first interlayer insulating film 226 may be formed using a silicon oxide film, a silicon oxynitride film, a silicon nitride film, or a stacked film including a combination thereof. In any case, the first interlayer insulating film 226 is formed of an inorganic insulating material. The thickness of the first interlayer insulating film 226 is 100 to 200 nm. When a silicon oxide film is used as the first interlayer insulating film 226, TEOS and O2 are formed by plasma CVD. 2 The reaction pressure is 40 Pa, the substrate temperature is 300 to 400 ° C., and the high frequency (13.56 MHz) power density is 0.5 to 0.8 W / cm. 2 And can be formed by discharging. When a silicon oxynitride film is used as the first interlayer insulating film 226, SiH is formed by plasma CVD. Four , N 2 O, NH Three Silicon oxynitride film manufactured from SiH or SiH Four , N 2 A silicon oxynitride film formed from O may be used. The production conditions in this case are a reaction pressure of 20 to 200 Pa, a substrate temperature of 300 to 400 ° C., and a high frequency (60 MHz) power density of 0.1 to 1.0 W / cm. 2 Can be formed. In addition, as the first interlayer insulating film 226, SiH Four , N 2 O, H 2 Alternatively, a silicon oxynitride silicon film manufactured from the above may be used. Similarly, the silicon nitride film is made of SiH by plasma CVD. Four , NH Three It is possible to make from.
[0064]
Then, a step of activating the impurity element imparting n-type or p-type added at each concentration is performed (FIG. 5C). Note that the conductive film used as the gate electrode in this example was very easily oxidized, and there was a problem that the resistivity increased when oxidized. Therefore, the heat treatment for activation in this embodiment is preferably performed by exhausting with a rotary pump and a mechanical booster pump to reduce the oxygen concentration in the atmosphere and performing the heat treatment in a reduced-pressure atmosphere.
[0065]
Next, heat treatment is performed at 410 ° C. for 1 hour in a hydrogen atmosphere for hydrogenation in which dangling bonds in the active layer are terminated by thermally excited hydrogen. As another means of hydrogenation, plasma hydrogenation using hydrogen excited by plasma may be performed.
[0066]
Next, a second interlayer insulating film 227 is formed to a thickness of 500 to 1000 nm (800 nm in this embodiment). As the second interlayer insulating film 227, an organic insulating film such as acrylic, polyimide, polyamide, or BCB (benzocyclobutene), or an inorganic insulating film such as a silicon oxynitride film or a silicon nitride oxide film may be used.
[0067]
Thereafter, a resist mask having a predetermined pattern is formed, and contact holes reaching the first impurity regions 215 and 217, the third impurity regions 224 and 225, and the impurity region 209 are formed. Note that a contact hole reaching the impurity region 209 is omitted in FIG. The contact hole is formed by a dry etching method. In this case, CF is used as an etching gas. Four , O 2 First, the second interlayer insulating film 227 made of an organic resin material is first etched using a mixed gas of He, and then the etching gas is changed to CF. Four , O 2 As a result, the first interlayer insulating film 226 is etched. Further, in order to increase the selectivity with the semiconductor layer, the etching gas is changed to CHF. Three The contact hole can be formed by etching the gate insulating film 205 while switching to.
[0068]
Then, a conductive metal film is formed by a sputtering method or a vacuum deposition method, patterned with a mask, and then etched to form a source line 228, connection wirings 229 and 230, and a power supply line 231. The source line 228 is connected to the first impurity region 215, the connection wiring 229 is connected to the first impurity region 217, the connection wiring 230 is connected to the third impurity region 224, and the power supply line 231 is connected to the third impurity region 225. Although not shown in FIG. 5D, the connection wiring 229 is connected to the gate electrode 212. Although not shown in FIG. 5D, the power supply line 231 is connected to the impurity region 209.
[0069]
Although not shown, in this embodiment, this wiring is formed by a laminated film of a Ti film having a thickness of 50 nm and an alloy film (alloy film of Al and Ti) having a thickness of 500 nm (FIG. 5D). ).
[0070]
FIG. 6 shows a top view of the pixel at the time when the step of FIG. 5D is completed. FIG. 5D corresponds to a cross-sectional view taken along the line AA ′ of the pixel shown in FIG. Note that the gate insulating film 205 and the first and second interlayer insulating films 226 and 227 are omitted for easy understanding of the drawing. Reference numeral 250 denotes a gate line.
[0071]
FIG. 20A illustrates a state where the connection wiring 229 and the gate electrode 212 are connected. Note that FIG. 20A corresponds to a cross-sectional view taken along the line BB ′ of the pixel illustrated in FIG. The connection wiring 229 is connected to the gate electrode 212 through a contact hole formed in the second interlayer insulating film 227 and the first interlayer insulating film 226.
[0072]
FIG. 20B illustrates a state where the power supply line 231 and the impurity region 209 are connected. Note that FIG. 20B corresponds to a cross-sectional view taken along the line CC ′ of the pixel illustrated in FIG. The power supply line 231 is connected to the impurity region 209 through a contact hole formed in the second interlayer insulating film 227 and the first interlayer insulating film 226.
[0073]
Next, a third interlayer insulating film 233 is formed. Since the third interlayer insulating film 233 needs to be planarized, it is formed to a thickness of 1.5 μm using an organic insulating film such as polyimide or acrylic. Then, a contact hole reaching the connection wiring 230 is formed in the third interlayer insulating film 233, and then a transparent conductive film is formed with a thickness of 80 to 120 nm on the third interlayer insulating film 233 and patterned to form a pixel electrode. 234 and the capacitor wiring 235 are formed (FIG. 7A). In this embodiment, an indium tin oxide (ITO) film or a transparent conductive film in which 2 to 20% zinc oxide (ZnO) is mixed with indium oxide is used as the transparent conductive film.
[0074]
The capacitor wiring 235 overlaps the connection wiring 229 with the third interlayer insulating film 233 interposed therebetween. In the present invention, the storage capacitor 236 is formed by the capacitor wiring 235, the third interlayer insulating film 233, and the connection wiring 229.
[0075]
FIG. 8 shows a top view of the pixel at the time when the step of FIG. FIG. 7A corresponds to a cross-sectional view taken along line AA ′ of the pixel shown in FIG. Note that the third interlayer insulating film 233 is omitted for easy understanding of the drawing.
[0076]
Note that although not illustrated in FIG. 7A, the capacitor wiring 235 forming the storage capacitor 236 is connected to each other between adjacent pixels. FIG. 9 shows a state in which a plurality of pixels shown in FIG. 8 are arranged.
[0077]
228 is a source line and 231 is a power supply line. As shown in FIG. 9, the capacitor wiring 235 is connected or shared between adjacent pixels, and a constant potential is applied to all the connection wirings 229. Note that 250 corresponds to a gate line and is connected to the gate electrode 211.
[0078]
Next, as shown in FIG. 7B, a fourth interlayer insulating film 237 having an opening at a position corresponding to the pixel electrode 234 is formed. The fourth interlayer insulating film 237 has insulating properties, functions as a bank, and has a role of separating organic light emitting layers of adjacent pixels. In this embodiment, the fourth interlayer insulating film 237 is formed using a resist.
[0079]
Next, the organic light emitting layer 238 is formed by an evaporation method, and further, a cathode (MgAg electrode) 239 and a protective electrode 240 are formed by an evaporation method. At this time, it is preferable that the pixel electrode 234 is heat-treated before the organic light emitting layer 238 and the cathode 239 are formed to completely remove moisture. In this embodiment, the MgAg electrode is used as the cathode of the OLED, but other known materials may be used.
[0080]
A known material can be used for the organic light emitting layer 238. In this embodiment, the organic light emitting layer has a two-layer structure composed of a hole transporting layer and a light emitting layer, but any one of a hole injection layer, an electron injection layer, and an electron transport layer is provided. In some cases. As described above, various examples of combinations have already been reported, and any of the configurations may be used.
[0081]
In this embodiment, polyphenylene vinylene is formed by a vapor deposition method as a hole transport layer. In addition, as the light emitting layer, 30-40% molecular dispersion of PBD, which is a 1,3,4-oxadiazole derivative, is formed by vapor deposition in polyvinyl carbazole, and about 1% of coumarin 6 is used as a green light emitting center. It is added.
[0082]
In addition, the protective electrode 240 can protect the organic light emitting layer 238 from moisture and oxygen; however, a protective film 241 is preferably provided. In this embodiment, a silicon nitride film having a thickness of 300 nm is provided as the protective film 241. This protective film may also be formed continuously after the protective electrode 240 without being released to the atmosphere.
[0083]
Further, the protective electrode 240 is provided to prevent the cathode 239 from being deteriorated, and a metal film mainly composed of aluminum is typically used. Of course, other materials may be used. In addition, since the organic light emitting layer 238 and the cathode 239 are very sensitive to moisture, it is desirable that the protective electrode 240 is continuously formed without being released to the atmosphere to protect the organic light emitting layer and the cathode from the outside air.
[0084]
The thickness of the organic light emitting layer 238 is 10 to 400 [nm] (typically 60 to 150 [nm]), and the thickness of the cathode 239 is 80 to 200 [nm] (typically 100 to 150 [nm]. nm]).
[0085]
Thus, a light emitting device having a structure as shown in FIG. 7B is completed. A portion 242 where the pixel electrode 234, the organic light emitting layer 238, and the cathode 239 overlap corresponds to the OLED.
[0086]
In this embodiment, the storage capacitor 243 is formed by the impurity region 209, the gate insulating film 205, and the capacitor electrode 213. In addition, a storage capacitor 244 is formed by the capacitor electrode 213, the second interlayer insulating film 227, and the power supply line 231. Since the impurity region 209 and the capacitor electrode 213 overlap with the power supply line 231, the storage capacitors 243 and 244 can be formed without reducing the aperture ratio.
[0087]
Reference numeral 245 denotes a switching TFT, and 246 denotes a driving TFT.
[0088]
Actually, when completed up to FIG. 7 (B), a protective film (laminate film, UV curable resin film, etc.) or a light-transmitting sealing material that is highly airtight and less degassed so as not to be exposed to the outside air. It is preferable to package (enclose). At that time, if the inside of the sealing material is made an inert atmosphere or a hygroscopic material (for example, barium oxide) is arranged inside, the reliability of the OLED is improved.
[0089]
The manufacturing method of the light-emitting device of the present invention is not limited to the manufacturing method described in this embodiment. The light emitting device of the present invention can be manufactured using a known method.
[0090]
(Example 2)
In this embodiment, a storage capacitor of the present invention having a structure different from that in FIG.
[0091]
FIG. 10 shows a cross-sectional view of the pixel of this embodiment. Reference numeral 301 denotes a switching TFT and 302 denotes a driving TFT. In this embodiment, an n-channel TFT and a p-channel TFT are used, respectively, but this embodiment is not limited to this configuration. As the switching TFT and the driving TFT, either an n-channel TFT or a p-channel TFT may be used.
[0092]
After forming the second interlayer insulating film 303, contact holes are formed in the second interlayer insulating film 303, the gate insulating film 307, and the first interlayer insulating film 306. Next, conductive layers to be the connection wirings 305 and 320, the source line 304, and the power supply line 321 are formed. In this embodiment, as a conductive layer, a conductive film mainly composed of titanium (Ti) is formed to a thickness of 50 to 100 nm, and then a conductive film mainly composed of aluminum (Al) is formed to a thickness of 300 to 500 nm. It was set as the laminated structure which forms into a film. Note that the conductive film for forming the connection wiring is either a film containing tantalum (Ta) as a main component, a conductive film containing aluminum (Al) as a main component, or a film containing titanium (Ti) as a main component. May be formed by laminating.
[0093]
Then, an insulating film 310 serving as a dielectric having a thickness of 20 to 100 nm (preferably 30 to 50 nm) is formed on the surface of the conductive layer by an anodic oxidation method or a plasma oxidation method (an anodic oxidation method in this embodiment). . In this embodiment, a film mainly composed of titanium and a film mainly composed of aluminum are stacked as the connection wiring 305, and the film mainly composed of aluminum is anodized and is an anodized film. An aluminum oxide film (alumina film) is formed. In this embodiment, this anodic oxide film corresponds to the insulating film 310 and is used as a dielectric for a storage capacitor. Note that an oxide insulating film obtained by anodizing tantalum (Ta) or titanium (Ti) also has a high dielectric constant, and thus can be suitably used as a dielectric for a storage capacitor.
[0094]
In this anodizing treatment, first, an ethylene glycol tartrate solution having a sufficiently low alkali ion concentration is prepared. This is a solution of 15% ammonium tartrate aqueous solution and ethylene glycol mixed at 2: 8, and ammonia water is added to this to adjust the pH to 7 ± 0.5. Then, a platinum electrode serving as a cathode is provided in the solution, the substrate on which the conductive layer is formed is immersed in the solution, and a constant (several mA to several tens mA) direct current is passed using the conductive layer as an anode. In this embodiment, a current of 200 mA was passed through one substrate.
[0095]
The voltage between the cathode and the anode in the solution changes with time according to the growth of the anodic oxide, but the voltage is increased at a constant step-up rate while maintaining a constant current. Terminate. In this manner, the insulating film 305 having a thickness of about 50 nm can be formed on the surface of the connection wiring 305. The numerical values related to the anodic oxidation method shown here are only examples, and the optimum values can naturally vary depending on the size of the element to be manufactured.
[0096]
When an anodic oxide film is formed on an aluminum film under the conditions of the anodic oxidation method in this embodiment, an Al film with a thickness of 51.4 nm is formed. X O Y A film was formed. This Al X O Y An ITO film of 1 mmΦ is formed on the film, and Al film-Al X O Y When a voltage of 5 V is applied between the film and the ITO film, 1 × 10 -11 The minute leak current of (A) was measured. As a result, Al X O Y It was found that the film can be used as a dielectric for a storage capacitor of a light emitting device.
[0097]
Note that although the insulating film 310 is formed using an anodic oxidation method here, the insulating film may be formed by a vapor phase method such as a plasma CVD method, a thermal CVD method, or a sputtering method. Alternatively, a silicon oxide film, a silicon nitride film, a silicon nitride oxide film, a DLC (Diamond Like Carbon) film, a tantalum oxide film, or an organic insulating film may be used. Further, a laminated film combining these may be used.
[0098]
After the insulating film 310 is formed, the conductive film and the insulating film 310 are patterned into a desired shape, so that the connection wiring 305, the source line 304, the connection wiring 320, and the power supply line 321 are formed. The source wiring 304 is connected to the impurity region 308 of the active layer included in the switching TFT 301 through contact holes formed in the second interlayer insulating film 303, the first interlayer insulating film 306, and the gate insulating film 307. Similarly, the connection wiring 305 is also connected to the impurity region 309 of the active layer included in the switching TFT 301 through a contact hole formed in the second interlayer insulating film 303, the first interlayer insulating film 306, and the gate insulating film 307. ing.
[0099]
Thereafter, a third interlayer insulating film 311 is formed. Then, a part of the third interlayer insulating film 311 is removed by etching, and the insulating film 310 in contact with the connection wiring 305 is exposed. Separately from this step, a contact hole reaching the connection wiring 320 is also formed. At this time, part of the insulating film 310 formed in contact with the connection wiring 320 is removed, and the connection wiring 320 is exposed.
[0100]
Thereafter, a transparent conductive film is formed and etched, whereby the capacitor wiring 322 and the pixel electrode 323 are formed. The pixel electrode is connected to the connection wiring 320 through a contact hole formed in the third interlayer insulating film 311.
[0101]
In this embodiment, a storage capacitor 324 is formed by the connection wiring 305, the insulating film 310 in contact with the connection wiring 305, and the capacitor wiring 322.
[0102]
In the storage capacitor of the configuration of the present embodiment, the selection range such as the thickness of the dielectric and the dielectric constant is wider than that of the first embodiment.
[0103]
(Example 3)
In this embodiment, an example in which a gate line is formed in the same layer as a connection wiring will be described.
[0104]
FIG. 11 shows a cross-sectional view of the pixel of this embodiment. Reference numeral 301 denotes a switching TFT, and 302 denotes a driving TFT. 303 corresponds to a source line, and 304 corresponds to a power supply line.
[0105]
The source line 303 and the power supply line 304 are formed on the gate insulating film 307 simultaneously with the gate electrode 305 of the switching TFT 301 and the gate electrode 306 of the driving TFT 302. The capacitor electrode 304 overlaps with the impurity region 308 with the gate insulating film 307 interposed therebetween. A storage capacitor 309 is formed by the capacitor electrode 304, the gate insulating film 307, and the impurity region 308.
[0106]
On the second interlayer insulating film 310, connection wirings 311 to 314 and a gate line 330 are formed. The source line 303 and the connection wiring 311 are connected through contact holes formed in the second interlayer insulating film 310 and the first interlayer insulating film 320, and the capacitor electrode 304 and the connection wiring 314 are connected. Has been.
[0107]
Further, the impurity region 321 of the switching TFT 301 and the connection wiring 311 are connected through contact holes formed in the second interlayer insulating film 310, the first interlayer insulating film 320, and the gate insulating film 307. The impurity region 322 and the connection wiring 312 are connected. Similarly, the impurity region 323 of the driving TFT 302 and the connection wiring 313 are connected through contact holes formed in the second interlayer insulating film 310, the first interlayer insulating film 320, and the gate insulating film 307. The impurity region 324 of the TFT 302 and the connection wiring 314 are connected.
[0108]
The connection wiring 312 overlaps the active layer of the switching TFT with the first and second interlayer insulating films 320 and 310 interposed therebetween. Although not shown, the gate line 330 is connected to the gate electrode 305 of the switching TFT through a contact hole formed in the second interlayer insulating film 310 and the first interlayer insulating film 320.
[0109]
A third interlayer insulating film 340 is formed on the second interlayer insulating film 310 so as to cover the connection wirings 311 to 314 and the gate line 330. On the third interlayer insulating film 340, a capacitor wiring 341 and a pixel electrode 342 made of the same conductive film are formed. The pixel electrode 342 is connected to the connection wiring 313 through a contact hole formed in the third interlayer insulating film 340.
[0110]
The storage capacitor 343, which is a feature of the present invention, is formed by the connection wiring 312, the third interlayer insulating film 340, and the capacitor wiring 341.
[0111]
By forming the gate line in the same layer as the connection wiring as in this embodiment, the number of steps can be suppressed even if the gate electrode and the gate line are formed of different materials. Therefore, it is also possible to form the gate electrode using a material that can be precisely processed and to form the gate line using a material having low resistance.
[0112]
This embodiment can be implemented in combination with Embodiment 2.
[0113]
Example 4
In this embodiment, a pixel configuration using an inverted staggered TFT will be described.
[0114]
FIG. 12 shows a cross-sectional view of the pixel of this embodiment. Reference numeral 401 denotes a switching TFT, and 402 denotes a driving TFT.
[0115]
A source line 405, connection wirings 406 and 407, and a power supply line 408 are formed on the first interlayer insulating film 409. The source line 405 is connected to the impurity region 410 of the switching TFT 401 through a contact hole formed in the first interlayer insulating film 409. The connection wiring 406 is also connected to the impurity region 411 of the switching TFT 401 through a contact hole formed in the first interlayer insulating film 409.
[0116]
The connection wiring 407 is connected to the impurity region 412 of the driving TFT 402 through a contact hole formed in the first interlayer insulating film 409. The power supply line 408 is connected to the impurity region 413 of the driving TFT 402 via a contact hole formed in the first interlayer insulating film 409.
[0117]
A second interlayer insulating film 415 is formed on the first interlayer insulating film 409 so as to cover the source line 405, the connection wirings 406 and 407, and the power supply line 408. On the second interlayer insulating film 415, a capacitor wiring 416 and a pixel electrode 417 made of the same conductive film are formed. Note that the pixel electrode 417 is connected to the connection wiring 407 through a contact hole formed in the second interlayer insulating film 415.
[0118]
This embodiment can be implemented by freely combining with the configuration of the second embodiment.
[0119]
(Example 5)
In this embodiment, an example in which a gate line is formed between an active layer of a switching TFT and a substrate will be described.
[0120]
A cross-sectional view of the pixel of this example is shown in FIG. Reference numeral 501 denotes a switching TFT, and reference numeral 502 denotes a driving TFT. A light shielding film 505 functioning as a gate line is formed between the active layer 503 of the switching TFT 501 and the substrate 504.
[0121]
As a film for forming the light shielding film 505, a polysilicon film, WSi x (X = 2.0 to 2.8) Any one kind or plural kinds of films made of a conductive material such as a film, Al, Ta, W, Cr, and Mo may be formed. In this embodiment, the polysilicon film has a thickness of 50 nm and WSi. x A film was formed to have a thickness of 100 nm and was formed as a light-shielding film 505.
[0122]
A base insulating film 506 is formed between the light shielding film 505 and the active layer 503. As the base insulating film 506, an insulating film containing silicon (eg, a silicon oxide film, a silicon oxynitride film, a silicon nitride film, or the like) is formed by a plasma CVD method, a sputtering method, or the like.
[0123]
In a later step, before forming the gate electrode 507 of the switching TFT 501, a contact hole reaching the light shielding film 505 is formed in the base insulating film 506, and a conductive film to be the gate electrode 507 is formed. Then, the conductive film is patterned to form a gate electrode 507 connected to the light shielding film 505.
[0124]
In the above structure, since the gate line and the switching TFT 501 overlap, the aperture ratio can be increased.
[0125]
This embodiment can be implemented by freely combining with the second embodiment.
[0126]
(Example 6)
In this embodiment, a driving method of the light emitting device of the present invention will be described.
[0127]
FIG. 14 is a circuit diagram of a pixel portion of the light emitting device of the present invention. Reference numeral 601 denotes a switching TFT, 602 denotes a driving TFT, 603 denotes an OLED, and 604 denotes a storage capacitor. The detailed connection configuration of the pixels is the same as that of the pixel shown in FIG.
[0128]
Source lines S1 to Sx, power supply lines V1 to Vx, and gate lines G1 to Gy are formed in the pixel portion. Each pixel has any one of source lines S1 to Sx, any one of power supply lines V1 to Vx, and any one of gate lines G1 to Gy.
[0129]
FIG. 15 shows a timing chart when the light emitting device shown in FIG. 14 is driven in an analog manner. A period from selection of one gate line to selection of another gate line is defined as one line period (L). In this specification, the selection of a gate line means that all TFTs connected to the gate line of the gate line are turned on.
[0130]
A period from when one image is displayed until the next image is displayed corresponds to one frame period (F). In the case of the light-emitting device shown in FIG. 14, since there are y gate lines, y line periods (L1 to Ly) are provided in one frame period.
[0131]
First, the potential (power supply potential) of the power supply lines (V1 to Vx) is kept constant. The potential of the counter electrode is also kept constant. The potential of the counter electrode has a potential difference from the power supply potential to such an extent that the OLED emits light when the power supply potential is applied to the pixel electrode of the OLED.
[0132]
In the first line period (L1), the gate line G1 is selected by the selection signal, and all the switching TFTs 601 connected to the gate line G1 are turned on. Then, analog video signals are sequentially input to the source lines (S1 to Sx). The analog video signal input to the source lines (S1 to Sx) is input to the gate electrode of the driving TFT 602 via the switching TFT 601.
[0133]
The amount of current flowing through the channel formation region of the driving TFT 602 is the gate voltage V which is the potential difference between the gate electrode and the source region of the driving TFT 602. GS Controlled by. Therefore, the potential applied to the pixel electrode of the OLED 603 is determined by the height of the potential of the analog video signal input to the gate electrode of the driving TFT 602. Accordingly, the OLED 603 emits light with the brightness controlled by the potential of the analog video signal.
[0134]
When the operation described above is repeated and the input of analog video signals to all the source lines (S1 to Sx) is completed, the first line period (L1) is completed. The period until the input of the analog video signal to the source lines (S1 to Sx) and the horizontal blanking period may be combined into one line period. Then, the second line period (L2) is started, the gate line G2 is selected by the selection signal, and analog video signals are sequentially input to the source lines (S1 to Sx) as in the first line period (L1). Is done.
[0135]
When all the gate lines (G1 to Gy) are selected, all the line periods (L1 to Ly) are finished. When all the line periods (L1 to Ly) end, one frame period ends. All pixels display during one frame period, and one image is formed. All the line periods (L1 to Ly) and the vertical blanking period may be combined into one frame period.
[0136]
As described above, in analog driving, the luminance of the OLED is controlled by the potential of the analog video signal, and gradation display is performed by controlling the luminance.
[0137]
In analog driving, it is desirable that the capacitance value of the storage capacitor is larger than that in the case of digital driving. Therefore, a configuration having a storage capacitor with a large capacitance value while suppressing a decrease in the aperture ratio as in the light emitting device of the present invention is analog Suitable for driving. However, the present invention is not limited to this driving method, and it is sufficiently possible to apply the present invention to a digitally driven light emitting device.
[0138]
This embodiment can be implemented by freely combining with Embodiments 1-5.
[0139]
(Example 7)
In this example, a driving method different from that in Example 6 of the light emitting device having the configuration shown in FIG. 14 will be described.
[0140]
The light emitting device of this embodiment displays an image using a digital video signal having image information (hereinafter referred to as a digital video signal). FIG. 16 shows the timings at which the writing period and the light emission period appear in digital driving. The horizontal axis indicates time, and the vertical axis indicates the pixel position of each line.
[0141]
First, the power supply potential of the power supply lines (V1 to Vx) is kept the same as the potential of the counter electrode of the OLED 603. Then, the gate line G1 is selected by the selection signal, and the switching TFTs 601 of all the pixels (pixels in the first line) connected to the gate line G1 are turned on.
[0142]
Then, the first bit digital video signal is input to the source lines (S1 to Sx). The digital video signal is input to the gate electrode of the driving TFT 602 through the switching TFT 601.
[0143]
Next, the selection of the gate line G1 is completed, the gate line G2 is selected, and the switching TFTs 601 of all the pixels connected to the gate line G2 are turned on. Then, the digital video signal of the first bit is input from the source lines (S1 to Sx) to the pixels of the second line.
[0144]
In turn, all the gate lines (G1 to Gy) are selected. The period until all the gate lines (G1 to Gy) are selected and the first bit digital video signal is input to the pixels of all the lines is the writing period Ta1.
[0145]
When the writing period Ta1 ends, the display period Tr1 follows. In the display period Tr1, the power supply potential of the power supply line is high enough to have a potential difference from the counter electrode so that the OLED emits light when the power supply potential is applied to the pixel electrode of the OLED.
[0146]
In the display period Tr1, whether or not the OLED 603 emits light is selected according to the digital video signal written to the pixel in the writing period Ta1. When the digital video signal has information of “0”, the driving TFT 602 is turned off. Therefore, no power supply potential is applied to the pixel electrode of the OLED 603. As a result, the OLED 603 included in the pixel to which the digital video signal having the information “0” is input does not emit light. On the other hand, when the information “1” is included, the driving TFT 602 is turned on. Therefore, a power supply potential is applied to the pixel electrode of the OLED 603. As a result, the OLED 603 included in the pixel to which the digital video signal having the information “1” is input emits light.
[0147]
As described above, in the display period Tr1, the OLED 603 emits light or does not emit light, and all the pixels perform display.
[0148]
When the display period Tr1 ends, the writing period Ta2 starts, and the power supply potential of the power supply line becomes the same as the potential of the counter electrode of the OLED. In the same manner as in the writing period Ta1, all the gate lines are sequentially selected, and the second bit digital video signal is input to all the pixels. A period until the second bit digital video signal is completely input to the pixels of all the lines is referred to as a writing period Ta2.
[0149]
When the writing period Ta2 ends, the display period Tr2 starts, and the power supply potential of the power supply line is set to a potential having a potential difference with the counter electrode so that the OLED 603 emits light when the power supply potential is applied to the pixel electrode of the OLED 603. Become. All pixels display.
[0150]
The above-described operation is repeated until the n-th digital video signal is input to the pixel, and the writing period Ta and the display period Tr appear repeatedly. When all the display periods (Tr1 to Trn) are completed, one image can be displayed. In the driving method of this embodiment, a period for displaying one image is referred to as one frame period (F). When one frame period ends, the next frame period starts. Then, the writing period Ta1 appears again, and the above-described operation is repeated.
[0151]
In a normal light emitting device, it is preferable to provide 60 or more frame periods per second. When the number of images displayed per second is less than 60, flickering of images may start to be noticeable visually.
[0152]
In this embodiment, the sum of the lengths of all the writing periods is shorter than one frame period, and the length ratio of the display periods is Tr1: Tr2: Tr3:...: Tr (n−1): Trn = 2 0 : 2 1 : 2 2 : ...: 2 (n-2) : 2 (n-1) It is necessary to ensure that 2 in combination with this display period n Of the gradations, a desired gradation display can be performed.
[0153]
By obtaining the sum of the lengths of the display periods during which the OLED emits light during one frame period, the gradation displayed by the pixel in the frame period is determined. For example, when n = 8, assuming that the luminance is 100% when the pixels emit light in the entire display period, 1% luminance can be expressed when the pixels emit light in Tr1 and Tr2, and Tr3, Tr5, and Tr8 When is selected, a luminance of 60% can be expressed.
[0154]
The display periods Tr1 to Trn may appear in any order. For example, in one frame period, it is possible to cause the display period to appear in the order of Tr3, Tr5, Tr2,.
[0155]
In this embodiment, the power supply potential of the power supply line is changed between the writing period and the display period, but the present invention is not limited to this. The power supply potential and the potential of the counter electrode may always have a potential difference such that the OLED emits light when the power supply potential is applied to the pixel electrode of the OLED. In that case, the OLED can emit light even in the writing period. Therefore, the gradation displayed by the pixel in the frame period is determined by the sum of the length of the writing period and the display period during which the OLED emits light during one frame period. In this case, the ratio of the sum of the length of the writing period and the display period corresponding to the digital video signal of each bit is (Ta1 + Tr1) :( Ta2 + Tr2) :( Ta3 + Tr3): ... :( Ta (n-1) + Tr ( n-1)): (Tan + Trn) = 2 0 : 2 1 : 2 2 : ...: 2 (n-2) : 2 (n-1) It is necessary to become.
[0156]
This embodiment can be implemented by freely combining with Embodiments 1-5.
[0157]
(Example 8)
In this example, an example in which a light-emitting device is manufactured using the present invention will be described with reference to FIGS.
[0158]
FIG. 17A is a top view of a light-emitting device formed by sealing a substrate on which an OLED is formed with a sealing material, and FIG. 17B is a cross-sectional view taken along line AA ′ of FIG. FIG. 17C is a cross-sectional view taken along the line BB ′ of FIG.
[0159]
A sealant 4009 is provided so as to surround the pixel portion 4002 provided over the substrate 4001, the source line driver circuit 4003, and the first and second gate line driver circuits 4004a and 4004b. Further, a sealing material 4008 is provided over the pixel portion 4002, the source line driver circuit 4003, and the first and second gate line driver circuits 4004a and 4004b. Therefore, the pixel portion 4002, the source line driver circuit 4003, and the first and second gate line driver circuits 4004 a and 400 b are sealed with the filler 4210 by the substrate 4001, the sealant 4009, and the sealant 4008. .
[0160]
The pixel portion 4002, the source line driver circuit 4003, and the first and second gate line driver circuits 4004a and 4004b provided over the substrate 4001 include a plurality of TFTs. The source line driver circuit 4003 is a circuit for inputting a video signal to the source line, and the first and second gate line driver circuits 4004a and 400b are circuits for selecting a gate line by a selection signal.
[0161]
In FIG. 17B, a driver circuit TFT included in the source line driver circuit 4003 formed over the base film 4010 (note that an n-channel TFT and a p-channel TFT are illustrated here) 4201 as a representative. In addition, a driving TFT (TFT for controlling current to the OLED) 4202 included in the pixel portion 4002 is illustrated.
[0162]
In this embodiment, a p-channel TFT or an n-channel TFT manufactured by a known method is used for the driving circuit TFT 4201, and a p-channel TFT manufactured by a known method is used for the driving TFT 4202. . Further, the pixel portion 4002 is provided with a storage capacitor (not shown) connected to the gate of the driving TFT 4202.
[0163]
An interlayer insulating film (planarization film) 4301 is formed over the driver circuit TFT 4201 and the driver TFT 4202, and a pixel electrode (anode) 4203 electrically connected to the drain of the driver TFT 4202 is formed thereon. As the pixel electrode 4203, a transparent conductive film having a large work function is used. As the transparent conductive film, a compound of indium oxide and tin oxide, a compound of indium oxide and zinc oxide, zinc oxide, tin oxide, or indium oxide can be used. Moreover, you may use what added the gallium to the said transparent conductive film.
[0164]
An insulating film 4302 is formed over the pixel electrode 4203, and an opening is formed over the pixel electrode 4203 in the insulating film 4302. In this opening, an organic light emitting layer 4204 is formed on the pixel electrode 4203. A known organic light emitting material or inorganic light emitting material can be used for the organic light emitting layer 4204. The organic light emitting material includes a low molecular (monomer) material and a high molecular (polymer) material, either of which may be used.
[0165]
As a method for forming the organic light emitting layer 4204, a known vapor deposition technique or coating technique may be used. The structure of the organic light emitting layer may be a laminated structure or a single layer structure by freely combining a hole injection layer, a hole transport layer, a light emitting layer, an electron transport layer, or an electron injection layer.
[0166]
On the organic light emitting layer 4204, a cathode 4205 made of a light-shielding conductive film (typically a conductive film containing aluminum, copper or silver as a main component or a laminated film of these with another conductive film) is formed. The In addition, it is desirable to remove moisture and oxygen present at the interface between the cathode 4205 and the organic light emitting layer 4204 as much as possible. Therefore, it is necessary to devise a method in which the organic light emitting layer 4204 is formed in a nitrogen or rare gas atmosphere and the cathode 4205 is formed without being exposed to oxygen or moisture. In this embodiment, the above-described film formation is possible by using a multi-chamber type (cluster tool type) film formation apparatus. The cathode 4205 is given a predetermined voltage.
[0167]
As described above, the OLED 4303 including the pixel electrode (anode) 4203, the organic light emitting layer 4204, and the cathode 4205 is formed. A protective film 4209 is formed on the insulating film 4302 so as to cover the OLED 4303. The protective film 4209 is effective in preventing oxygen, moisture, and the like from entering the OLED 4303.
[0168]
Reference numeral 4005 a denotes a lead wiring connected to the power supply line, and is electrically connected to the source region of the driving TFT 4202. The lead wiring 4005 a passes between the sealant 4009 and the substrate 4001 and is electrically connected to the FPC wiring 4301 included in the FPC 4006 through the anisotropic conductive film 4300.
[0169]
As the sealing material 4008, a glass material, a metal material (typically a stainless steel material), a ceramic material, or a plastic material (including a plastic film) can be used. As the plastic material, an FRP (Fiberglass-Reinforced Plastics) plate, a PVF (polyvinyl fluoride) film, a mylar film, a polyester film, or an acrylic resin film can be used. A sheet having a structure in which an aluminum foil is sandwiched between PVF films or mylar films can also be used.
[0170]
However, when the radiation direction of light from the OLED is directed toward the sealing material, the sealing material must be transparent. In that case, a transparent material such as a glass plate, a plastic plate, a polyester film or an acrylic film is used.
[0171]
As the filler 4210, in addition to an inert gas such as nitrogen or argon, an ultraviolet curable resin or a thermosetting resin can be used. PVC (polyvinyl chloride), acrylic, polyimide, epoxy resin, silicone resin, PVB (Polyvinyl butyral) or EVA (ethylene vinyl acetate) can be used. In this example, nitrogen was used as the filler.
[0172]
In order to expose the filler 4210 to a hygroscopic substance (preferably barium oxide) or a substance capable of adsorbing oxygen, a recess 4007 is provided on the surface of the sealing material 4008 on the substrate 4001 side to adsorb the hygroscopic substance or oxygen. A possible substance 4207 is placed. In order to prevent the hygroscopic substance or the substance 4207 capable of adsorbing oxygen from scattering, the concave part cover material 4208 holds the hygroscopic substance or the substance 4207 capable of adsorbing oxygen in the concave part 4007. Note that the concave cover material 4208 has a fine mesh shape, and is configured to allow air and moisture to pass therethrough but not a hygroscopic substance or a substance 4207 capable of adsorbing oxygen. By providing the hygroscopic substance or the substance 4207 capable of adsorbing oxygen, deterioration of the OLED 4303 can be suppressed.
[0173]
As shown in FIG. 17C, the conductive film 4203a is formed so as to be in contact with the lead wiring 4005a at the same time as the pixel electrode 4203 is formed.
[0174]
The anisotropic conductive film 4300 has a conductive filler 4300a. By thermally pressing the substrate 4001 and the FPC 4006, the conductive film 4203a on the substrate 4001 and the FPC wiring 4301 on the FPC 4006 are electrically connected by the conductive filler 4300a.
[0175]
This embodiment can be implemented by freely combining with Embodiments 1-7.
[0176]
Example 9
In the present invention, by using an organic light emitting material that can utilize phosphorescence from triplet excitons for light emission, the external light emission quantum efficiency can be dramatically improved. Thereby, low power consumption, long life, and light weight of the OLED can be achieved.
[0177]
Here, a report of using triplet excitons to improve the external emission quantum efficiency is shown.
(T. Tsutsui, C. Adachi, S. Saito, Photochemical Processes in Organized Molecular Systems, ed. K. Honda, (Elsevier Sci. Pub., Tokyo, 1991) p.437.)
[0178]
The molecular formula of the organic light-emitting material (coumarin dye) reported by the above paper is shown below.
[0179]
[Chemical 1]
[0180]
(MABaldo, DFO'Brien, Y.You, A.Shoustikov, S.Sibley, METhompson, SRForrest, Nature 395 (1998) p.151.)
[0181]
The molecular formula of the organic light-emitting material (Pt complex) reported by the above paper is shown below.
[0182]
[Chemical 2]
[0183]
(MABaldo, S. Lamansky, PEBurrrows, METhompson, SRForrest, Appl.Phys.Lett., 75 (1999) p.4.) (T.Tsutsui, M.-J.Yang, M.Yahiro, K.Nakamura, T Watanabe, T.tsuji, Y.Fukuda, T.Wakimoto, S.Mayaguchi, Jpn.Appl.Phys., 38 (12B) (1999) L1502.)
[0184]
The molecular formula of the organic light-emitting material (Ir complex) reported by the above paper is shown below.
[0185]
[Chemical 3]
[0186]
As described above, if phosphorescence emission from triplet excitons can be used, in principle, it is possible to realize an external emission quantum efficiency that is 3 to 4 times higher than that in the case of using fluorescence emission from singlet excitons.
[0187]
In addition, the structure of a present Example can be implemented in combination freely with any structure of Example 1- Example 8. FIG.
[0188]
(Example 10)
In this embodiment, a storage capacitor of the present invention having a configuration different from that in FIG. 2 will be described.
[0189]
FIG. 21 is a cross-sectional view of the pixel of this example. 2 that are already shown in FIG.
[0190]
A source line (S), connection wirings 118 and 119, and a power supply line (V) are formed on the second interlayer insulating film 117. The source line (S) is formed on the second interlayer insulating film 117. The impurity region 110 is connected through the contact hole. The connection wiring 118 is connected to the impurity region 111 through a contact hole formed in the second interlayer insulating film 117. The connection wiring 119 is connected to the impurity region 112 through a contact hole formed in the second interlayer insulating film 117. The power supply line (V) is connected to the impurity region 113 through a contact hole formed in the second interlayer insulating film 117. The connection wiring 118 overlaps the active layer 130 with the second interlayer insulating film 117 interposed therebetween.
[0191]
Then, a capacitor insulating film 170 is formed on the second interlayer insulating film 117 so as to cover the source line (S), the connection wirings 118 and 119, and the power supply line (V). As the material of the capacitor insulating film 170, either an inorganic material or an organic material can be used as long as it has insulating properties. However, it is important that the etching selectivity is different from that of the third interlayer insulating film 120 to be formed later.
[0192]
Next, a third interlayer insulating film 120 is formed on the capacitor insulating film 170. The third interlayer insulating film is partially removed by etching in the portion overlapping with the connection wiring 118, and the capacitor insulating film 170 is exposed. With the above structure, the capacitor wiring 121 to be formed later, the capacitor insulating film 170, and the connection wiring 118 are sequentially formed in contact with each other.
[0193]
A capacitor wiring 121 and a pixel electrode 122 are formed on the third interlayer insulating film 120.
[0194]
The pixel electrode 122 is formed on the connection wiring 119 through a contact hole formed in the third interlayer insulating film 120.
[0195]
In this embodiment, the storage capacitor 104 is formed in a portion where the capacitor insulating film 170 is formed between the connection wiring 118 and the capacitor wiring 121. In this embodiment, the capacitor insulating film 170 is described as a layer different from the third interlayer insulating film 120, but the capacitor insulating film 170 is a part of the third interlayer insulating film 120 formed of a plurality of insulating film layers. It can also be regarded as a part.
[0196]
In addition, the structure of a present Example can be implemented in combination freely with any structure of Example 1, Example 3-Example 9. FIG.
[0197]
(Example 11)
Since the light-emitting device is a self-luminous type, it has excellent visibility in a bright place and a wide viewing angle compared to a liquid crystal display. Therefore, it can be used for display portions of various electronic devices.
[0198]
As an electronic device using the light emitting device of the present invention, a video camera, a digital camera, a goggle type display (head mounted display), a navigation system, a sound reproduction device (car audio, audio component, etc.), a notebook type personal computer, a game device, A portable information terminal (mobile computer, cellular phone, portable game machine, electronic book, etc.), an image playback device equipped with a recording medium (specifically, a DVD: Digital Versatile Disc or other recording medium is played back, and the image is displayed. And a device equipped with a display that can be used. In particular, it is desirable to use a light-emitting device for a portable information terminal that often has an opportunity to see a screen from an oblique direction because the wide viewing angle is important. Specific examples of these electronic devices are shown in FIGS.
[0199]
FIG. 18A illustrates an OLED display device which includes a housing 2001, a support base 2002, a display portion 2003, a speaker portion 2004, a video input terminal 2005, and the like. The light emitting device of the present invention can be used for the display portion 2003. Since the light-emitting device is a self-luminous type, a backlight is not necessary and a display portion thinner than a liquid crystal display can be obtained. The OLED display device includes all information display devices such as a personal computer, a TV broadcast receiver, and an advertisement display.
[0200]
FIG. 18B shows a digital still camera, which includes a main body 2101, a display portion 2102, an image receiving portion 2103, operation keys 2104, an external connection port 2105, a shutter 2106, and the like. The light emitting device of the present invention can be used for the display portion 2102.
[0201]
FIG. 18C illustrates a laptop personal computer, which includes a main body 2201, a housing 2202, a display portion 2203, a keyboard 2204, an external connection port 2205, a pointing mouse 2206, and the like. The light-emitting device of the present invention can be used for the display portion 2203.
[0202]
FIG. 18D illustrates a mobile computer, which includes a main body 2301, a display portion 2302, a switch 2303, operation keys 2304, an infrared port 2305, and the like. The light emitting device of the present invention can be used for the display portion 2302.
[0203]
FIG. 18E shows a portable image reproducing device (specifically, a DVD reproducing device) provided with a recording medium, which includes a main body 2401, a housing 2402, a display portion A2403, a display portion B2404, and a recording medium (DVD or the like). A reading unit 2405, operation keys 2406, a speaker unit 2407, and the like are included. Although the display portion A 2403 mainly displays image information and the display portion B 2404 mainly displays character information, the light-emitting device of the present invention can be used for the display portions A, B 2403, and 2404. Note that an image reproducing device provided with a recording medium includes a home game machine and the like.
[0204]
FIG. 18F illustrates a goggle type display (head mounted display), which includes a main body 2501, a display portion 2502, and an arm portion 2503. The light emitting device of the present invention can be used for the display portion 2502.
[0205]
FIG. 18G illustrates a video camera, which includes a main body 2601, a display portion 2602, a housing 2603, an external connection port 2604, a remote control receiving portion 2605, an image receiving portion 2606, a battery 2607, an audio input portion 2608, operation keys 2609, and the like. . The light-emitting device of the present invention can be used for the display portion 2602.
[0206]
Here, FIG. 18H shows a mobile phone, which includes a main body 2701, a housing 2702, a display portion 2703, an audio input portion 2704, an audio output portion 2705, operation keys 2706, an external connection port 2707, an antenna 2708, and the like. The light emitting device of the present invention can be used for the display portion 2703. Note that the display portion 2703 can reduce power consumption of the mobile phone by displaying white characters on a black background.
[0207]
If the light emission luminance of the organic light emitting material is increased in the future, the light including the output image information can be enlarged and projected by a lens or the like and used in a front type or rear type projector.
[0208]
In addition, the electronic devices often display information distributed through electronic communication lines such as the Internet and CATV (cable television), and in particular, opportunities to display moving image information are increasing. Since the organic light emitting material has a very high response speed, the light emitting device is preferable for displaying moving images.
[0209]
Further, since the light emitting part consumes power in the light emitting device, it is desirable to display information so that the light emitting part is minimized. Therefore, when a light emitting device is used for a display unit mainly including character information, such as a portable information terminal, particularly a mobile phone or a sound reproduction device, it is driven so that character information is formed by the light emitting part with the non-light emitting part as the background. It is desirable to do.
[0210]
As described above, the applicable range of the present invention is so wide that it can be used for electronic devices in various fields. In addition, the electronic device of this embodiment may use the light emitting device having any configuration shown in Embodiments 1 to 9.
[0211]
【The invention's effect】
According to the present invention, since the TFT and the storage capacitor can be formed to overlap each other with the above structure, the capacitance value of the storage capacitor can be increased while suppressing a decrease in the aperture ratio. Accordingly, a change in gate voltage due to leakage or the like can be suppressed, so that a change in luminance of the OLED can be suppressed and a screen flicker can be suppressed in analog driving.
[0212]
Further, suppressing the decrease in the aperture ratio leads to suppressing the reduction of the effective light emission area of the pixel. The larger the effective light emitting area, the higher the luminance of the screen. Therefore, the power consumption can be suppressed by the configuration of the present invention.
[Brief description of the drawings]
FIG. 1 is a circuit diagram of a pixel of a light emitting device of the present invention.
FIG. 2 is a cross-sectional view of a pixel of a light-emitting device of the present invention.
FIGS. 3A to 3D are diagrams illustrating a manufacturing process of a light-emitting device of the present invention. FIGS.
FIG. 4 is a top view of the light-emitting device of the present invention.
FIGS. 5A to 5D are diagrams illustrating a manufacturing process of a light-emitting device of the present invention. FIGS.
FIG. 6 is a top view of the light-emitting device of the present invention.
7A and 7B illustrate a manufacturing process of a light-emitting device of the present invention.
FIG. 8 is a top view of the light-emitting device of the present invention.
FIG. 9 is a top view of the light-emitting device of the present invention.
FIG. 10 is a cross-sectional view of a pixel of a light-emitting device of the present invention.
FIG. 11 is a cross-sectional view of a pixel of a light-emitting device of the present invention.
12 is a cross-sectional view of a pixel of a light-emitting device of the present invention.
13 is a cross-sectional view of a pixel of a light-emitting device of the present invention.
FIG. 14 is a circuit diagram of a pixel portion of a light emitting device of the present invention.
FIG. 15 is a timing chart in analog driving.
FIG. 16 is a timing chart in digital driving.
FIGS. 17A and 17B are a top view and a cross-sectional view of a light-emitting device of the present invention. FIGS.
FIG. 18 is a diagram of an electronic device using the light-emitting device of the present invention.
FIG. 19 shows transistor characteristics of a driving TFT.
FIG. 20 is a cross-sectional view of a pixel of a light-emitting device of the present invention.
FIG. 21 is a cross-sectional view of a pixel of a light-emitting device of the present invention.

Claims (25)

  1. A light emitting device having a source line, a power supply line, a switching TFT, a driving TFT, a first storage capacitor, a second storage capacitor, and an OLED,
    One of the source region and the drain region of the switching TFT is electrically connected to the source line, and the other is electrically connected to the gate electrode of the driving TFT through a connection wiring,
    One of a source region and a drain region of the driving TFT is electrically connected to the power supply line, and the other is electrically connected to a pixel electrode included in the OLED.
    The connection wiring is formed on an interlayer insulating film covering the gate electrode of the switching TFT,
    The first storage capacitor includes the connection wiring, the capacitance wiring, and a first insulating film formed between the connection wiring and the capacitance wiring.
    The second storage capacitor includes a capacitor electrode made of the same conductive film as the gate electrode of the driving TFT, a semiconductor layer formed simultaneously with the semiconductor layer of the switching TFT and the driving TFT, and the capacitor electrode And a second insulating film formed between the semiconductor layers of the second storage capacitor .
  2. A light emitting device having a source line, a power supply line, a switching TFT, a driving TFT, a first storage capacitor, a second storage capacitor, and an OLED,
    One of the source region and the drain region of the switching TFT is electrically connected to the source line, and the other is electrically connected to the gate electrode of the driving TFT through a connection wiring,
    One of a source region and a drain region of the driving TFT is electrically connected to the power supply line, and the other is electrically connected to a pixel electrode included in the OLED.
    The connection wiring is formed on an interlayer insulating film covering the gate electrode of the switching TFT,
    The first storage capacitor includes the connection wiring, the capacitance wiring, and a first insulating film formed between the connection wiring and the capacitance wiring.
    The second storage capacitor includes a capacitor electrode made of the same conductive film as the gate electrode of the driving TFT, the power line, and a second insulating film formed between the capacitor electrode and the power line. have a, the second insulating film is a light-emitting device, characterized in that said interlayer insulating film.
  3. A light emitting device having a source line, a power supply line, a switching TFT, a driving TFT, a first storage capacitor, a second storage capacitor, a third storage capacitor, and an OLED,
    One of the source region and the drain region of the switching TFT is electrically connected to the source line, and the other is electrically connected to the gate electrode of the driving TFT through a connection wiring,
    One of a source region and a drain region of the driving TFT is electrically connected to the power supply line, and the other is electrically connected to a pixel electrode included in the OLED.
    The connection wiring is formed on an interlayer insulating film covering the gate electrode of the switching TFT,
    The first storage capacitor includes the connection wiring, the capacitance wiring, and a first insulating film formed between the connection wiring and the capacitance wiring.
    The second storage capacitor includes a capacitor electrode made of the same conductive film as a gate electrode of the driving TFT, a semiconductor layer formed simultaneously with a semiconductor layer of the switching TFT and the driving TFT, and the capacitor electrode And a second insulating film formed between the semiconductor layers of the second storage capacitor ,
    The third storage capacitor, and the capacitor electrode, and the power line, have a third insulating film provided between the capacitor electrode and the power supply line, said third insulating film is the interlayer A light-emitting device which is an insulating film .
  4. According to claim 1 or 2, have a third insulating film covering the upper side of one the TFT and the storage capacitor contact with the pixel electrode, the third insulating film opening at a position corresponding to the pixel electrode the light emitting device characterized in that it comprises a.
  5. 5. The method according to claim 1, wherein a fourth insulating film is provided above the first insulating film, and a part of the fourth insulating film is removed at a portion overlapping with the connection wiring. A light emitting device characterized.
  6. According to claim 3, have a fourth insulating film covering the upper side of one the TFT and the storage capacitor contact with the pixel electrode, the fourth insulating film has openings at positions corresponding to the pixel electrode A light emitting device characterized by that.
  7. 7. The method according to claim 3, wherein a fifth insulating film is provided above the first insulating film, and a part of the fifth insulating film is removed at a portion overlapping with the connection wiring. Light-emitting device.
  8. 8. The light-emitting device according to claim 1 , wherein the capacitor wiring and the pixel electrode are formed of the same conductive film.
  9. 9. The light-emitting device according to claim 1, wherein the connection wiring and the power supply line are formed of the same conductive film.
  10. 10. The light-emitting device according to claim 1, wherein a gate electrode of the driving TFT and the capacitor electrode are electrically connected.
  11. 11. The light-emitting device according to claim 1, wherein the semiconductor layer included in the second storage capacitor and the power supply line are electrically connected.
  12. 12. The light emitting device according to claim 1, wherein the connection wiring overlaps with a semiconductor layer of the switching TFT.
  13. 13. The light-emitting device according to claim 1, wherein the capacitor wiring overlaps with a semiconductor layer of the switching TFT.
  14. 14. The light-emitting device according to claim 1, wherein the capacitor wiring is disposed in parallel with a gate line, and the power supply line is disposed in parallel with the source line.
  15. 15. The light emitting device according to claim 1, wherein the brightness of the OLED is controlled by an analog video signal.
  16. Electronic devices using the light emitting device according to any one of claims 1 to 15.
  17. Forming a semiconductor film,
    Patterning the semiconductor film to form first and second semiconductor layers;
    An insulating film is formed above the first and second semiconductor layers;
    Forming a first conductive film above the insulating film;
    The first conductive film is patterned, a first gate electrode is formed above the first semiconductor layer, a second gate electrode is formed above the second semiconductor layer, and a capacitor electrode is formed form And
    Forming an insulating film a over the first and second gate electrodes and the capacitor electrode;
    Forming a second conductive film above the insulating film A;
    The second conductive film is patterned to form a connection wiring that is electrically connected to the first semiconductor layer and the second gate electrode, and overlaps the capacitor electrode and is electrically connected to the second semiconductor layer. Power supply lines to be connected
    Forming an insulating film over the connection wiring and the power supply line;
    Forming a third conductive film above the insulating film C;
    Patterning the third conductive film to form a pixel electrode electrically connected to the second semiconductor layer, and forming a capacitor wiring overlapping the connection wiring;
    A method for manufacturing a light-emitting device, wherein a light-emitting layer and a counter electrode are formed above the pixel electrode.
  18. Forming a semiconductor film,
    Patterning the semiconductor film to form first, second and third semiconductor layers;
    Forming an insulating film over the first, second and third semiconductor layers;
    Forming a first conductive film above the insulating film;
    The first conductive film is patterned, a first gate electrode is formed above the first semiconductor layer, a second gate electrode is formed above the second semiconductor layer, and the third Forming a capacitive electrode overlying the semiconductor layer of
    Forming an insulating film a over the first and second gate electrodes and the capacitor electrode;
    Forming a second conductive film above the insulating film A;
    The second conductive film is patterned to form a connection wiring electrically connected to the first semiconductor layer and the second gate electrode, and a power supply line electrically connected to the second semiconductor layer Form the
    Forming an insulating film over the connection wiring and the power supply line;
    Forming a third conductive film above the insulating film C;
    Patterning the third conductive film to form a pixel electrode electrically connected to the second semiconductor layer, and forming a capacitor wiring overlapping the connection wiring;
    A method for manufacturing a light-emitting device, wherein a light-emitting layer and a counter electrode are formed above the pixel electrode.
  19. Forming a semiconductor film,
    Patterning the semiconductor film to form first, second and third semiconductor layers;
    Forming an insulating film over the first, second and third semiconductor layers;
    Forming a first conductive film above the insulating film;
    The first conductive film is patterned, a first gate electrode is formed above the first semiconductor layer, a second gate electrode is formed above the second semiconductor layer, and the third Forming a capacitive electrode overlying the semiconductor layer of
    Forming an insulating film a over the first and second gate electrodes and the capacitor electrode;
    Forming a second conductive film above the insulating film A;
    The second conductive film is patterned to form a connection wiring that is electrically connected to the first semiconductor layer and the second gate electrode, and overlaps the capacitor electrode and is electrically connected to the second semiconductor layer. Power supply lines to be connected
    Forming an insulating film over the connection wiring and the power supply line;
    Forming a third conductive film above the insulating film C;
    Patterning the third conductive film to form a pixel electrode electrically connected to the second semiconductor layer, and forming a capacitor wiring overlapping the connection wiring;
    A method for manufacturing a light-emitting device, wherein a light-emitting layer and a counter electrode are formed above the pixel electrode.
  20. 20. The insulating film having an opening at a position corresponding to the pixel electrode is formed above the pixel electrode, and the light emission is formed above the pixel electrode and the insulating film. A method for manufacturing a light-emitting device, comprising forming a layer and the counter electrode.
  21. 21. The insulating film according to claim 17, wherein an insulating film is formed above the insulating film and a part of the insulating film overlapping with the connection wiring is partially removed, and the insulating film and the insulating film are removed. A method for manufacturing a light-emitting device, characterized in that the third conductive film is formed above the film (e).
  22. The method for manufacturing a light-emitting device according to claim 17, wherein the second gate electrode and the capacitor electrode are electrically connected.
  23. 23. The method for manufacturing a light-emitting device according to claim 17, wherein the third semiconductor layer and the power supply line are electrically connected.
  24. 24. The method for manufacturing a light-emitting device according to claim 17, wherein the connection wiring is formed so as to overlap with the first semiconductor layer.
  25. 25. The method for manufacturing a light-emitting device according to claim 17, wherein the capacitor wiring is formed so as to overlap with the first semiconductor layer.
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