CN112582381B - Touch display panel and preparation method thereof - Google Patents
Touch display panel and preparation method thereof Download PDFInfo
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- CN112582381B CN112582381B CN202011451170.3A CN202011451170A CN112582381B CN 112582381 B CN112582381 B CN 112582381B CN 202011451170 A CN202011451170 A CN 202011451170A CN 112582381 B CN112582381 B CN 112582381B
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/40—OLEDs integrated with touch screens
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
- G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
- G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
- G06F3/0412—Digitisers structurally integrated in a display
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/552—Protection against radiation, e.g. light or electromagnetic waves
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
- H10K59/1201—Manufacture or treatment
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2203/00—Indexing scheme relating to G06F3/00 - G06F3/048
- G06F2203/041—Indexing scheme relating to G06F3/041 - G06F3/045
- G06F2203/04103—Manufacturing, i.e. details related to manufacturing processes specially suited for touch sensitive devices
Abstract
The application provides a touch display panel and a preparation method thereof, wherein the touch display panel comprises a substrate, a thin film transistor layer, a light emitting device layer and a touch electrode layer; the touch electrode layer and the light-emitting device layer are positioned on the thin film transistor layer, and the touch electrode layer and the light-emitting device layer are arranged at intervals; the touch display panel further comprises a shielding layer, and the shielding layer is arranged between the thin film transistor layer and the touch electrode layer. According to the application, the shielding layer is added between the thin film transistor layer and the touch electrode layer of the touch display panel, so that the effect of shielding noise signals generated in the operation of the thin film transistor layer from interfering the touch signals of the touch electrode layer is achieved, and the signal-to-noise ratio is enhanced.
Description
Technical Field
The application relates to the technical field of display, in particular to a touch display panel and a preparation method thereof.
Background
With the development of display technology, displays with touch functions, especially small and medium-sized displays, are increasingly popular in the market. In general, a display with a touch function needs to be attached to a touch panel and a display panel, but this results in complicated process, and the display is too thick, which is not beneficial to the light and thin technology of the product. Then, in the future, there are In-Cell (On-Cell) and In-Cell (In-Cell) touch technologies, and the use of these two touch technologies greatly reduces the complexity of the process, and makes a significant contribution to the light and thin display, and the touch technology combined with the display technology does not need to separately construct a touch factory, so this technology has been greatly developed once it appears.
However, with the advent and development of OLED technology, and more, the mainstream technology, especially the flexible technology, is becoming a bottleneck for touch technology. In general, in an In-Cell touch panel, the touch unit is far away from the touch finger, and the cathode In the array substrate has a certain shielding effect on the touch signal, so that the touch signal is weaker than the conventional external touch and DOT technology; meanwhile, because the touch unit In the In-Cell touch panel is close to the thin film transistor layers In the array substrate structure, the thin film transistor layers inevitably generate a large amount of noise signals to interfere with the touch sensitivity.
Disclosure of Invention
The application provides an array substrate and a preparation method thereof, which are used for shielding interference of noise signals generated in the working of a thin film transistor layer on touch signals of a touch electrode layer, so that the signal to noise ratio is enhanced.
In order to realize the functions, the technical scheme provided by the application is as follows:
a touch display panel, comprising: a substrate, a thin film transistor layer, a light emitting device layer, and a touch electrode layer;
the touch electrode layer and the light-emitting device layer are positioned on the thin film transistor layer, and the touch electrode layer and the light-emitting device layer are arranged at intervals; wherein, the liquid crystal display device comprises a liquid crystal display device,
the touch display panel further comprises a shielding layer, and the shielding layer is arranged between the thin film transistor layer and the touch electrode layer.
In the touch display panel, the touch display panel further comprises a first flat layer, a second flat layer and an electrode layer which are sequentially positioned on the thin film transistor layer; wherein the shielding layer is located between the first planar layer and the second planar layer.
In the touch display panel, the light-emitting device layer comprises an anode, a light-emitting layer and a cathode which are stacked; the touch electrode layer comprises a laminated touch wiring, a touch connecting wire and a touch electrode;
the anode and the touch connection line are in the same layer, the cathode and the touch electrode are in the same layer, and the electrode layer and the touch wiring are in the same layer.
In the touch display panel of the present application, the touch display panel further includes a first via hole and a second via hole, wherein the first via hole exposes a part of source/drain electrodes of the thin film transistor layer and penetrates through the first planarization layer and the shielding layer; the second via hole is connected and communicated with the first via hole and penetrates through the second flat layer;
wherein the electrode layer is electrically connected with the source/drain electrode of the thin film transistor layer through the first via hole and the second via hole. The light emitting device layer is electrically connected with the electrode layer.
In the touch display panel of the application, the diameter of the opening of the first via hole corresponding to the first flat layer is smaller than that of the opening of the first via hole corresponding to the shielding layer.
In the touch display panel of the application, a gap exists between the part of the first electrode passing through the first via hole and the side wall of the shielding layer.
In the touch display panel of the application, the shielding layer is made of a metal material.
The application also provides a preparation method of the touch display panel, which comprises the following steps:
sequentially preparing a thin film transistor layer, a first flat layer and a shielding layer on a substrate;
etching the shielding layer and the first flat layer by adopting the same photomask to form a first via hole positioned above a source/drain electrode of the thin film transistor layer;
preparing a second flat layer on the shielding layer, and performing patterning treatment on the second flat layer to form a second via hole communicated with the first via hole;
and preparing a light-emitting device layer and a touch electrode layer on the second flat layer, wherein the light-emitting device layer is connected with a source/drain electrode of the thin film transistor layer through the second via hole and the first via hole, and the shielding layer is arranged between the thin film transistor layer and the touch electrode layer.
In the preparation method of the present application, the step of etching the shielding layer and the first planarization layer by using the same photomask includes:
preparing a photoresist layer on the shielding layer;
exposing the photoresist layer by using a half-tone mask plate, and then developing the photoresist layer to remove the photoresist layer corresponding to the source/drain electrodes of the thin film transistor layer;
etching the shielding layer corresponding to the source/drain electrode of the thin film transistor layer to form a first through hole exposing the first planarization layer;
exposing, developing and etching the first flat layer to remove the first flat layer corresponding to the source/drain electrode of the thin film transistor layer, and forming a second through hole connected and communicated with the first through hole;
and stripping the photoresist layer.
In the preparation method of the application, in the photomask manufacturing process, the exposure intensity of the photoresist layer is larger than that of the first flat layer, and the diameter of the first through hole is larger than that of the second through hole.
The application has the beneficial effects that: according to the application, the shielding layer is added between the thin film transistor layer and the touch electrode layer of the touch display panel, so that the effect of shielding noise signals generated in the operation of the thin film transistor layer from interfering the touch signals of the touch electrode layer is achieved, and the signal-to-noise ratio is enhanced.
Drawings
The technical solution and other advantageous effects of the present application will be made apparent by the following detailed description of the specific embodiments of the present application with reference to the accompanying drawings.
Fig. 1 is a schematic structural diagram of a touch display panel provided by the present application;
fig. 2 is a schematic structural diagram of a first touch display panel according to an embodiment of the present application;
fig. 3 is a top view of a touch display panel according to an embodiment of the application;
fig. 4 is a schematic structural diagram of a second touch display panel according to an embodiment of the present application;
fig. 5 is a flowchart illustrating steps of a method for manufacturing a touch display panel according to an embodiment of the present application;
fig. 6A to fig. 6E are schematic structural diagrams of a touch display panel according to an embodiment of the application in a manufacturing process.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application. It will be apparent that the described embodiments are only some, but not all, embodiments of the application. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to fall within the scope of the application.
In the prior art, in-Cell technology touch panels, the touch signal is weaker than the traditional external touch and DOT technology due to the fact that the touch unit is far away from the touch finger and the cathode itself In the array substrate has a certain shielding effect on the touch signal; meanwhile, because the touch unit In the In-Cell touch panel is close to the thin film transistor layers In the array substrate structure, the thin film transistor layers inevitably generate a large amount of noise signals to interfere with the touch sensitivity. Based on the above, the application provides a touch display panel and a preparation method thereof, which can solve the above-mentioned drawbacks.
Referring to fig. 1, a schematic structure diagram of a touch display panel according to the present application is shown.
In the present application, the touch display panel includes a substrate 10, a thin film transistor layer 20, a light emitting device layer 50, and a touch electrode layer 60.
The light emitting device layer 50 and the touch electrode layer 60 are located on the thin film transistor layer 20, and the light emitting device layer 50 and the touch electrode layer 60 are disposed at intervals.
The touch display panel further includes a shielding layer 80, and the shielding layer 80 is disposed between the thin film transistor layer 20 and the touch electrode layer 60.
According to the application, the shielding layer 80 is added between the thin film transistor layer 20 and the touch electrode layer 60 of the touch display panel, so that the effect of shielding noise signals generated in the operation of the thin film transistor layer 20 from interfering the touch signals of the touch electrode layer 60 is achieved, and the signal to noise ratio is enhanced.
The technical scheme of the present application will now be described with reference to specific embodiments.
Example 1
Referring to fig. 2, a schematic structural diagram of a first touch display panel according to an embodiment of the application is shown.
In this embodiment, the touch display panel includes a touch display area 100 and a non-display area 200 adjacent to the touch display area 100.
The touch display panel includes a substrate 10; a thin film transistor layer 20 disposed on the substrate 10; a light emitting device layer 50 and a touch electrode layer 60 disposed on the thin film transistor layer 20 at an interval; the touch electrode layer 60 is located in the touch display area 100.
In this embodiment, the substrate 10 includes, but is not limited to, a glass substrate and a flexible substrate.
Further, in this embodiment, the substrate 10 is a flexible and transparent PI substrate, mainly polyimide, and the PI material can effectively improve the light transmittance.
In this embodiment, the thin film transistor layer 20 is disposed on the upper surface of the substrate 10, and the thin film transistor layer 20 includes, from bottom to top, a barrier layer 21, a buffer layer 22, an active layer, a first gate insulating layer 23, a first gate, a second gate insulating layer 24, a second gate, a dielectric layer 25, and source/drain electrodes.
Note that, in the present embodiment, the thin film transistor layer 20 includes the barrier layer 21, the buffer layer 22, the active layer, the first gate insulating layer 23, the first gate electrode, the second gate insulating layer 24, the second gate electrode, the dielectric layer 25, and the source/drain electrode are only used for illustration, and the present embodiment does not limit the film structure included in the thin film transistor layer 20.
In this embodiment, the barrier layer 21, the buffer layer 22, the first gate insulating layer 23, the second gate insulating layer 24, and the dielectric layer 25 are made of an inorganic material, including one of silicon nitride, silicon oxide, and silicon oxynitride, which is not limited in this embodiment.
In this embodiment, the touch display surface further includes a first flat layer 31, a second flat layer 32, an electrode layer 41, a third flat layer 33, an anode layer 51, a pixel defining layer 70, a light emitting layer (not labeled in the figure), and a cathode layer 52 disposed on the thin film transistor layer 20.
The anode layer 51 includes an anode 511 and the touch connection line 512 that are disposed at intervals, and the cathode layer 52 includes a cathode 521 and a touch electrode 522 that are disposed at intervals.
In the present embodiment, the light emitting device layer 50 includes the anode 511, the light emitting layer, and the cathode 521 which are stacked; the touch electrode layer 60 includes a plurality of touch electrodes 522 corresponding to the touch display area 100, and the touch connection lines 512 corresponding to each of the touch electrodes 522, and a plurality of touch traces 42 extending from the touch display area 100 to the non-display area 200; the electrode layer 41 and the touch trace 42 are arranged at the same layer and at intervals.
In the present embodiment, the anode 511 is electrically connected to a source/drain electrode in the thin film transistor layer 20 through the electrode layer 41; each of the touch electrodes 522 is electrically bridged with the touch trace 42 through the touch connection line 512.
Referring to fig. 3, in this embodiment, the touch display panel further includes a touch integrated circuit 90 disposed on the substrate 10 and located in the non-display area 200, and the touch integrated circuit 90 is connected to each of the touch electrodes 522 through a plurality of the touch traces 42 and the touch connection lines 512.
In the present embodiment, the light emitting device layer 50 is electrically connected to the electrode layer 41, and the anode 51 is electrically connected to the source/drain electrode in the thin film transistor layer 20 through the electrode layer 41; the electrode layer 41 is used to input a display signal to the corresponding anode 511 when the touch display panel displays a time period.
The cathode layer 50 includes a cathode 521 and a plurality of touch electrodes 522 corresponding to the display area, where the touch electrodes 522 are electrically connected to the touch trace 42 through the touch connection lines 512, and the touch trace 42 is configured to input a touch signal to the corresponding touch electrode 522 when the touch display panel is in a touch time period, so as to realize touch.
It is to be understood that the number of the electrode layers 41, the number of the touch traces 42, the number of the anodes 511, the number of the touch connection lines 512, the number of the cathodes 521 and the number of the touch electrodes 522 may be designed according to actual needs, and are not limited in this embodiment.
In this embodiment, the touch display panel further includes a shielding layer 80, where the shielding layer 80 is disposed between the thin film transistor layer 20 and the touch electrode layer 60, and further, the shielding layer 80 is located between the first flat layer 31 and the second flat layer 32.
In this embodiment, the material of the shielding layer 80 is a metal material with a signal shielding function, and further, in this embodiment, the shielding layer 80 is a laminated structure of titanium/aluminum/titanium.
It is understood that the shielding layer 80 is a titanium/aluminum/titanium laminate structure for illustration only, and the present embodiment is not limited thereto.
In this embodiment, a shielding layer 80 is added between the tft layer 20 and the touch electrode layer 60 of the touch display panel, so as to play a role in shielding noise signals generated in the operation of the tft layer 20 from interfering with touch signals of the touch electrode layer 60, thereby enhancing the signal-to-noise ratio.
In this embodiment, the touch display panel further includes a first via 311, a second via 321, a third via 331, and a fourth via 701; the first via hole 311 exposes a portion of the source/drain electrode of the thin film transistor layer 20; the second via 321 is connected and communicated with the first via 311; the third via 331 exposes a portion of the electrode layer 41 and exposes a portion of the touch trace 42; the fourth via 701 exposes a portion of the touch connection line 512 and a portion of the anode 511.
Wherein the electrode layer 41 is electrically connected to the source/drain electrode of the thin film transistor layer 20 through the first via 311 and the second via 321, and the light emitting device layer 50 is electrically connected to the electrode layer 41; wherein, a gap exists between the portion of the electrode layer 41 passing through the first via hole 311 and the side wall of the shielding layer 80.
In this embodiment, the diameter of the first via hole 311 corresponding to the first flat layer 31 is smaller than the diameter of the first via hole 311 corresponding to the shielding layer 80, and the diameter of the second via hole 321 is equal to the diameter of the first via hole 311 corresponding to the first flat layer 31, and when the electrode layer 41 is electrically connected to the source/drain electrode of the thin film transistor layer 20 through the second via hole 321 and the first via hole 311, the electrode layer 41 is insulated from the shielding layer and is disposed at a distance, so that it is possible to ensure the reliability of the wiring, that is, to avoid the phenomenon that the electrode layer 41 is not in contact with the shielding layer 80 when the electrode layer 41 is used to input a display signal to the corresponding anode 511 during a display period, and thus a short circuit is found.
Referring to fig. 4, a schematic structural diagram of a second touch display panel according to an embodiment of the application is shown.
In this embodiment, the structure of the touch display panel is similar to/the first schematic structure of the touch display panel provided in the above embodiment, please refer to the description of the touch display panel in the above embodiment, and the difference between the two is that:
in this embodiment, the projection of the shielding layer 80 on the substrate 10 is located in the touch display area 100, so as to avoid the negative influence of the shielding layer 80 on the components in the non-display area 200.
Example two
Referring to fig. 5, a flowchart of steps of a method for manufacturing a touch display panel according to an embodiment of the application is shown.
In this embodiment, the touch display panel includes a touch display area 100 and a non-display area 200 adjacent to the touch display area 100.
The preparation method of the touch display panel comprises the following steps:
step S10: a thin film transistor layer 20, a first planarization layer 31, and a shielding layer 80 are sequentially prepared on the substrate 10, as shown in fig. 6A.
In this embodiment, the step S10 includes the steps of:
step S11: a substrate 10 is provided, the substrate 10 including, but not limited to, a glass substrate and a flexible substrate.
Further, in this embodiment, the substrate 10 is a flexible and transparent PI substrate, mainly polyimide, and the PI material can effectively improve the light transmittance.
Step S12: a barrier layer 21, a buffer layer 22, an active layer, a first gate insulating layer 23, a first gate electrode, a second gate insulating layer 24, a second gate electrode, a dielectric layer 25, source/drain electrodes, a first planarization layer 31, and a shielding layer 80 are sequentially prepared on the substrate 10.
The materials used for the barrier layer 21, the buffer layer 22, the first gate insulating layer 23, the second gate insulating layer 24, and the dielectric layer 25 are inorganic materials, including one of silicon nitride, silicon oxide, and silicon oxynitride, which is not limited in this embodiment.
The material of the shielding layer 80 is a metal material with a signal shielding function, and further, in this embodiment, the shielding layer 80 is a laminated structure of titanium/aluminum/titanium.
Step S20: the shielding layer 80 and the first planarization layer 31 are etched using the same photomask to form a first via hole 311 over the source/drain electrode of the thin film transistor layer 20, as shown in fig. 6B.
In this embodiment, the step 20 includes the steps of:
step S21: a photoresist layer is prepared on the shielding layer 80.
Step S22: the photoresist layer is exposed using a halftone mask plate, and then developed, and the photoresist layer corresponding to the source/drain electrodes of the thin film transistor layer 20 is removed.
Step S23: the shielding layer 80 corresponding to the source/drain electrode of the thin film transistor layer 20 is etched to form a first via hole exposing the first planarization layer 31.
Step S23: the first planarization layer 31 is exposed, developed and etched, the first planarization layer 31 corresponding to the source/drain electrode of the thin film transistor layer 20 is removed, and a second via hole connected and communicating with the first via hole is formed, and the first via hole and the second via hole constitute the first via hole 311.
Step S24: and stripping the photoresist layer.
In step S22, in the mask process, the exposure intensity of the photoresist layer is greater than that of the first planarization layer 31, so that the diameter of the first via hole is greater than that of the second via hole, that is, the diameter of the opening of the first via hole 311 corresponding to the first planarization layer 31 is smaller than that of the opening of the first via hole 311 corresponding to the shielding layer 80.
It will be appreciated that in this embodiment, the exposure intensity of the photoresist layer and the exposure intensity of the first planarization layer 31 may be selected according to actual needs, and are not limited in this embodiment.
In this embodiment, the method further includes performing a photomask process on the shielding layer 80, and removing the shielding layer 80 in the non-display area 200 through exposure, development and etching, so as to avoid negative effects of the shielding layer 80 on components in the non-display area 200.
Step S30: a second planarization layer 32 is prepared on the shielding layer 80, and the second planarization layer 32 is patterned to form a second via 321 connected and communicated with the first via 311, as shown in fig. 6C.
In this embodiment, the diameter of the second via 321 is equal to the diameter of the opening of the first via 311 corresponding to the first flat layer 31.
Step S40: a light emitting device layer 50 and a touch electrode layer 60 are prepared on the second planarization layer 32, and the light emitting device layer 50 is connected to the source/drain electrode of the thin film transistor layer 20 through the second via 321 and the first via 311, and the shielding layer 80 is disposed between the thin film transistor layer 20 and the touch electrode layer 60, as shown in fig. 6E.
In this embodiment, the step 40 includes the steps of:
step S41: a metal layer is prepared on the second planarization layer 32, and the metal layer is patterned to form an electrode layer 41 and a touch trace 42, as shown in fig. 6D.
In this embodiment, the material of the metal layer includes, but is not limited to, metals such as aluminum, molybdenum, titanium, copper, and alloys thereof; the electrode layer 41 is electrically connected to the source/drain electrode of the thin film transistor layer 20 through the second via 321 and the first via 311, and a gap exists between a portion of the electrode layer 41 passing through the first via 311 and the sidewall of the shielding layer 80.
Step S42: a third planarization layer 33, an anode layer 51, a pixel defining layer 70, a light emitting layer, and a cathode layer 52 are sequentially prepared on the electrode layer 41.
In this embodiment, the step S42 includes the steps of:
step S421: preparing a third flat layer 33 on the electrode layer 41, and patterning the third flat layer 33 to form a third via 331 above the electrode layer 41 and the touch trace 42; the third via 331 exposes a portion of the electrode layer 41 and exposes a portion of the touch trace 42.
Step S422: an anode layer 51 is prepared on the third flat layer 33, and the anode layer 51 is patterned to form anodes 511 and touch connection lines 512 which are arranged at intervals.
In the third via 331, the thin film transistor layer 20 is electrically connected to the electrode layer 41, and further, the anode 511 is electrically bridged by the electrode layer 41 to the source/drain electrode of the thin film transistor layer 20; the touch connection line 512 is electrically connected to the touch trace 42 through the third via 331.
Step S423: preparing a pixel defining layer 70 on the anode layer 51, and patterning the pixel defining layer 70 to form a fourth via 701 on the anode 511 and the touch connection line 512; the fourth via 701 exposes a portion of the anode 511 and a portion of the touch connection line 512.
Step S424: a light emitting layer is prepared on the pixel defining layer 70, and the light emitting layer is electrically connected to the anode 511 through the fourth via 701.
Step S425: a cathode layer 52 is prepared on the pixel defining layer 70 and the light emitting layer, and the cathode layer 52 is patterned to form a cathode 521 and a plurality of touch electrodes 522 corresponding to the touch display area 100, which are disposed at intervals.
In this embodiment, the cathode 521, the light emitting layer, and the anode 511 are in one-to-one correspondence; in the second via 321 and the first via 311, each touch electrode 522 is electrically bridged to the corresponding touch trace 42 through the touch connection line 512, so as to realize touch.
In the present embodiment, the shapes of the first via 311, the second via 321, the third via 331, and the fourth via 701 include, but are not limited to, circular hole shapes.
It can be appreciated that in this embodiment, the thickness of each film layer may be designed according to actual needs, where when the first flat layer 31 and the second flat layer 32 are prepared, the total thickness of the first flat layer 31 and the second flat layer 32 may be controlled to be the same as the thickness of the flat layer in the prior art, that is, in this embodiment, a shielding layer 80 may be prepared between the first flat layer 31 and the second flat layer 32 without increasing the thickness of the touch display panel, which plays a role in shielding interference of noise signals generated in the operation of the thin film transistor layer on touch signals of the touch electrode layer, thereby enhancing the signal-to-noise ratio.
In this embodiment, the method for manufacturing a touch display panel further includes:
step S50: preparing a touch integrated circuit on the substrate, wherein the touch integrated circuit is positioned in the non-display area; the touch integrated circuit is connected with each touch electrode through a plurality of touch wires and touch connecting wires.
The application provides a touch display panel and a preparation method thereof, wherein the touch display panel comprises a substrate, a thin film transistor layer, a light emitting device layer and a touch electrode layer; the touch electrode layer and the light-emitting device layer are positioned on the thin film transistor layer, and the touch electrode layer and the light-emitting device layer are arranged at intervals; the touch display panel further comprises a shielding layer, and the shielding layer is arranged between the thin film transistor layer and the touch electrode layer.
According to the application, the shielding layer is added between the thin film transistor layer and the touch electrode layer of the touch display panel, so that the interference effect of noise signals generated in the operation of the thin film transistor layer on touch signals of the touch electrode layer is achieved, and the signal-to-noise ratio is enhanced.
In the foregoing embodiments, the descriptions of the embodiments are emphasized, and for parts of one embodiment that are not described in detail, reference may be made to related descriptions of other embodiments.
The above describes in detail a touch display panel and a method for manufacturing the same provided by the embodiment of the present application, and specific examples are applied to describe the principle and implementation of the present application, and the description of the above embodiment is only used to help understand the technical solution and core idea of the present application; those of ordinary skill in the art will appreciate that: the technical scheme described in the foregoing embodiments can be modified or some technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit of the application.
Claims (9)
1. A touch display panel, the touch display panel comprising:
a substrate, a thin film transistor layer, a light emitting device layer, and a touch electrode layer;
the touch electrode layer and the light-emitting device layer are positioned on the thin film transistor layer, and the touch electrode layer and the light-emitting device layer are arranged at intervals; wherein, the liquid crystal display device comprises a liquid crystal display device,
the touch display panel further comprises a first flat layer, a second flat layer, an electrode layer and a third flat layer which are sequentially positioned between the thin film transistor layer and the light-emitting device layer;
the touch display panel further comprises a shielding layer, wherein the shielding layer is positioned between the first flat layer and the second flat layer.
2. The touch display panel according to claim 1, wherein the light-emitting device layer comprises an anode, a light-emitting layer, and a cathode, which are stacked; the touch electrode layer comprises a laminated touch wiring, a touch connecting wire and a touch electrode;
the anode and the touch connection line are in the same layer, the cathode and the touch electrode are in the same layer, and the electrode layer and the touch wiring are in the same layer.
3. The touch display panel of claim 2, further comprising a first via and a second via, the first via exposing a portion of the source/drain electrode of the thin film transistor layer and penetrating the first planarization layer and the shielding layer; the second via hole is connected and communicated with the first via hole and penetrates through the second flat layer;
the electrode layer is electrically connected with the source/drain electrode of the thin film transistor layer through the first via hole and the second via hole, and the light emitting device layer is electrically connected with the electrode layer.
4. The touch display panel of claim 3, wherein a diameter of the opening of the first via corresponding to the first flat layer is smaller than a diameter of the opening of the first via corresponding to the shielding layer.
5. The touch display panel of claim 4, wherein a gap exists between a portion of the electrode layer passing through the first via and the shield layer sidewall.
6. The touch display panel of claim 1, wherein the shielding layer is made of a metal material.
7. The preparation method of the touch display panel is characterized by comprising the following steps of:
sequentially preparing a thin film transistor layer, a first flat layer and a shielding layer on a substrate;
etching the shielding layer and the first flat layer by adopting the same photomask to form a first via hole positioned above a source/drain electrode of the thin film transistor layer;
preparing a second flat layer on the shielding layer, and performing patterning treatment on the second flat layer to form a second via hole communicated with the first via hole;
and preparing a light-emitting device layer and a touch electrode layer on the second flat layer, wherein the light-emitting device layer is connected with a source/drain electrode of the thin film transistor layer through the second via hole and the first via hole, and the shielding layer is arranged between the thin film transistor layer and the touch electrode layer.
8. The method of claim 7, wherein the step of etching the shielding layer and the first planarization layer using the same photomask comprises:
preparing a photoresist layer on the shielding layer;
exposing the photoresist layer by using a half-tone mask plate, and then developing the photoresist layer to remove the photoresist layer corresponding to the source/drain electrodes of the thin film transistor layer;
etching the shielding layer corresponding to the source/drain electrode of the thin film transistor layer to form a first through hole exposing the first planarization layer;
exposing, developing and etching the first flat layer to remove the first flat layer corresponding to the source/drain electrode of the thin film transistor layer, and forming a second through hole connected and communicated with the first through hole;
and stripping the photoresist layer.
9. The method of claim 8, wherein in the masking process, an exposure intensity of the photoresist layer is greater than an exposure intensity of the first planarization layer, and a diameter of the first via hole is greater than a diameter of the second via hole.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202011451170.3A CN112582381B (en) | 2020-12-10 | 2020-12-10 | Touch display panel and preparation method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202011451170.3A CN112582381B (en) | 2020-12-10 | 2020-12-10 | Touch display panel and preparation method thereof |
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| CN113745241B (en) * | 2021-07-30 | 2022-09-27 | 惠科股份有限公司 | Array substrate and manufacturing method thereof, display panel and control method thereof, and display device |
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