JP4136510B2 - Manufacturing method of semiconductor memory device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a method for manufacturing a semiconductor memory device, and more particularly to a technique effective when applied to a method for setting a write voltage and an erase voltage of a memory cell of the device.
[0002]
[Prior art]
For example, as a technique studied by the present inventor, in a semiconductor memory device such as a flash memory, a probe inspection is performed after a wafer processing process. In this probe inspection, an electrical characteristic test at a normal temperature and a high temperature state, writing and erasing are performed. The speed is measured. When measuring the writing and erasing speed, it is necessary to set a voltage, and the internal voltage for writing and erasing the memory cell is set to a constant value based on an empirical value. .
[0003]
As a technique related to such a semiconductor memory device such as a flash memory, for example, a technique described in “Advanced Electronics I-9 VLSI Memory” issued on November 5, 1994, published by Bafukan Co., Ltd., and the like can be mentioned.
[0004]
[Problems to be solved by the invention]
By the way, as a result of examination of the technique of the internal voltage setting method for writing and erasing the memory cell as described above, the following has been clarified.
[0005]
For example, due to process variations such as film thickness in the wafer processing step, the write and erase characteristics of the memory cells may vary greatly between wafers or within the wafer surface.
[0006]
However, since the programming and erasing voltage of the memory cell is set to a constant value based on empirical values, the fluctuation causes the programming and erasing speed of the memory cell between chips or in the chip to fluctuate, resulting in the product yield and quality. It is thought that it falls.
[0007]
Therefore, in order to improve the yield and quality of the product, it is necessary to correct variations in the write and erase characteristics of the memory cell.
[0008]
Therefore, an object of the present invention is to set the internal voltage for writing and erasing to an optimum value even in the case where the writing and erasing characteristics of the memory cell fluctuate due to process variations in a semiconductor memory device such as a flash memory. Thus, the present invention provides a method for manufacturing a semiconductor memory device capable of keeping the writing and erasing speed constant.
[0009]
The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.
[0010]
[Means for Solving the Problems]
Of the inventions disclosed in the present application, the outline of typical ones will be briefly described as follows.
[0011]
That is, the method for manufacturing a semiconductor memory device according to the present invention includes a first step of measuring a threshold voltage before writing of a memory cell of the semiconductor memory device, and applying a voltage to the memory cell to write the memory cell. A second step of performing, a third step of measuring a threshold voltage of the memory cell after the writing, a fourth step of erasing the memory cell by applying a voltage to the memory cell, A fifth step of measuring a threshold voltage of the memory cell after erasing and a sixth step of setting an internal voltage of the semiconductor memory device based on the measurement results It is.
[0012]
The method of manufacturing a semiconductor memory device according to the present invention further includes performing the voltage application and the measurement on a plurality of the memory cells, and setting an optimum internal voltage of the semiconductor memory device based on the measurement result. It is a feature.
[0013]
The method of manufacturing a semiconductor memory device according to the present invention further includes arranging measured values of the plurality of memory cells in ascending order and setting an optimum internal voltage of the semiconductor memory device based on an intermediate value thereof. It is what.
[0014]
In the method of manufacturing a semiconductor memory device according to the present invention, the first to sixth steps are further performed by probe inspection.
[0015]
In the method of manufacturing a semiconductor memory device according to the present invention, the semiconductor memory device is a flash memory.
[0016]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
[0017]
FIG. 1 is a block diagram showing an example of a semiconductor memory device such as a flash memory manufactured by the manufacturing method of the present invention, and FIG. 2 is a method for manufacturing a semiconductor memory device such as a flash memory according to an embodiment of the present invention. FIG. 3 is a flow chart showing a method for setting a write and erase voltage of a memory cell, FIG. 3 is a view showing a position of a memory cell in a chip to which a write and erase voltage is applied and measured, and FIG. FIG. 5 is a diagram showing a change state of the threshold voltage of the memory cell, and FIG. 6 is a graph used for calculating optimum write and erase voltages.
[0018]
First, an example of the configuration of a semiconductor memory device manufactured by the manufacturing method of the present invention will be described with reference to FIG.
[0019]
The semiconductor memory device manufactured by the manufacturing method of the present invention is a flash memory such as 64M, 256M, and 512Mb (bit), for example, and includes a memory mat 1, a main decoder / gate decoder 2, a sub decoder 3, and a sense latch circuit 4. , Data latch circuit 5, main amplifier 6, input data arithmetic circuit 7, input / output buffer 8, control signal input buffer 9, data input / output control circuit 10, ready / busy circuit 11, system clock circuit 12, status register test system circuit 13, command decoder 14, ROM control system circuit 15, ROM 16, ROM decoder 17, CPU 18, power supply control circuit 19, power supply switching circuit 20, charge pump step-down system circuit 21, reference power supply 22, address counter 23, relief system circuit 24, Address generator 25, redundant fuse Made from the general structure of such's trimming fuse 26 is formed on one semiconductor chip by a known semiconductor manufacturing technique.
[0020]
In this flash memory, control signals such as a chip enable signal / CE, a write enable signal / WE, a reset signal / RES, a command data enable signal / CDE, and an output enable signal / OE are sent to the control signal input buffer 9 via an external terminal. The serial clock signal SC is input to the data input / output control circuit 10, and a command and timing signal for controlling the internal circuit are generated based on these signals. A ready / busy signal R / B is output from the ready / busy circuit 11 via an external terminal.
[0021]
In this flash memory, the memory mat 1 is composed of a plurality of memory cells MC arranged at the intersections of the word lines WL and the bit lines BL, and is divided into four in the horizontal and vertical directions. Arbitrary memory cells MC in the memory mat 1 are selected by the main decoder / gate decoder 2 and the sub-decoder 3, and a sense latch circuit 4, a data latch circuit 5, a main amplifier are selected for the selected memory cells MC. 6. Data is written / read through the input data operation circuit 7 and the input / output buffer 8.
[0022]
In the flash memory configured as described above, voltages applied to the memory cells for writing and erasing of the memory cells MC are the power supply control circuit 19, the power supply switching circuit 20, the charge pump step-down circuit 21, the reference voltage 22, and the like. Supplied from
[0023]
The values of these internal voltages are adjusted by trimming the redundant fuse / trimming fuse 26 in accordance with a programming and erasing voltage setting method described later.
[0024]
Next, an example of a method for setting the write and erase voltage (internal voltage) of the memory cell MC in the present embodiment will be described with reference to FIG.
[0025]
The method of setting the write and erase voltage (internal voltage) of the memory cell MC in the present embodiment includes, for example, a step of measuring the threshold voltage Vthi before writing of the memory cell MC (step S30), and writing of the memory cell MC (Step S31), measuring the threshold voltage Vthw after writing (step S32), erasing the memory cell MC (step S33), measuring the threshold voltage Vthe after erasing (Step S34), a step of calculating a write threshold voltage Vthwi and an erase threshold voltage Vthwe (Step S35), a standard write threshold voltage Vthwi (typ) and a standard erase threshold voltage Vthwe (typ) Step (step S36), an optimum internal voltage setting step (step S37), and the like.
[0026]
In addition, these steps are performed in a probe inspection after the wafer processing step in the semiconductor memory device manufacturing process.
[0027]
In the step of measuring the threshold voltage Vthi before writing to the memory cell MC (step S30), a plurality of memory cells MC in the chip 40 to be measured, for example, five memory cells MC as shown in FIG. (A) to MC (E) are selected, and initial states, that is, threshold voltages Vthi (A) to Vthi (E) before writing are measured for them. The position of the memory cell MC to be measured is preferably selected in a well-balanced manner over the entire chip 40 as shown in FIG.
[0028]
Next, in the step of writing the memory cell (step S31), a voltage necessary for writing is applied from the outside to the memory cells MC (A) to MC (E).
[0029]
FIG. 4 shows the vertical structure and voltage application position of the memory cell MC. The memory cell MC includes a control gate 41, a floating gate 42, a drain 43, a source 44, a well 45, and the like. The control gate 41 has a gate voltage Vg, the drain 43 has a drain voltage Vd, a source 44 has a source voltage Vs, and a well 45. By applying the well voltage Vwell to the memory cell, electrons are accumulated in the floating gate 42 and the memory cell MC is written.
[0030]
For example, 18.6 V is applied as the gate voltage Vg, 0 V is applied as the drain voltage Vd, 0 V is applied as the source voltage Vs, and 0 V is applied as the well voltage Vwell. By applying this voltage, as shown in FIG. 5, the threshold voltages Vthi (A) to Vthi (E) of the memory cells MC (A) to MC (E) are changed to the threshold voltage Vthw (A ) To Vthw (E).
[0031]
Next, in the step of measuring the threshold voltage Vthw of the memory cell after writing (step S32), the threshold voltages Vthw (A) to Vthw (after writing of the memory cells MC (A) to MC (E)). E) is measured.
[0032]
Next, in the step of erasing the memory cell MC (step S33), voltages necessary for erasing, that is, the gate voltage Vg, the drain voltage Vd, the source voltage Vs, are applied to the memory cells MC (A) to MC (E). A well voltage Vwell is applied from the outside.
[0033]
For example, −17.5 V is applied as the gate voltage Vg, 0 V is applied as the drain voltage Vd, 0 V is applied as the source voltage Vs, and 0 V is applied as the well voltage Vwell. By applying this voltage, as shown in FIG. 5, the threshold voltages Vthw (A) to Vthw (E) of the memory cells MC (A) to MC (E) are changed to the threshold voltage Vthe (A after erase). ) To Vthe (E).
[0034]
Next, in the step of measuring the threshold voltage Vthe after erasure (step S34), the threshold voltages Vthe (A) to Vthe (E) after erasure of the memory cells MC (A) to MC (E) are obtained. taking measurement.
[0035]
Next, in the step of calculating the write threshold voltage Vthwi and the erase threshold voltage Vthwe (step S35), the threshold voltages Vthi (A) to Vthi (E) before writing measured in the above steps are written. Based on the results of the subsequent threshold voltages Vthw (A) to Vthw (E) and the erased threshold voltages Vthe (A) to Vthe (E), the write threshold voltage Vthwi and An erase threshold voltage Vthwe is calculated.
[0036]
Vthwi = Vthw−Vthi
Vthwe = Vthw−Vthe
However, in the above equation, (A) to (E) indicating the position of the memory cell MC to be measured are omitted, and Vthwi (A) to (E) are all applied to the memory cells MC (A) to MC (E). ), Vthwe (A) to (E) are calculated.
[0037]
Next, in the step of calculating the standard write threshold voltage Vthwi (typ) and the standard erase threshold voltage Vthwe (typ) (step S36), the write threshold voltages Vthwi (A) to (E) and the erase are performed. The threshold voltages Vthwe (A) to (E) are arranged in ascending order, and the intermediate value, that is, the third value, is the standard write threshold voltage Vthwi (typ) and standard erase threshold voltage Vthwe (typ) of the target chip. And
[0038]
Finally, in the step of setting the optimum internal voltage (step S37), for example, based on the standard write threshold voltage Vthwi (typ) and the standard erase threshold voltage Vthwe (typ) calculated in the above step, for example Using the graph shown in FIG. 6, the optimum gate voltage Vgw at the time of writing and gate voltage Vge at the time of erasing of the target chip 40 are obtained, and the internal voltage is set.
[0039]
FIG. 6A is a graph showing the relationship between the write threshold voltage Vthwi and the gate voltage Vg at the write speed required for the product, and FIG. 6B is the erase required for the product. It is a graph which shows the relationship between the erase threshold voltage Vthwe and the gate voltage Vg in speed.
[0040]
In setting the internal voltage, the redundant fuse / trimming fuse 26 is trimmed so that the value of the internal voltage in the chip 40 becomes the calculated gate voltage Vgw at the time of writing and gate voltage Vge at the time of erasing.
[0041]
Therefore, according to the method for setting the write and erase voltages (internal voltage) of the memory cell MC in the present embodiment, the internal voltage is set to the optimum value for each chip 40, and the write and erase of the memory cell MC are performed. Even when the characteristics fluctuate, it is possible to keep the writing and erasing speed seen from the outside constant.
[0042]
As a result, product yield and quality are improved.
[0043]
As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.
[0044]
For example, in the above-described embodiment, voltage application and measurement are performed at five points of the memory cells MC (A) to (E) in the chip, but the present invention is not limited to this, and voltage application and measurement are performed. The position to perform may be 4 points or less or 6 points or more.
[0045]
In the embodiment, the write threshold voltages Vthwi (A) to (E) and the erase threshold voltages Vthwe (A) to (E) are arranged in ascending order, and the intermediate value, that is, the third The values are the standard write threshold voltage Vthwi (typ) and the standard erase threshold voltage Vthwe (typ) of the target chip. However, the present invention is not limited to this, and other methods, for example, the average of the respective values The standard write threshold voltage Vthwi (typ) and the standard erase threshold voltage Vthwe (typ) may be calculated from the values and the like.
[0046]
In the above embodiment, the flash memory as the semiconductor memory device has been described. However, the present invention is not limited to this, and the present invention can also be applied to EPROM and other memories.
[0047]
【The invention's effect】
Of the inventions disclosed in the present application, effects obtained by typical ones will be briefly described as follows.
[0048]
(1) Even when the writing and erasing characteristics of the memory cell fluctuate due to process variations, the writing and erasing speed seen from the outside can be kept constant by setting the internal voltage to an optimum value. Become.
[0049]
(2) Product yield and quality can be improved.
[Brief description of the drawings]
FIG. 1 is a configuration diagram showing an example of a semiconductor memory device manufactured by a manufacturing method of the present invention.
FIG. 2 is a flowchart showing a method for setting a write and erase voltage of a memory cell in a method for manufacturing a semiconductor memory device according to an embodiment of the present invention;
FIG. 3 is a diagram showing a position in a chip of a memory cell that performs voltage application and measurement in an embodiment of the present invention.
FIG. 4 is a configuration diagram showing a vertical structure of a memory cell of a flash memory in an embodiment of the present invention.
FIG. 5 is a diagram showing a change state of a threshold voltage of a memory cell in an embodiment of the present invention.
FIG. 6 is a graph used to calculate an optimum write voltage and (b) to calculate an optimum erase voltage in an embodiment of the present invention.
[Explanation of symbols]
1 Memory Mat 2 Main Decoder / Gate Decoder 3 Sub Decoder 4 Sense Latch Circuit 5 Data Latch Circuit 6 Main Amplifier 7 Input Data Operation Circuit 8 Input / Output Buffer 9 Control Signal Input Buffer 10 Data Input / Output Control Circuit 11 Ready / Busy Circuit 12 System Clock circuit 13 Status register test system circuit 14 Command decoder 15 ROM control system circuit 16 ROM
17 ROM decoder 18 CPU
19 power supply control circuit 20 power supply switching circuit 21 charge pump step-down circuit 22 reference power supply 23 address counter 24 relief system circuit 25 address generator 26 redundant fuse / trimming fuse 40 chip 41 control gate 42 floating gate 43 drain 44 source 45 well MC, MC (A), MC (B), MC (C), MC (D), MC (E) Memory cell BL Bit line WL Word line Vg Gate voltage Vd Drain voltage Vs Source voltage Vwell Well voltage Vth Threshold voltage Vthi Write Previous threshold voltage Vthw Threshold voltage after programming Vthe Erase threshold voltage Vthwi Programming threshold voltage Vthwe Erase threshold voltage Vthwi (typ) Standard programming threshold voltage Vthwe (typ) Standard erase Threshold voltage Vgw Optimal write gate voltage Vge Optimal erase Gate voltage

Claims (2)

A first step of measuring a threshold voltage before writing in a plurality of memory cells of a semiconductor memory device;
A voltage is applied to the plurality of memory cells, a second step of writing said plurality of memory cells,
A third step of measuring threshold voltages of the plurality of memory cells after the writing;
Wherein a voltage is applied to the plurality of memory cells, a fourth step of erasing said plurality of memory cells,
A fifth step of measuring threshold voltages of the plurality of memory cells after erasure;
The measurement results of the plurality of memory cells based on the first, third, and fifth steps are arranged in ascending order, and an optimum internal voltage of the semiconductor memory device is set based on an intermediate value thereof It possesses a step,
Wherein said first to sixth steps, a method of manufacturing a semiconductor memory device according to claim Rukoto place at probe test. A method of manufacturing a semiconductor memory device according to claim 1,
The semiconductor memory device manufacturing method of the semiconductor memory device according to claim flash memory der Rukoto.

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