JP4136255B2 - Image processing apparatus and method - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to an image processing apparatus and method, and more particularly to an image processing apparatus and method for generating a reduced image from a Bayer array image.
[0002]
[Prior art]
In general, in an imaging apparatus such as a digital still camera or a digital video camera, image data of a subject photographed and output by the imaging sensor is an RGB Bayer array in the primary color system. This RGB Bayer array is an array that detects RG / BG signals or BG / RG signals from odd / even scanning lines by arranging Gs that are important in terms of resolution in a checkered pattern. As types of the Bayer array, four types shown in FIGS. 2A to 2D are common.
[0003]
As a method for reducing RGB image data having such a Bayer array, other two elements (color components) that do not exist in the target pixel are linearly or adaptively interpolated using peripheral pixels for each of RGB. How to do is well known.
[0004]
However, if the output image size is sufficiently reduced by performing a thinning process on the input image size, from the viewpoint of hardware limitations and input / output latency rather than the generated image quality, An RGB image may be created based on the Bayer array input without interpolating pixels. A specific example of this method will be described below with reference to FIG.
[0005]
FIG. 3 is a diagram showing a configuration of a conventional reduced image generation circuit. According to this configuration, the multi-stage low-pass filter (hereinafter referred to as LPF) process and the pixel thinning process are performed in the horizontal and vertical directions for each of the RGB pixels of the Bayer array image input for each line. Gradually reduce the original image size.
[0006]
Reference numeral 302 shown in FIG. 3 denotes a reduction unit that realizes generation of an RGB reduced thumbnail image. In the input Bayer array image, horizontal high-frequency components are cut by the horizontal LPF 302. The horizontal thinning unit 304 samples pixels in the horizontal direction at a desired interval, thereby creating a primary image in which the horizontal direction is reduced. Further, the same processing as in the horizontal direction is performed in the vertical LPF 305 and the vertical thinning unit 306 in the next stage, thereby generating an image reduced in both the horizontal and vertical directions.
[0007]
By repeating this horizontal and vertical LPF processing and thinning processing a plurality of times, that is, by providing a plurality of reduction units, it was possible to generate and output an RGB image having a desired reduction ratio from the input image size. .
[0008]
[Problems to be solved by the invention]
However, the conventional reduced image generation circuit needs to include more reduction units as the reduction ratio increases.
[0009]
If the LPF having a sufficient number of stages according to the reduction ratio and the processing by the thinning unit cannot be performed, moire occurs in the generated reduced image, and the image quality is significantly deteriorated.
[0010]
In addition, when image data is input line-sequentially, a tap memory for realizing the LPF in the vertical direction is necessary, and there is a problem that the memory capacity to be provided becomes enormous.
[0011]
Further, when the reduced image generation process is realized by hardware as described above, the number of filter stages is fixed, so that the range of reduction ratios that can be processed is limited and the versatility is poor.
[0012]
Here, in addition to the reduction method using the LPF as described above, a method of generating a reduced image by a region integration method as shown in FIG. 4 is also known. According to this method, a reduced size image is obtained by spreading a matrix of a fixed size (9 × 9 in this case) on each RGB plane, averaging the matrix units, and outputting them as one pixel.
[0013]
However, even in this method, depending on the relationship between the input image size and the output image size, many pixels that are not subject to matrix processing may be generated both horizontally and vertically, and input information cannot be used sufficiently. There was a problem. In the example shown in FIG. 4, the horizontal / vertical 42/28 pixels are discarded.
[0014]
Therefore, when performing reduction using the region integration method, if you try to eliminate pixels that are not subject to matrix processing, the control of the matrix size, the calculation method at the time of averaging, etc. will be complicated, so it will be realized in hardware. It was very difficult to do.
[0015]
The present invention has been made to solve the above-described problems, and provides an image processing apparatus and method capable of generating a high-quality reduced image with a small memory capacity from an original image having a Bayer array. The purpose is to do.
[0016]
[Means for Solving the Problems]
As a means for achieving the above object, an image processing apparatus of the present invention comprises the following arrangement.
[0017]
That is, an image processing apparatus that inputs image data in which each component forms a Bayer array and outputs the reduced image data, and a separation unit that separates the image data in which each component forms a Bayer array into planes for each component Matrix determining means for determining the horizontal and vertical sizes of the matrix for each plane based on the horizontal and vertical reduction ratios of the image data, and the matrix determined by the matrix determining means for each plane. Horizontal averaging means for integrating and averaging the image data in the horizontal direction based on the horizontal size of the image, and the image data averaged in the horizontal direction in the horizontal averaging means for each plane Vertical averaging means for integrating and averaging in the vertical direction based on the vertical direction size, and in the vertical direction in the vertical averaging means The disproportionation image data of each plane has, and having and an output means for sequentially outputting points in accordance with the Bayer array.
[0018]
The image processing apparatus further includes a holding unit that holds one line of image data of each plane averaged in the vertical direction by the vertical averaging unit, and the output unit is held by the holding unit according to the Bayer arrangement. The image data of each plane is output dot-sequentially by reading out the image data.
[0019]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, an embodiment according to the present invention will be described in detail with reference to the drawings.
[0020]
FIG. 1 is a block diagram showing a configuration of a reduced image creation circuit in the present embodiment. Hereinafter, each configuration will be described in detail.
[0021]
[RGB separation circuit 102]
An image having any one of the four types of Bayer arrays shown in FIG. 2 is sequentially input to the RGB separation circuit 102 in units of lines in the horizontal direction. However, a 2-bit identification signal indicating which Bayer array shown in FIG. 2 is input to the RGB separation circuit 102 needs to be input as a parameter. The RGB separation circuit 102 outputs a synchronization signal indicating which component of R, G, and B the data at the current timing is.
[0022]
[Arbitrary Size Integration Matrix Generation Unit 106]
The arbitrary size integration matrix generation unit 106 receives the output synchronization signal from the RGB separation circuit 102 and outputs the respective pulse signals MAT_H and R_MAT_CLR indicating the right end column and the lower right end of each integration matrix shown in FIG.
[0023]
Here, FIG. 5 shows an example of the RB plane particularly in the case where the input image is a Bayer array composed of 3000 pixels in the horizontal direction and 2000 pixels in the vertical direction, and the output thumbnail image size is 162 pixels in the horizontal direction and 108 pixels in the vertical direction. It is. That is, the number of pixels to be processed in the RB plane is 1500/1000 pixels in the horizontal / vertical directions, respectively, due to the characteristics of the Bayer array. The G plane is 1500/2000 pixels.
[0024]
The arbitrary size integration matrix generation unit 106 determines the reduction ratio in the horizontal / vertical direction. According to the example shown in FIG. 5, the horizontal reduction ratio THIN _h is 162/1500 = 0.108, that is, THIN _h = 10.8%. Similarly, the reduction ratio THIN _rbv of the RB plane in the vertical direction is _108/1000 = 0.108, that is, THIN _rbv = 10.8%. Further, the reduction rate THIN _gv of the G plane is 108/2000 = 0.054, that is, THIN _gv = 5.4% (shifted to the right by 1 bit).
[0025]
In the present embodiment, there is no problem even when a remainder is generated as a result of division, and processing can be performed by rounding the quotient by the number of digits existing as parameter accuracy.
[0026]
In the arbitrary size matrix generation unit 106 in which the reduction ratio is set as described above, the timing (MAT_H) of the right end column of the matrix on each plane is generated by an algorithm applying the Bresenham principle described below. That is, the arbitrary size matrix generator 106 implements the following logic circuit.
[0027]
TMP = THIN _h − 100
IF (TMP> 0) THEN
MAT_H = 1
TMP = TMP − 100
ELSE
MAT_H = 0
TMP = TMP + THIN _h … (1)
Here, THIN _h = 10.8, and MAT_H is a signal representing the right end column of the matrix. That is, if MAT_H is “1”, it indicates the right end of the matrix. TMP indicates a variable realized by appropriately providing a flip-flop in the arbitrary size matrix generation unit 106.
[0028]
In the arbitrary size integration matrix generator 106, that is, when THIN _h is added for each pixel with respect to the difference between the horizontal reduction rate THIN _h and 100%, and when the accumulation exceeds 100%, The rightmost column of the matrix is detected.
[0029]
The arbitrary size integration matrix generator 106 generates a signal R_MAT_CLR indicating the timing of the lower right end of the matrix by configuring the same logic circuit in the vertical direction as in the horizontal direction. In the arbitrary size matrix generation unit 106, logic circuits in the horizontal and vertical directions are configured for each of the RGB planes.
[0030]
The size of the matrix output from the arbitrary size matrix generator 106 is N (natural number) or N + 1 only when the reduction ratio is not 0 in both horizontal and vertical directions, that is, always two values, even and odd. It becomes a combination. In the example shown in FIG. 5, it can be seen that a matrix with a horizontal size of 9 pixels and a matrix with 10 pixels are generated. Since these two types of values are self-evident when the reduction ratio is determined, the two kinds of values are given in advance as parameters to the apparatus together with the reduction ratio (that is, the input / output image size).
[0031]
As described above, according to the arbitrary size matrix generation unit 106, it is possible to effectively utilize all of the input image data regardless of the input / output image size.
[0032]
[Horizontal integration & averaging circuit 103]
Also in the horizontal integration & averaging circuit 103, a processing unit is provided for each RGB plane. Here, FIG. 6 shows a main configuration of the R plane processing unit in the horizontal integration & averaging circuit 103.
[0033]
As described above, the horizontal / vertical direction sizes of the matrix generated from the arbitrary size integration matrix generation unit 106 are always a combination of two values, an even number and an odd number. If the reciprocal of the size (number of pixels) when the size is even is the parameter EVEN_NUM_H, and the reciprocal of the size (number of pixels) when the size is the odd is the parameter ODD_NUM_H, the following logic is circuitized as shown in FIG. Thus, integration and averaging of the horizontal lines of the matrix can be automatically performed.
[0034]
IF (MAT_H = 1) THEN
IF (ODD_EVEN = 0)
R_AVE = R_SUM_H × EVEN_NUM_H
ELSE
R_AVE = R_SUM_H × ODD_NUM_H
ODD_EVEN = 0
ELSE
ODD_EVEN = NOT ODD_EVEN
R_SUM_H = R_SUM_H + R_DATA… (2)
Here, ODD_EVEN corresponds to a 1-bit flip-flop (not shown) provided in the circuit, and indicates a variable used to determine whether the number of pixels in the matrix is odd or even. R_DATA represents input data, R_SUM_H represents the total of R values in the horizontal direction, and R_AVE is obtained as a signal representing the average value of one row of the matrix on the R plane. However, the value of R_AVE is valid only when MAT_H = 1.
[0035]
In the horizontal integration & averaging circuit 103, that is, in the right end column of the matrix, the average value is obtained by multiplying the accumulated value in the horizontal direction by the inverse of the number of pixels in the matrix depending on whether the matrix size is even or odd. Is calculated. On the other hand, if the matrix is not the rightmost column, the horizontal R value is accumulated together with the setting process of the variable ODD_EVEN for even / odd determination.
[0036]
That is, according to FIG. 6, the input R_DATA is integrated by the integration circuit 601 and R_SUM_H is output. MAT_H indicating the right end column of the matrix is divided by ½ by the ½ divider circuit 603 based on the characteristics of the Bayer array, and input as an enable signal to the multiplexer 604. EVEN_NUM_H and ODD_NUM_H are input to the multiplexer 604, and an ODD_EVEN signal (not shown) is selected as a selection signal, one of which is output at the timing of MAT_H, and multiplied by R_SUM_H in the multiplier 602. R_AVE representing the average value of one row of the matrix on the R plane is a signal as a result of this multiplication.
[0037]
The horizontal integration & averaging circuit 103 has the same circuit configuration as that of FIG. 6 for the B and G planes.
[0038]
[Vertical integration & averaging circuit 104]
Also in the vertical integration & averaging circuit 104, a processing unit is provided for each of the RGB planes. FIG. 7 shows a main configuration of the R plane processing unit in the memory 107 and the vertical integration & averaging circuit 104.
[0039]
The vertical integration & averaging circuit 104 averages the entire matrix by further integrating and averaging the data averaged in the horizontal direction of each matrix in the vertical direction.
[0040]
The R_AVE signal input from the horizontal integration & averaging circuit 103 is written to the memory 107 at the first line (MAT_FIRST_LINE) of the matrix. In other cases, the adder 701 integrates up to the previous line within the same matrix R_INTG. And added (integrated). Also, the output of the adder 701 is averaged in the last row of the matrix.
[0041]
Here, as in the horizontal integration & averaging circuit 103, the fact that the size in the horizontal / vertical direction of the matrix generated from the arbitrary size integration matrix generation unit 106 is always a combination of two values, even and odd, is used. In other words, the inverse of the size (number of pixels) when the size in the vertical direction of the matrix is an even number is parameter EVEN_NUM_V, and the inverse of the size (number of pixels) when it is an odd number is parameter ODD_NUM_V. R_MAT_AVE representing the average value in the matrix on the R plane is obtained by determining, selecting, and performing multiplication. This R_MAT_AVE is written into the memory 107 via the decoder 703. The operation in the decoder 703 follows the following logic.
[0042]
IF (R_MAT_CLR = 1)
THEN
MEM = R_MAT_AVE
ELSE IF (MAT_FIRST_LINE = 1)
THEN
MEM = R_AVE
ELSE
MEM = R_INTG (3)
Here, the R_MAT_CLR signal is a signal representing the lower right end of the matrix obtained by AND gate output of horizontal and vertical timing pulses generated by the arbitrary size integration matrix generator 106. The MAT_FIRST_LINE signal is a signal indicating that it is the first line of each matrix.
[0043]
That is, in the decoder 703, R_MAT_AVE is written to the memory 107 if it is the lower right corner of the matrix, R_AVE is written to the memory 107 if it is the first line of the matrix, and R_INTG that is an accumulated value in the matrix is written to the memory 107 in other cases.
[0044]
According to FIG. 7, that is, on the basis of the effective synchronization signal of the R line, the rising edge detection circuit 704 detects the start of the block, and the signal obtained by dividing the signal by 1/2 by the 1/2 divider circuit 705 is sent to the multiplexer 706. Input as an enable signal. EVEN_NUM_V and ODD_NUM_V are input to the multiplexer 706, one of which is output at the start timing of the block by a selection signal (not shown), and is multiplied by the accumulated value of R_AVE in the multiplier 702. The multiplication result is output as an R_OUT signal representing the average value in the matrix on the R plane via the multiplexer 707.
[0045]
Based on the control of the RGB point sequential rearrangement unit 105 in the subsequent stage, the multiplexer 707 calculates either R_MAT_AVE, which is a multiplication result in the multiplier 702, or an average value of R (R_MAT_AVE) already stored in the memory 107. The R_OUT signal is output based on the R line effective synchronization signal.
[0046]
As described above, the result of averaging in the vertical direction of the matrix in the vertical integration & averaging circuit 104 is output as R_OUT, G_OUT, and B_OUT for each color component.
[0047]
As described above, in the horizontal integration & averaging circuit 103 and the vertical integration & averaging circuit 104, the reciprocal corresponding to two matrix sizes is used as a parameter, and one of them is automatically selected and reduced by performing multiplication. Output an image. That is, since reduction according to the reduction ratio is possible, it can be seen that the reduction ratio is versatile in the reduced image generation circuit of the present embodiment.
[0048]
[RGB Sorting Unit 105]
FIG. 8 is a block diagram illustrating main configurations of the memory 107 and the RGB point order rearrangement unit 105.
[0049]
The RGB point order rearrangement unit 105 extracts RGB output data R_OUT, G_OUT, and B_OUT from the vertical integration & averaging circuit 104, temporarily stores them in a storage element such as 802, and then outputs them in RGB point order. . In FIG. 8, the data synchronization signal is input from the RGB separation circuit 102, and the matrix synchronization signal such as R_MAT_CLR representing the lower right end of the matrix is input from the vertical integration & averaging circuit 104.
[0050]
According to the Bayer array as shown in FIG. 2, each color component of RGB is arranged by an odd / even line pair. Therefore, a line from which data is output from the RGB dot order rearrangement unit 105 is always an even number of the original image. It is clear that it will be a line. However, in the original image, either the R or B component is input as an even line and the other as an odd line. That is, the controller 801 determines the positional relationship of the lower right pixel of the matrix in each RGB plane based on the type of Bayer array of the original image that is currently input, and outputs it in dot order.
[0051]
Hereinafter, the operation in the dot sequential rearrangement unit 105 will be specifically described.
[0052]
FIG. 9 is a timing chart showing RGB point sequential output when the input image has the Bayer arrangement shown in FIG.
[0053]
According to the figure, the controller 801 receives R_OUT from the vertical integration & averaging circuit 104 at the Xth (X is a natural number) line which is the last line of the matrix for the R plane, for example, but does not perform this output. As described above, in the vertical integration & averaging circuit 104, R_OUT is written in the memory 107 in synchronization with the R_MAT_CLR signal.
[0054]
Then, in the next line (X + 1th line) of the last line in the R matrix, the line is always the last line of the G and B matrices, so the controller 801 outputs the control signal R_Memory to the memory 107. Thus, the R data held in the memory 107 is read out through the multiplexer 707 in synchronization with the timing signal B_MAT_CLR indicating the lower right end of the matrix of the G and B planes, and is output in the order of R_OUT, G_OUT, and B_OUT.
[0055]
As described above, the data (R_OUT, G_OUT, B_OUT) integrated and averaged in the matrix by the vertical integration & averaging circuit 104 for each of the R, G, and B planes is output dot-sequentially in RGB order for each pixel. This output is reduced image data output in the reduced image generation circuit of this embodiment.
[0056]
Needless to say, even if the input image has the Bayer arrangement shown in FIG. 2B, the timing chart is as shown in FIG. Needless to say, when the input image has the Bayer arrangement shown in any of (C) and (D) of FIG. 2, a timing chart in which R and B are interchanged in FIG. 9 can be obtained.
[0057]
Therefore, in the reduced image generation circuit of this embodiment, the capacity of the memory 107 used in the vertical integration & averaging circuit 104 and the RGB dot sequential rearrangement unit 105 is one line of the reduced image for each RGB, that is, a total of three lines. You only need to prepare the minutes.
[0058]
[Processing flowchart]
Here, processing in the reduced image generation circuit of the present embodiment described above will be briefly summarized and described with reference to the flowchart of FIG.
[0059]
First, in step S101, the RGB separation circuit 102 separates the RGB planes according to the type of the Bayer array.
[0060]
In step S102, the arbitrary size integration matrix generating unit 106 generates a matrix having an optimum vertical and horizontal arbitrary size according to the reduction ratio.
[0061]
In step S103, the horizontal integration & averaging circuit 103 integrates the matrix in the horizontal direction and automatically selects and averages the averaging parameters.
[0062]
In step S104, the vertical integration & averaging circuit 104 further integrates the matrix in the vertical direction and automatically selects and averages the averaging parameter.
[0063]
Finally, in step S105, the RGB point sequential rearrangement unit 105 rearranges and outputs the matrix integration results of each RGB plane from an arbitrary Bayer array in the order of RGB points.
[0064]
As described above, according to the reduced image generation circuit of the present embodiment, the RGB separation circuit 102 separates the RGB planes according to the type of the Bayer array with respect to the original image forming the Bayer array, and the arbitrary size integration matrix generation unit 106 To generate an optimal matrix of arbitrary vertical and horizontal sizes according to the reduction ratio, and the horizontal integration & averaging circuit 103 integrates and averages the matrix in the horizontal direction, and the vertical integration & averaging circuit 104 further vertically converts the matrix in the vertical direction. Integration and averaging are performed, and the RGB point sequential rearrangement unit 105 rearranges and outputs the integration results of the matrix of each RGB plane from an arbitrary Bayer array in the order of RGB points. At this time, as the capacity of the memory 107 that holds the output in the vertical integration & averaging circuit 104, only one line of the reduced image needs to be prepared for each RGB.
[0065]
In the reduced image generation circuit of the present embodiment, all of the input image data can be effectively used regardless of the input / output image size, and the versatility of the reduction rate is high.
[0066]
That is, according to the reduced image generation circuit of the present embodiment, the size of the memory used is small, the range of reduction rates that can be processed is versatile, and the input image data is sufficiently utilized to generate a reduced image. Is possible.
[0067]
Note that the present invention can be applied to a system including a plurality of devices (for example, a host computer, an interface device, a reader, and a printer), and a device (for example, a copying machine and a facsimile device) including a single device. You may apply to.
[0068]
【The invention's effect】
As described above, according to the present invention, it is possible to generate a high-quality reduced image with a small memory capacity from an original image having a Bayer array.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a configuration of a reduced image generation circuit according to an embodiment of the present invention.
FIG. 2 is a diagram illustrating types of Bayer arrangement of original images.
FIG. 3 is a block diagram showing a configuration of a conventional reduced image generation circuit.
FIG. 4 is a diagram for explaining a reduced image generation method by a conventional region integration method.
FIG. 5 is a diagram for explaining a matrix in the present embodiment.
FIG. 6 is a diagram showing a configuration of a horizontal integration & averaging circuit in the present embodiment.
FIG. 7 is a diagram showing a configuration of a vertical integration & averaging circuit in the present embodiment.
FIG. 8 is a diagram illustrating a configuration of an RGB dot sequential rearrangement unit in the present embodiment.
FIG. 9 is a timing chart showing RGB point sequential output in the present embodiment.
FIG. 10 is a flowchart showing processing in the reduced image generation circuit of the present embodiment.
[Explanation of symbols]
101 Reduced Image Generation Circuit 102 RGB Separation Circuit 103 Horizontal Integration & Average Circuit 104 Vertical Integration & Average Circuit 105 RGB Point Sequential Rearrangement Circuit 106 Arbitrary Size Integration Matrix Generation Unit

Claims (10)

An image processing apparatus for inputting image data in which each component forms a Bayer array and outputting the reduced image data,
Separating means for separating image data in which each component forms a Bayer array into planes for each component;
Matrix determining means for determining the horizontal and vertical sizes of the matrix for each plane based on the horizontal and vertical reduction ratios of the image data;
Horizontal averaging means for integrating and averaging the image data in the horizontal direction based on the horizontal size of the matrix determined by the matrix determination means for each plane;
For each plane, vertical averaging means for integrating and averaging the image data averaged in the horizontal direction in the horizontal averaging means in the vertical direction based on the vertical size of the matrix;
Output means for outputting the image data of each plane averaged in the vertical direction in the vertical averaging means in a dot-sequential manner according to the Bayer arrangement;
An image processing apparatus comprising: And a holding means for holding one line of image data of each plane averaged in the vertical direction in the vertical averaging means,
The image processing apparatus according to claim 1, wherein the output unit outputs the image data of each plane in a dot-sequential manner by reading out the image data held in the holding unit according to the Bayer arrangement.   3. The image processing apparatus according to claim 2, wherein the matrix determining means determines two consecutive natural numbers as the horizontal and vertical sizes of the matrix for each plane. The matrix determination means generates a horizontal timing signal of the matrix;
The horizontal averaging means integrates image data in a horizontal direction based on a horizontal timing signal of the matrix, and averages the image data in a horizontal direction based on a horizontal size of the matrix. The image processing apparatus according to claim 3.   The horizontal averaging means averages image data in the horizontal direction by multiplying the integration result by one of the reciprocal numbers of the two consecutive natural numbers determined as the horizontal size of the matrix by the matrix determining means. The image processing apparatus according to claim 4, wherein: The matrix determining means generates a timing signal in a vertical direction of the matrix;
The vertical averaging means integrates image data in a vertical direction based on a vertical timing signal of the matrix, and averages the image data in a vertical direction based on a vertical size of the matrix. The image processing apparatus according to claim 3.   The vertical averaging means averages the image data in the vertical direction by multiplying the integration result by either reciprocal of the two consecutive natural numbers determined as the vertical size of the matrix by the matrix determination means. The image processing apparatus according to claim 6, wherein: Input means for inputting image data in which each component forms a Bayer array;
Reduction means for reducing the image data independently for each component;
Output means for outputting the image data of each component dot-sequentially each time one pixel is aligned by the image data of each component output from the reduction means;
An image processing apparatus comprising: An image processing method in an image processing apparatus for inputting image data in which each component forms a Bayer array and outputting the reduced image data,
Separating means includes a separation step of each component to separate the image data constituting the Bayer array plane for each said component,
A matrix determination step in which the determining means determines the horizontal and vertical sizes of the matrix for each plane based on the horizontal and vertical reduction ratios of the image data;
For each plane, based on the horizontal size of the matrix determined in the matrix determining step, horizontal averaging means integrates and averages the image data in the horizontal direction, and a horizontal averaging step;
For each plane, a vertical averaging step in which the vertical averaging means integrates and averages the image data averaged in the horizontal direction in the horizontal averaging step in the vertical direction based on the vertical size of the matrix. When,
An output step in which the output means outputs the image data of each plane averaged in the vertical direction in the vertical averaging step in a dot-sequential manner according to the Bayer arrangement;
An image processing method comprising: An image processing method of an image processing apparatus,
The input means, the steps of each component for inputting image data constituting the Bayer array,
Reduction means comprises the steps of reducing independently the image data for each component,
An output means for outputting the image data of each component dot-sequentially every time one pixel is aligned with the reduced image data of each component ;
An image processing method comprising:

Images