JP4126583B2 - Manufacturing method of semiconductor device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a method of manufacturing a semiconductor device in which a field effect transistor and a bipolar transistor are formed on a common semiconductor substrate.
[0002]
[Prior art]
FIG. 3 shows an NPN type silicon germanium (Si _1-x Ge _x , hereinafter referred to as SiGe) heterojunction bipolar transistor and a CMOS transistor formed on a common semiconductor substrate and manufactured according to a conventional example of the present invention. 2 shows a BiCMOS semiconductor device. In this conventional example, an oxide film (not shown) is formed by thermal oxidation on the surface of a semiconductor substrate 11 which is a P-type and (100) Si substrate or the like, and a transistor for a SiGe heterojunction bipolar transistor is formed. An opening that defines a buried collector formation region in the formation region 12 is formed in the oxide film.
[0003]
Next, Sb ₂ O ₃ to Sb is vapor-phase diffused at 1200 ° C. into the semiconductor substrate 11 exposed through the opening of the oxide film, thereby forming an N ⁺ type buried collector 13. Thereafter, the oxide film is removed. Then, an N-type semiconductor layer 14 such as a Si layer having a resistivity of 1 to 5 Ωcm and a thickness of 0.3 to 2.0 μm is epitaxially grown on the semiconductor substrate 11. A semiconductor substrate 15 is formed.
[0004]
Next, the surface of the semiconductor layer 14 is thermally oxidized to form an oxide film (not shown) such as a SiO ₂ film having a thickness of 50 nm as a pad film, and a 100 nm thick film is formed on the oxide film by a CVD method. An oxidation resistant film such as a silicon nitride (Si ₃ N ₄ ) film is formed. Then, a resist having a pattern covering the element formation region is formed on the oxidation resistant film, and the oxidation resistant film is removed using the resist as a mask. Thereafter, an element isolation insulating film 16 such as a SiO ₂ film having a thickness of 200 to 800 nm is formed by steam oxidation at a temperature of 1000 to 1050 ° C.
[0005]
Next, after removing the above-described oxidation resistant film, an oxide film (not shown) such as a SiO ₂ film having a thickness of 40 nm is formed on the entire surface. Then, using a resist (not shown) as a mask, several ion implantations of boron (B) having an acceleration energy in the range of 20 to 850 keV and a dose in the range of 1 × 10 ¹² to 1 × 10 ¹⁴ cm ⁻² are performed. As a result, the P ⁺ -type element isolation region 17 is formed between the portions to be electrically isolated from each other, and at the same time, the P-type well 21 is formed in the NMOS transistor formation region 18.
[0006]
Subsequently, using a resist (not shown) of another pattern as a mask, phosphorus (P) having an acceleration energy in the range of 50 to 600 keV and a dose in the range of 1 × 10 ^{12 to} 5 × 10 ¹³ cm ^−2. By performing this ion implantation several times, an N-type well 23 is formed in the transistor formation region 22 for the PMOS transistor. Further, using a resist (not shown) of another pattern as a mask, ion implantation of P having an acceleration energy in the range of 70 to 400 keV and a dose in the range of 2 × 10 ^{13 to} 7 × 10 ¹⁵ cm ^−2. The collector extraction region 24 is formed in the transistor formation region 12 by performing several times.
[0007]
Next, after removing the oxide film on the surface of the semiconductor substrate 15 in the element formation region by wet etching, the exposed surface of the semiconductor substrate 15 is exposed to SiO 4 having a thickness of 4 to 10 nm by thermal oxidation at 800 to 900 ° C. _A gate insulating film 25 such as _two films is formed. Subsequently, a semiconductor film such as an N-type polycrystalline Si film having a thickness of 100 nm and a tungsten silicide (WSi) film having a thickness of 100 nm are sequentially deposited on the entire surface. Then, these films are patterned by lithography and dry etching to form gate electrodes 26 in the transistor formation regions 18 and 22.
[0008]
Thereafter, using a resist (not shown) or the like as a mask, arsenic (As) is ion-implanted into the semiconductor substrate 15 with an acceleration energy of 60 keV and a dose of 1 × 10 ¹³ to 1 × 10 ¹⁴ cm ⁻² . An N-type impurity region 27 to be a part of the source / drain in the transistor formation region 18 is formed. Also, BF ₂ is ion-implanted into the semiconductor substrate 15 with an acceleration energy of 25 keV and a dose of 1 × 10 ¹³ to 1 × 10 ¹⁴ cm ⁻² using another pattern of resist (not shown) as a mask. As a result, a P-type impurity region 28 which becomes a part of the source / drain in the transistor formation region 22 is formed.
[0009]
Next, an insulating film 31 such as a 100 nm thick SiO ₂ film and a metal diffusion prevention film 32 such as a 30 nm thick Si ₃ N ₄ film are sequentially deposited on the entire surface. Then, the impurities in the impurity regions 27 and 28 are activated by heat treatment at a temperature of about 800 to 900 ° C. Thereafter, as shown in FIG. 4A, a resist 33 is applied on the diffusion prevention film 32, and an opening 34 corresponding to the base formation region of the transistor formation region 12 is formed in the resist 33. Then, as shown in FIG. 4B, an opening 35 is formed in the diffusion preventing film 32 by dry etching using the resist 33 as a mask.
[0010]
Next, as shown in FIG. 5A, the resist 33 is removed, and the insulating film 31 and the gate insulating film 25 are wet-etched. Then, as shown in FIG. 5B, a semiconductor layer 36 which is a SiGe mixed crystal layer is formed on the entire surface of the semiconductor substrate 15 and the diffusion prevention film 32 exposed through the opening 35 by the CVD method. Deposit. Prior to the start of the CVD, the semiconductor substrate 15 is exposed through the opening 35 of the gate insulating film 25, the insulating film 31, and the diffusion prevention film 32, so that the semiconductor substrate 15 exposed in the semiconductor layer 36 is exposed. The upper part becomes an epitaxial layer, and the part on the diffusion prevention film 32 becomes a polycrystalline layer.
[0011]
Note that the wet etching is performed in the step of FIG. 5A without performing the dry etching using the resist 33 as a mask in the insulating film 31 such as the SiO ₂ film and the semiconductor layer 14 such as the Si layer. This is because the selectivity cannot be increased, and the surface of the semiconductor substrate 15 is damaged by dry etching, and an epitaxial layer having a good crystal quality cannot be formed on the semiconductor substrate 15 as a base layer.
[0012]
FIG. 6 shows another process for forming the opening 35 in the diffusion preventing film 32, the insulating film 31, and the gate insulating film 25. In this step, after the opening 35 is formed in the diffusion prevention film 32 by dry etching using the resist 33 as a mask as shown in FIG. 4B, as shown in FIG. Dry etching is performed using the resist 33 as a mask until the insulating film 31 and the gate insulating film 25 remain slightly. Then, as shown in FIG. 6B, after the resist 33 is removed, the remaining insulating film 31 and gate insulating film 25 are wet-etched. The openings 35 and the like in FIG. 3 are formed in the process of FIG.
[0013]
As the semiconductor layer 36, in addition to the SiGe mixed crystal layer as described above, a silicon germanium carbon (Si _1-xy Ge _{x Cy} ) mixed crystal layer containing an impurity necessary for the base, a Si layer, or the like may be formed. is there. After the semiconductor layer 36 is formed as described above, the semiconductor layer 36 is processed into a pattern of the base layer and the base take-out electrode by dry etching using a resist (not shown) as a mask. Thereafter, an insulating film 37 such as a SiO ₂ film is deposited, and the insulating film 37 is densified by heat treatment. Then, an opening 38 corresponding to the emitter formation region is formed in the insulating film 37 by dry etching using a resist (not shown) as a mask.
[0014]
Next, a semiconductor film 41 such as a polycrystalline Si film having a thickness of 100 to 150 nm is deposited on the entire surface, and As is applied at an acceleration energy of 40 to 60 keV and a dose of 1 × 10 ¹⁶ to 2 × 10 ¹⁶ cm ^−2. Ions are implanted into the semiconductor film 41. Then, the semiconductor film 41 is processed into a conductive film pattern to which the emitter metal electrode is connected by dry etching using a resist (not shown) as a mask. Thereafter, using the resist remaining on the semiconductor film 41 as a mask and using the semiconductor layer 36 as a stopper and mask, the insulating film 37, the diffusion preventing film 32, and the insulating film 31 are dry-etched. As a result, sidewall spacers 42 made of the insulating film 31 and the like are formed on the side surfaces of the gate electrode 26.
[0015]
Next, As is ion-implanted into the semiconductor substrate 15 with an acceleration energy of 25 to 40 keV and a dose of 1 × 10 ¹⁵ to 1 × 10 ¹⁶ cm ^{−2 using} a resist (not shown) as a mask. An N ⁺ -type impurity region 43 that becomes a part of the source / drain in the transistor formation region 18 is formed, and the impurity concentration in the surface portion of the collector extraction region 24 in the transistor formation region 12 is increased.
[0016]
Further, using a resist (not shown) having another pattern as a mask, BF _{2 is applied} to the semiconductor substrate 15 and the semiconductor layer at an acceleration energy of 25 to 40 keV and a dose of 1 × 10 ¹⁵ to 1 × 10 ¹⁶ cm ^−2. By ion-implanting into the exposed portion 36, a P ⁺ -type impurity region 44 that becomes a part of the source / drain in the transistor formation region 22 is formed and the impurity concentration of the base extraction electrode in the transistor formation region 12 is increased.
[0017]
Next, by heat treatment, As in the semiconductor film 41 is activated and diffused into the semiconductor layer 36 to form the emitter 45 in the transistor formation region 12. At the same time, the impurity regions 43 and 44, the collector extraction region 24 and the base are formed. Impurities in the extraction electrode are activated. Then, an interlayer insulating film 46 such as a BPSG film is formed, and the interlayer insulating film 46 is planarized by heat treatment.
[0018]
Thereafter, a contact hole 47 is opened in the interlayer insulating film 46, and impurities are ion-implanted into the contact hole 47 in order to compensate for the positional deviation of the contact hole 47. Then, a metal electrode 48, a multilayer wiring (not shown), an overcoat film (not shown), etc. are formed to complete this BiCMOS semiconductor device.
[0019]
[Problems to be solved by the invention]
However, in the above-described conventional example, when the opening 35 is formed in the base formation region by the process shown in FIGS. 4 and 5, the amount of wet etching is large. For this reason, there are many side etchings of the insulating film 31, and the base formation region of the transistor formation region 12 becomes larger than a desired dimension.
[0020]
Further, since the etching selectivity of the insulating film 31 with respect to the diffusion preventing film 32 during wet etching with respect to the insulating film 31 is large, the diffusion preventing film 32 is formed on the inner surface of the opening 35 as shown in FIG. A cocoon is formed. When the semiconductor layer 36 is formed in this state as shown in FIG. 5B, an excessive stress is generated in the semiconductor layer 36 due to the discontinuous base shape, and an epitaxial layer having a good crystal quality is used as a base. It cannot be formed as a layer. Therefore, it is difficult to manufacture a highly reliable semiconductor device in the above-described conventional example using the steps shown in FIGS.
[0021]
On the other hand, in the above-described conventional example, when the opening 35 is formed in the base formation region by the steps shown in FIGS. 4 and 6, since the amount of wet etching is small, side etching of the insulating film 31 is suppressed, A base formation region close to a desired dimension can be obtained in the transistor formation region 12. In addition, the amount of protrusion of the diffusion preventing film 32 is small, and the formation of the semiconductor layer 36 makes it possible to form an epitaxial layer having better crystal quality than the steps shown in FIGS. However, it is actually difficult to perform dry etching until the insulating film 31 and the gate insulating film 25 remain slightly, particularly in the mass production process, and the wrinkles of the diffusion preventing film 32 cannot be completely eliminated.
[0022]
Eventually, in the above-described conventional example, it is difficult to manufacture a semiconductor device in which a field effect transistor and a bipolar transistor are formed on a common semiconductor substrate and have high reliability. Accordingly, an object of the present invention is to provide a semiconductor device manufacturing method capable of manufacturing a highly reliable semiconductor device despite the fact that a field effect transistor and a bipolar transistor are formed on a common semiconductor substrate. It is.
[0023]
[Means for Solving the Problems]
In the method of manufacturing a semiconductor device according to the present invention, the gate electrode containing metal of the field effect transistor is covered with a diffusion preventing film that prevents diffusion of the metal. For this reason, abnormal growth due to metal contamination is prevented during the formation of the epitaxial layer as the base layer. Further, when the surface protection film is etched to expose the semiconductor substrate in the base formation region of the bipolar transistor, dry etching is performed to the middle of the thickness, and the remaining thickness is wet etched. For this reason, it is possible to obtain a base formation region of a bipolar transistor having a small wet etching amount, suppressing side etching of the surface protective film, and having a desired dimension. Further, even if the etching selectivity of the surface protective film to the semiconductor substrate is not large, the surface of the semiconductor substrate in the base formation region of the bipolar transistor is not damaged.
[0024]
In addition, prior to etching the surface protective film, the diffusion prevention film on the surface protective film is etched using a first mask having an opening extending to the outside of the base formation region. For this reason, even if a wrinkle of the diffusion prevention film is formed by side etching when the surface protection film is wet-etched using the second mask having the opening corresponding to the base formation region, the edge of the opening of the first mask And the edge of the opening of the second mask are separated from the base formation region of the bipolar transistor by the distance from the base of the bipolar transistor. As a result, the wrinkles of the diffusion preventing film are formed on the surface protective film instead of the semiconductor substrate, and the base layer formed in the vicinity of the wrinkles of the diffusion preventing film is not an epitaxial layer but a polycrystalline layer. Since this polycrystalline layer portion is not used as an intrinsic base, the influence of the stress of the base layer on the bipolar transistor can be ignored.
[0025]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, an embodiment of the present invention applied to a method of manufacturing a BiCMOS semiconductor device in which an NPN-type SiGe heterojunction bipolar transistor and a CMOS transistor are formed on a common semiconductor substrate will be described with reference to FIGS. To do. As shown in FIG. 1A, also in this embodiment, the same steps as in the above-described conventional example are executed until the resist 33 is applied on the diffusion preventing film 32. However, in this embodiment, thereafter, an opening 51 that extends to the outside of the base formation region of the transistor formation region 12 is formed in the resist 33. Then, the diffusion prevention film 32 is subjected to dry etching using the resist 33 as a mask.
[0026]
Next, as shown in FIG. 1B, the resist 33 is removed, and another resist 52 is applied on the diffusion prevention film 32 and the insulating film 31. Next, an opening 53 corresponding to the base formation region of the transistor formation region 12 is formed in the resist 52. Thereafter, dry etching is performed halfway through the thickness of the insulating film 31 using the resist 52 as a mask. In this case, it is ideal if dry etching can be performed until the insulating film 31 and the gate insulating film 25 remain slightly, but the insulating film 31 and the gate insulating film 25 may be left with a certain thickness.
[0027]
Next, as shown in FIG. 2A, the resist 52 is removed, and the remaining thicknesses of the insulating film 31 and the gate insulating film 25 are wet-etched to form openings 54. Then, as shown in FIG. 2B, a semiconductor layer which is a SiGe mixed crystal layer is formed on the entire surface of the semiconductor substrate 15, the insulating film 31, and the diffusion prevention film 32 exposed through the opening 54. 36 is deposited by CVD. After the semiconductor layer 36 is deposited, the same steps as in the above-described conventional example are performed again to complete the BiCMOS semiconductor device.
[0028]
In the above embodiment, as shown in FIGS. 1 and 2, the diffusion prevention film 32 is patterned so as to cover the transistor formation region 12 except for the opening 54 and its vicinity. However, since the diffusion prevention film 32 is provided to prevent metal diffusion from the WSi film or the like in the gate electrode 26 before the formation of the semiconductor layer 36, the diffusion prevention film 32 needs to cover the transistor formation region 12. Instead, the diffusion prevention film 32 may be patterned so as to cover at least the transistor formation regions 18 and 22.
[0029]
In the above-described embodiment, the gate electrode 26 is formed in the transistor formation regions 18 and 22 by the polycrystalline Si film and the WSi film. However, a metal-containing film other than the WSi film may be used instead of the WSi film. The same effects as those of the above-described embodiment can be obtained. In the above-described embodiment, the Si ₃ N ₄ film is used as the metal diffusion preventing film 32, but a film other than the Si ₃ N ₄ film can be used as long as it can prevent metal diffusion. May be.
[0030]
In the above-described embodiment, the bipolar transistor in the transistor formation region 12 is an NPN type, but this bipolar transistor may be a PNP type. In the above embodiment, the invention of the present application is applied to a manufacturing method of a BiCMOS semiconductor device in which an NPN-type SiGe heterojunction bipolar transistor and a CMOS transistor are formed on a common semiconductor substrate. The invention of the present application can also be applied to a method for manufacturing a semiconductor device that is only a transistor or a PMOS transistor.
[0031]
【The invention's effect】
In the method for manufacturing a semiconductor device according to the present invention, a base formation region of a bipolar transistor close to a desired dimension can be obtained. In addition, the surface of the semiconductor substrate in the base formation region of the bipolar transistor is not damaged, and abnormal growth due to metal contamination is prevented during the formation of the epitaxial layer as the base layer. A layer can be formed in the base formation region. Furthermore, the influence of the base layer stress on the bipolar transistor can be ignored. Therefore, it is possible to manufacture a highly reliable semiconductor device even though the field effect transistor and the bipolar transistor are formed on a common semiconductor substrate.
[Brief description of the drawings]
FIG. 1 is a side sectional view of a semiconductor device sequentially showing steps in the middle of an embodiment of the present invention.
FIG. 2 is a side sectional view of the semiconductor device sequentially illustrating processes following FIG. 1;
3 is a side sectional view of a semiconductor device manufactured according to one conventional example of the present invention using the process of FIG. 6;
FIG. 4 is a side sectional view of a semiconductor device sequentially showing steps in the middle of one conventional example of the present invention.
FIG. 5 is a side sectional view of the semiconductor device, sequentially illustrating processes following FIG. 4;
6 is a side cross-sectional view of the semiconductor device, which is a step different from FIG. 5 and sequentially shows steps subsequent to FIG. 4;
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 15 ... Semiconductor substrate, 25 ... Gate insulating film (surface protective film), 26 ... Gate electrode, 31 ... Insulating film (surface protective film), 32 ... Diffusion prevention film, 33 ... Resist (first mask), 36 ... Semiconductor Layer (base layer), 51 ... opening, 52 ... resist (second mask), 53 ... opening,

Claims (3)

In a method for manufacturing a semiconductor device in which a field effect transistor having a gate electrode containing a metal and a bipolar transistor having a base layer that is an epitaxial layer are formed on a common semiconductor substrate,
A step of sequentially laminating a surface protective film for protecting a surface of the semiconductor substrate in a formation region of the bipolar transistor and a diffusion prevention film for covering the gate electrode and preventing diffusion of the metal on an upper layer of the semiconductor substrate;
Etching the diffusion barrier film using a first mask having an opening extending to the outside of the base formation region of the bipolar transistor;
Dry etching halfway through the thickness of the surface protective film using a second mask having an opening corresponding to the base formation region of the bipolar transistor;
Wet etching the remaining thickness of the surface protective film;
Run
Forming a ridge of the diffusion prevention film away from the base formation region of the bipolar transistor by a distance between the edge of the opening of the first mask and the edge of the opening of the second mask. A method for manufacturing a semiconductor device. The method of manufacturing a semiconductor device according to claim 1, wherein the diffusion prevention film is a silicon nitride film. 2. The method of manufacturing a semiconductor device according to claim 1, wherein the epitaxial layer is any one of a silicon germanium mixed crystal layer, a silicon germanium carbon mixed crystal layer, and a silicon layer.

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