JP4121138B2 - 光再構成可能論理回路 - Google Patents

光再構成可能論理回路 Download PDF

Info

Publication number
JP4121138B2
JP4121138B2 JP2006519534A JP2006519534A JP4121138B2 JP 4121138 B2 JP4121138 B2 JP 4121138B2 JP 2006519534 A JP2006519534 A JP 2006519534A JP 2006519534 A JP2006519534 A JP 2006519534A JP 4121138 B2 JP4121138 B2 JP 4121138B2
Authority
JP
Japan
Prior art keywords
circuit
logic
configuration
input
configuration information
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP2006519534A
Other languages
English (en)
Japanese (ja)
Other versions
JPWO2005117262A1 (ja
Inventor
実 渡邊
史典 小林
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Japan Science and Technology Agency
National Institute of Japan Science and Technology Agency
Original Assignee
Japan Science and Technology Agency
National Institute of Japan Science and Technology Agency
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Japan Science and Technology Agency, National Institute of Japan Science and Technology Agency filed Critical Japan Science and Technology Agency
Publication of JPWO2005117262A1 publication Critical patent/JPWO2005117262A1/ja
Application granted granted Critical
Publication of JP4121138B2 publication Critical patent/JP4121138B2/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17748—Structural details of configuration resources
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F39/00—Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group H10F30/00, e.g. radiation detectors comprising photodiode arrays
    • H10F39/10—Integrated devices
    • H10F39/107—Integrated devices having multiple elements covered by H10F30/00 in a repetitive configuration, e.g. radiation detectors comprising photodiode arrays

Landscapes

  • Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Logic Circuits (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
JP2006519534A 2004-05-26 2005-05-11 光再構成可能論理回路 Expired - Fee Related JP4121138B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP2004156769 2004-05-26
JP2004156769 2004-05-26
PCT/JP2005/008612 WO2005117262A1 (ja) 2004-05-26 2005-05-11 光再構成可能論理回路

Publications (2)

Publication Number Publication Date
JPWO2005117262A1 JPWO2005117262A1 (ja) 2008-04-03
JP4121138B2 true JP4121138B2 (ja) 2008-07-23

Family

ID=35451211

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2006519534A Expired - Fee Related JP4121138B2 (ja) 2004-05-26 2005-05-11 光再構成可能論理回路

Country Status (4)

Country Link
US (1) US7876483B2 (enExample)
JP (1) JP4121138B2 (enExample)
TW (1) TW200603539A (enExample)
WO (1) WO2005117262A1 (enExample)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8581625B2 (en) 2011-05-19 2013-11-12 Semiconductor Energy Laboratory Co., Ltd. Programmable logic device

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8054670B2 (en) * 2006-08-28 2011-11-08 Kyushu Institute Of Technology Reconfiguration controlling apparatus for optically reconfigurable gate array and method thereof
JP4923251B2 (ja) * 2006-08-28 2012-04-25 国立大学法人九州工業大学 光再構成ゲートアレイの再構成制御装置及びその方法
JP4923257B2 (ja) * 2006-11-24 2012-04-25 国立大学法人九州工業大学 光再構成ゲートアレイの再構成制御装置及びその方法
KR102341264B1 (ko) * 2015-02-02 2021-12-20 삼성전자주식회사 래치를 이용한 레이저 검출기 및 이를 포함하는 반도체 장치
CN115425965B (zh) * 2022-11-03 2023-02-17 之江实验室 一种可重构逻辑门电路及电路的控制方法

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5959747A (en) * 1996-09-11 1999-09-28 California Institute Of Technology Compact architecture for holographic systems
US6057703A (en) * 1997-08-22 2000-05-02 Holoplex Inc. Reconfigurable programmable logic devices
US6055174A (en) * 1999-06-07 2000-04-25 Holoplex Inc. Solid state holographic memory
JP3456981B2 (ja) 2001-05-25 2003-10-14 科学技術振興事業団 光再構成型ゲートアレイおよびその再構成方法
JP3649711B2 (ja) 2002-07-31 2005-05-18 独立行政法人科学技術振興機構 光再構成型ゲートアレイへのデータ書き込み方法および装置

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8581625B2 (en) 2011-05-19 2013-11-12 Semiconductor Energy Laboratory Co., Ltd. Programmable logic device
US9595964B2 (en) 2011-05-19 2017-03-14 Semiconductor Energy Laboratory Co., Ltd. Programmable logic device
US9900007B2 (en) 2011-05-19 2018-02-20 Semiconductor Energy Laboratory Co., Ltd. Programmable logic device

Also Published As

Publication number Publication date
WO2005117262A1 (ja) 2005-12-08
US7876483B2 (en) 2011-01-25
JPWO2005117262A1 (ja) 2008-04-03
TW200603539A (en) 2006-01-16
US20090296178A1 (en) 2009-12-03
TWI346455B (enExample) 2011-08-01

Similar Documents

Publication Publication Date Title
US7265577B2 (en) Integrated circuits with RAM and ROM fabrication options
US9151798B2 (en) Method and apparatus for testing a semiconductor device
KR20250048823A (ko) 큐비트용 제어 시스템 및 전하 로킹 회로
US9923555B2 (en) Fine-grained power gating in FPGA interconnects
JPWO2005117262A1 (ja) 光再構成可能論理回路
US9000812B1 (en) Current steering with independent biasing between bleed and steering circuitry
US20080282214A1 (en) Reconfigurable integrated circuit
US5083181A (en) Semiconductor integrated circuit device and wiring method thereof
US4760249A (en) Logic array having multiple optical logic inputs
CN213583056U (zh) 显示驱动芯片和led灯板
JP5086345B2 (ja) 発光素子アレイ、発光装置および画像形成装置
Watanabe et al. An optically differential reconfigurable gate array using a 0.18/spl mu/m CMOS process
Watanabe et al. An optically differential reconfigurable gate array and its power consumption estimation
Watanabe et al. A high-density optically reconfigurable gate array using dynamic method
US20060152249A1 (en) Configuration circuit for programmable logic devices
ES2973490T3 (es) Sistema Informático óptico de múltiples bits
CN116346124A (zh) 用于可编程逻辑器件的低功率模式的系统和方法
JP2008166610A (ja) 発光素子アレイ、発光装置および画像形成装置
Watanabe et al. An optical reconfiguration circuit for optically reconfigurable Gate Arrays
JP3456981B2 (ja) 光再構成型ゲートアレイおよびその再構成方法
US20250008241A1 (en) Clock transmission circuit, imaging element, and method for manufacturing clock transmission circuit
Watanabe et al. A 16,000-gate-count optically reconfigurable gate array in a standard 0.35/spl mu/m CMOS technology
EP0395070A2 (en) Gate array semiconductor integrated circuit
Furukawa et al. Direct optical communication on an optically reconfigurable gate array
Watanabe An 11,424 gate-count zero-overhead dynamic optically reconfigurable gate array VLSI

Legal Events

Date Code Title Description
A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20080125

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20080125

A871 Explanation of circumstances concerning accelerated examination

Free format text: JAPANESE INTERMEDIATE CODE: A871

Effective date: 20080125

TRDD Decision of grant or rejection written
A975 Report on accelerated examination

Free format text: JAPANESE INTERMEDIATE CODE: A971005

Effective date: 20080415

A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20080423

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20080425

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20110509

Year of fee payment: 3

R150 Certificate of patent or registration of utility model

Ref document number: 4121138

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20120509

Year of fee payment: 4

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20130509

Year of fee payment: 5

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20140509

Year of fee payment: 6

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

S533 Written request for registration of change of name

Free format text: JAPANESE INTERMEDIATE CODE: R313533

R350 Written notification of registration of transfer

Free format text: JAPANESE INTERMEDIATE CODE: R350

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

LAPS Cancellation because of no payment of annual fees