JP4120572B2 - Circuit equipment - Google Patents

Description

  The present invention includes a power-on reset circuit unit that outputs a power-on reset signal to a logic circuit unit based on a power supply voltage state, and a constant current circuit unit that supplies a constant current generated based on the power source to an analog circuit unit. The present invention relates to a configured circuit device.

  In recent years, environmental problems have been greatly highlighted, and it is indispensable to promote energy saving in order to save resources in various technical fields. The situation is the same for the in-vehicle electronic circuit device. The electrical components in vehicles are increasing in scale of the system, and the number of control units is increasing. Therefore, as long as the standby current (dark current, for example, backup current) of each control unit when the ignition switch is OFF does not decrease, the standby current per vehicle keeps increasing and the battery consumption is reduced. Become intense.

For example, in a microcomputer that constitutes an ECU (Electronic Control Unit), a power supply circuit for backing up RAM data is required, but it is also necessary to reduce the standby current for the power supply circuit itself.
By the way, the backup power supply circuit generates and outputs a power-on reset signal in order to reliably reset the CPU of the microcomputer and the logic circuit as its peripheral circuit when the operation power supply is started. It is usually done to incorporate. The power-on reset circuit is often composed of a simple logic circuit, but a power-on reset circuit dedicated to the circuit may be required to operate the logic circuit with certainty. In addition, since a constant current circuit for supplying a constant current is also required to maintain the analog circuit in a predetermined operation state, it is difficult to reduce current consumption.

  FIG. 17 shows a configuration example of a power-on reset circuit and a constant current circuit. The collector of the NPN transistor 2 constituting the power-on reset circuit 1 is connected to the power supply line 4 via the resistor 3, and the emitter is connected to the ground line 5. A series circuit of resistors 6 and 7 is connected between the power supply line 4 and the ground line 5, and a common connection point between them is connected to the base of the transistor 2. The collector of the transistor 2 serves as an output terminal for the power-on reset signal POR. One or more diodes may be interposed between the resistor 6 and the base of the transistor 2 for potential adjustment.

The power-on reset circuit 1 configured as described above maintains the reset signal active (high) if the power supply voltage Vcc is equal to or lower than the threshold value Vth, and the power supply voltage Vcc exceeds the threshold value Vth. The reset signal is made inactive (low). In this case, the threshold value Vth is set as follows.
Vth = VBE1 / R2 ・ R1 + VBE1
= (R1 + R2) / R2 · VBE1 (1)
However, VBE1 is the base-emitter voltage of the transistor 1, and R1 and R2 are resistance values of the resistors 6 and 7, respectively.

  On the other hand, the emitter of the NPN transistor 9 constituting the constant current circuit 8 is connected to the ground line 5, the collector is connected to the power supply line 4 through the resistor 10, and the base of the NPN transistor 11 and the PNP transistor It is connected to 12 collectors (one of the multi-collectors). The emitter of the transistor 12 is connected to the power supply line 4, and the collector (the other of the multi-collectors) is connected to the collector of the transistor 11 and the base of the PNP transistor 13. The emitter of the transistor 11 is connected to the ground line 5 via the resistor 14. The emitter of the transistor 13 is connected to the base of the transistor 12 via the resistor 15, and the collector is connected to the ground line 5.

In the constant current circuit 8 configured as described above, the constant current I flowing through the emitter-collector of the transistor 12 is set as follows.
I = VBE2 / R3 (2)
However, VBE2 is the base-emitter voltage of the transistor 9, and R3 is the resistance value of the resistor 14. Such a configuration of the constant current circuit 8 is disclosed in Patent Document 1, for example. Further, although it has not been possible to find a document in which the configuration of the power-on reset circuit 1 is clearly disclosed, it goes without saying that it is a very general circuit.
JP 11-161348 A

  The power-on reset circuit 1 maintains the reset signal in an inactive state by continuing to flow a current (bias current) through the transistor 2 even after the power supply voltage Vcc reaches a steady level. It is like that. Further, the constant current circuit 8 also has a configuration in which a current continues to flow through the transistor 12 in order to continue supplying the constant current I. Thus, in order to maintain each operation state for each circuit, current is kept flowing.

  The present invention has been made in view of the above circumstances, and an object thereof is to further reduce a current that is constantly consumed, such as a standby current, in a configuration including a power-on reset circuit unit and a constant current circuit unit. It is an object of the present invention to provide a circuit device that can be used.

According to the circuit device of the first aspect, the circuit part for supplying the operating current in the power-on reset circuit part and the part of the constant current circuit part are configured in common. Specifically, the common and the device for operating the current setting for supplying the operating current, and a constant current setting device of the constant current circuit unit in power-on reset circuit. That is, since each of the two parts is a component that aims to flow a predetermined current, the amount of current that flows steadily can be reduced by configuring both of them together.

According to the circuit device of the second aspect , when the common setting element is constituted by the PNP transistor, each circuit element is formed by the trench isolation structure. That is, when the PNP transistor is configured by junction isolation, a parasitic PNP transistor is formed by the isolation region, and thus a current corresponding to the hFE of the transistor flows into the isolation region. On the other hand, if the trench isolation structure is adopted, a parasitic PNP transistor is not formed, and thus unnecessary current consumption can be suppressed.

According to the circuit device of the third aspect, since the output stage of the power-on reset signal is composed of the NPN transistor and the parasitic PNP transistor is formed, the electric charge accumulated in the base region of the NPN transistor passes through the parasitic PNP transistor. As a result, the emitter is discharged at a high speed, and the operation speed of the NPN transistor can be improved.

According to the circuit device of the fourth aspect, the resistance element for setting the reset release threshold value in the power-on reset circuit section and the resistance element for setting the constant current value in the constant current circuit section are CMOS. It comprises using an element. That is, a resistor having a high resistance value is required to reduce the current consumption, but if such a resistor element is formed as a diffused resistor, the element area becomes large. On the other hand, if the resistance element is formed using a CMOS element, the element area can be reduced.

According to the circuit device of the fifth aspect, the present invention is applied to an I / O circuit that outputs a signal to the CPU constituting the vehicle control ECU. That is, the vehicle control ECU may shift to a low power consumption mode such as a sleep mode, for example, depending on the processing state. It is necessary to continue supplying a constant current so that a part of the circuit maintains a predetermined operation state. In addition, it is necessary to initialize a logic circuit portion included in the I / O circuit by a power-on reset. The vehicle control ECU is highly demanded to reduce power consumption in order to suppress battery consumption. Therefore, the circuit device of the present invention can be applied very effectively.

(First embodiment)
A first embodiment of the present invention will be described below with reference to FIGS. FIG. 1 shows an electrical configuration of a circuit device in which a power-on reset circuit unit and a constant current circuit unit are integrally configured. The configuration of the power-on reset circuit unit 22 of the circuit device 21 will be described. The collector of the NPN transistor 23 constituting the power-on reset circuit 22 is connected to the power supply line 25 via the resistor 24, and the emitter is connected to the ground line 26.

  A series circuit of resistors 28 and 29 is connected between the power supply line 25 and the ground line 26 via an emitter-collector of a PNP transistor (operating current setting element, constant current setting element) 27. The common connection point between the two is connected to the base of the transistor 23. The base and collector of the transistor 27 are directly connected. The collector of the transistor 23 is an output terminal for a power-on reset signal.

  On the other hand, the constant current circuit unit 30 includes the transistor 27 and the resistors 28 and 29 constituting the power-on reset circuit unit 22 as common components. The base of the transistor 27 is connected to the base of the PNP transistor 31, the emitter of the transistor 31 is connected to the power supply line 25, and the collector is connected to the ground line 26 via the resistor 32. The collector of the transistor 31 is an output terminal for the constant current I. That is, the transistors 27 and 31 constitute a current mirror circuit.

According to the power-on reset circuit unit 22 configured as described above, the reset release threshold voltage Vth is expressed by equation (3).
Vth = VBE3 / R5.R4 + VBE3 + VBE4 (3)
However, VBE3 and VBE4 are the base-emitter voltages of the transistors 23 and 22, and R4 and R5 are the resistance values of the resistors 28 and 29, respectively. Here, if VBE3 = VBE4 = VBE,
Vth = (R4 + 2 · R5) / R5 · VBE (4)
It becomes.

On the other hand, the constant current I flowing by the constant current circuit unit 30 is
I = (Vcc-VBE4-VBE3) / R4
= (Vcc-2 · VBE) / R4 (5)
It becomes. Accordingly, the circuit operation is the same as that of the conventional power-on reset circuit 1 and constant current circuit 8.
When the power supply voltage Vcc exceeds the threshold voltage Vth and the reset signal becomes inactive, the operating current continues to flow through the transistor 27, the resistors 28 and 29, and the transistor 23 in the power-on reset circuit unit 22. The operating current is also a current that needs to flow in order for the constant current circuit unit 30 to continue supplying the constant current I.

  Next, FIG. 2 schematically shows the semiconductor structure of the PNP transistor 27. In this embodiment, the PNP transistor 27 is formed with a trench isolation structure. That is, a trench 42 reaching the buried oxide film 41 is formed on an SOI (Silicon On Insulator) substrate, and an oxide film is formed in the trench, and then polysilicon 43 is buried, thereby providing an element formation region of the transistor 27. Then, a P + collector region 45, an emitter region 46, and an N + base region 47 are formed in the low-concentration silicon semiconductor layer 44 (N−).

FIG. 3 shows an example in which a PNP transistor is formed by junction (PN junction) separation for comparison. In this case, a parasitic PNP transistor 49 is formed by adding an isolation P + region 48 to the collector region 45 and the base region 47. Then, since the current depending on hFE of the transistor 49 flows into the P + region 48, the effect of reducing current consumption cannot be sufficiently obtained.
On the other hand, according to the trench isolation structure shown in FIG. 2, the P + region 48 does not exist and the parasitic PNP transistor is not formed. Therefore, current consumption is further suppressed.

FIG. 4 schematically shows the semiconductor structure of the NPN transistor 23 arranged at the output stage of the power-on reset signal. Of course, the NPN transistor 23 is also formed with a trench isolation structure. In the element formation region provided as in FIG. 2, a P + base region 50 and an N + collector region 51 are formed, and an N + emitter region 52 is formed inside the base region 50. Further, by forming the P + region 53 separately from these, the parasitic PNP transistor 54 is intentionally formed by the base region 50, the collector region 51, and the P + region 53.
By forming the parasitic PNP transistor 54, the charge accumulated in the base region of the NPN transistor 23 can be extracted at high speed to the emitter side of the transistor 23 through the emitter-collector of the transistor 54. That is, the transistor 23 can be shut off at high speed.

  As described above, according to the present embodiment, the circuit device 21 is configured by sharing the circuit portion that supplies the operating current in the power-on reset circuit unit 22 and a part of the constant current circuit unit 30. Specifically, the operating current setting element of the power-on reset circuit unit 22 and the constant current setting element of the constant current circuit unit 30 are shared by the transistor 27, so that the amount of current that constantly flows in the circuit device 21 Can be reduced.

  Since the PNP transistor 27 is formed with a trench isolation structure, it is possible to avoid the formation of the parasitic PNP transistor 49 and suppress unnecessary current consumption. Further, since the output stage of the power-on reset signal is composed of the NPN transistor 23 and the parasitic PNP transistor 54 is formed by additionally forming the P + region 53, the operation speed of the NPN transistor 23 can be improved.

(Second embodiment)
FIG. 5 shows a second embodiment of the present invention. The same parts as those in the first embodiment are denoted by the same reference numerals and the description thereof is omitted. Only different parts will be described below. In the second embodiment, a circuit device 55 functionally identical to the circuit device 1 in the first embodiment is formed by a CMOS process.

  That is, the NPN transistor 23 and the PNP transistors 27 and 31 in the first embodiment are replaced with an N-channel MOSFET 56 and a P-channel MOSFET (operating current setting element, constant current setting element) 57 and 58, respectively. Incidentally, in the expressions (4) and (5) for the threshold voltage Vth and the constant current I, the emitter-collector voltage VBE is replaced with the FET threshold voltage VT. According to the second embodiment configured as described above, the same operational effects as those of the first embodiment can be obtained.

(Third embodiment)
FIG. 6 shows a third embodiment of the present invention, and only the parts different from the second embodiment will be described. The circuit device 59 of the third embodiment is formed of a so-called load MOS that uses the on-resistances of N-channel MOSFETs 60, 61, 62, and 63 instead of the resistors 24, 28, 29, and 32 of the second embodiment. It is.

  According to the third embodiment configured as described above, the resistance element for setting the reset release threshold value in the power-on reset circuit unit 59A and the constant current value of the constant current circuit unit 59B are set. Since the resistive element of FIG. 2 is composed of a load MOS composed of N-channel MOSFETs 60, 61, 62, and 63, the element having a high resistance value necessary for suppressing current consumption is formed as a diffused resistor. The area can be made very small. For example, when the resistance values of the FETs 61 and 62 are set to be equal, the resistance ratio can be set with high accuracy by taking the pair characteristics of the load MOS, so that the accuracy of the detection voltage can be improved.

(Fourth embodiment)
FIG. 7 shows a fourth embodiment of the present invention, and only different portions from the first embodiment will be described. In the circuit device 64 of the fourth embodiment, a capacitor 65 is disposed between the base of the transistor 23 and the ground line 26. According to the fourth embodiment configured as described above, a necessary reset time can be secured by appropriately selecting the capacitance of the capacitor 65. Therefore, even when the rise of the power supply VCC is very steep, the reset can be reliably performed.

(5th Example)
FIG. 8 shows a fifth embodiment of the present invention, and only different portions from the first embodiment will be described. In the circuit device 66 of the fifth embodiment, a resistor 67 and a PNP transistor 68 are arranged between the base of the transistor 27 and the ground line 26. That is, the connection between the base and the collector of the transistor 27 is cut off, the emitter of the transistor 68 is connected to the base of the transistor 27 via the resistor 67, the collector is connected to the ground line 26, and the base is connected to the collector of the transistor 27. It is connected.
The resistor 67 and the transistor 68 are provided for correcting the base current of the constant current circuit portion 66B, and the characteristic deviation due to the influence of hFE of the transistor 27 can be reduced. Further, if a separate resistor is inserted on the emitter side of the transistors 27 and 31, the variation in VBE can be absorbed.

(Sixth to tenth embodiments)
9 to 13 show sixth to tenth embodiments of the present invention. These embodiments correspond to the first to fifth embodiments, in which the output logic of the power-on reset signal is reversed (that is, made low active), and the constant current circuit unit has a sink configuration. For example, the circuit device 69 of the sixth embodiment shown in FIG. 9 replaces the NPN transistors 22 and 30 arranged on the power supply line 25 side in the first embodiment with an NPN transistor 70 (operating current setting) on the ground line 26 side. Element, constant current setting element) 71. Further, instead of the NPN transistor 23, a PNP transistor 72 is disposed on the power supply line 25 side, the collector of the transistor 72 is an output terminal for a power-on reset signal, and the collector of the transistor 71 is a constant current output terminal. .

  In the circuit device 73 of the seventh embodiment shown in FIG. 10, the transistors 70, 71, 72 of the sixth embodiment are replaced with MOSFETs 74 (operation current setting elements, constant current setting elements), 75, 76. The circuit device 77 of the eighth embodiment shown in FIG. 11 is obtained by replacing the resistors 24, 28, 29, and 32 of the circuit device 73 with MOSFETs 78, 79, 80, and 81 as load MOSs.

The circuit device 82 of the ninth embodiment shown in FIG. 12 is provided with a capacitor 83 between the power line 25 and the transistor 72 of the sixth embodiment, and the circuit device of the tenth embodiment shown in FIG. A resistor 84 and an NPN transistor 86 are provided between the power supply line 25 of the sixth embodiment and the base of the transistor 70.
According to the sixth to tenth embodiments configured as described above, the same effects as those of the first to fifth embodiments can be obtained.

(11th and 12th embodiments)
FIGS. 14 and 15 show the eleventh and twelfth embodiments of the present invention and show application examples of the circuit device shown in the first to tenth embodiments. For example, in the eleventh embodiment shown in FIG. 14, the circuit device 21 outputs a power-on reset (POR) signal to the logic circuit (logic circuit section) 88, and the transistor 31 of the constant current circuit section 30 is an analog circuit. (Analog circuit portion) 89 is incorporated as a part. An output signal obtained as a result of the operation in the logic circuit 88 is supplied to the analog circuit 89 and output to the outside.

  Further, the twelfth embodiment shown in FIG. 15 shows a case where the circuit device 55 composed of MOSFET is applied to a logic circuit (logic circuit section) 90 and an analog circuit (analog circuit section) 91 which have a function of application. . The analog circuits in these configuration examples may have an inverter output or a buffer output configuration. The logic circuit may be bipolar logic, CMOS logic, or IIL.

(Thirteenth embodiment)
FIG. 16 shows a thirteenth embodiment of the present invention, which shows a more specific application example of the circuit device shown in the first to tenth embodiments. FIG. 16 is a functional block diagram showing a configuration of a transceiver circuit used for communication using an in-vehicle LAN in a vehicle. This transceiver circuit is configured as a part of the vehicle control ECU. The battery power source + B is supplied to the constant voltage circuit 93 for generating the control power source 5V via the low voltage cut circuit 92. The voltage output from the constant voltage circuit 93 is supplied to, for example, the circuit device 21 and other components in the first embodiment.

  The power-on reset signal POR output by the circuit device 21 is given to a timer circuit (logic circuit unit) 94. The timer circuit 94 is a timer that is started when a wake-up signal is output by one of the two wake-up circuits 95 and 96, and the internal logic is reset by a power-on reset signal. . The constant current supplied by the circuit device 21 is supplied to these two wake-up circuits (analog circuit units) 95 and 96.

The external switch wakeup circuit 95 outputs a wakeup signal when, for example, a wakeup switch (not shown) is operated by a user. The LIN bus wakeup circuit 96 is a LIN bus that is a type of in-vehicle LAN standard. When the data is received via the wake-up signal, the wake-up signal is output.
The timer circuit 94 starts a count operation when the wake-up signal becomes active, and outputs a count-up signal to an INH (inhibit) output circuit 97 when a predetermined time is counted. The INH output circuit 97 receives the count-up signal, and outputs an INH signal to a CPU that constitutes a vehicle control ECU (not shown), for example. The CPU monitors whether the INH signal becomes active by interrupting or polling, and outputs an enable signal EN to the trapezoidal wave generation circuit 98 when the INH signal becomes active. That is, this transceiver circuit is configured as a peripheral circuit of the CPU.

When the trapezoidal wave generation circuit 98 receives the serial data TX transmitted from the CPU, the trapezoidal wave generation circuit 98 generates a trapezoidal wave signal based on the waveform of the serial data and outputs it to the driver circuit 99 in order to reduce the unnecessary radiation level. The driver circuit 99 outputs the trapezoidal wave signal to the LIN bus. The overheat protection / overcurrent limiting circuit 100 monitors whether or not the driver circuit 99 is in an overheated state or an overcurrent state, and when those states are detected, the operation of the driver circuit 99 is limited and protected. To do.
On the other hand, the data received via the LIN bus is given to the LIN bus wakeup circuit 96 and the receiver circuit 101 described above. The receiver circuit 101 transmits serial data RX to the CPU according to the received data.

  In the transceiver circuit (I / O circuit) 102 configured as described above, the wake-up circuit 95, even during sleep (in this case, the operation of the timer circuit 94 and the trapezoidal wave generation circuit 98 is stopped) Since 96 needs to operate in preparation for the occurrence of a wake-up factor, an operating current is supplied from the circuit device 21. If the timer circuit 94 is not reset when the battery power supply + B is turned on, an accurate count operation cannot be guaranteed. Therefore, by applying the circuit device 21 and configuring the entire transceiver circuit 102 as a semiconductor integrated circuit having a trench isolation structure as described in the first embodiment, it is possible to configure a system with excellent noise resistance. It becomes.

  As described above, according to the thirteenth embodiment, the circuit device 21 is applied to the transceiver circuit 102 that transmits / receives serial data to / from the CPU constituting the vehicle control ECU for data transmitted / received via the LIN bus. did. That is, since the vehicle control ECU is very demanded to reduce power consumption in order to suppress battery consumption, the circuit device 21 of the present invention can be applied very effectively.

The present invention is not limited to the embodiments described above and shown in the drawings, and the following modifications or expansions are possible.
When it is necessary to supply a constant current by a source type and output a power-on reset signal in a low active state, in the configuration of the first to fifth embodiments, a logic inversion is applied to the output stage of the power-on reset signal. These elements may be added.

The circuit devices applied to the first to thirteenth embodiments may be appropriately selected from the circuit devices according to the first to tenth embodiments in accordance with the surrounding design specifications.
The present invention is not limited to the vehicle control ECU, and can be widely applied to any configuration including a logic circuit that needs to be reset when the power is turned on and an analog circuit that needs to continue to supply a predetermined level of operating current. .

1 is a diagram showing an electrical configuration of a circuit device according to a first embodiment of the present invention. The figure which shows the semiconductor structure of a PNP transistor typically FIG. 2 equivalent diagram when a PNP transistor is formed by junction isolation FIG. 2 equivalent diagram of the NPN transistor arranged at the output stage of the reset signal FIG. 1 equivalent view showing a second embodiment of the present invention. FIG. 1 equivalent view showing a third embodiment of the present invention. FIG. 1 equivalent view showing a fourth embodiment of the present invention. FIG. 1 equivalent view showing a fifth embodiment of the present invention. FIG. 1 equivalent view showing a sixth embodiment of the present invention. FIG. 1 equivalent view showing a seventh embodiment of the present invention FIG. 1 equivalent view showing an eighth embodiment of the present invention. FIG. 1 equivalent diagram showing a ninth embodiment of the present invention. FIG. 1 equivalent view showing a tenth embodiment of the present invention. Functional block diagram showing an application example of the circuit device shown in the above embodiment, which is an eleventh embodiment of the present invention (No. 1) FIG. 14 equivalent diagram showing the twelfth embodiment of the present invention (No. 2) FIG. 13 is a functional block diagram showing an electrical configuration when the circuit device shown in the above embodiment is applied to a vehicle transceiver circuit according to a thirteenth embodiment of the present invention. 1 equivalent diagram showing the prior art

Explanation of symbols

In the drawings, 21 is a circuit device, 22 is a power-on reset circuit unit, 27 is a PNP transistor (operating current setting element, constant current setting element), 30 is a constant current circuit unit, 54 is a parasitic PNP transistor, and 55 is Circuit device, 57 is a P-channel MOSFET (element for setting operating current, element for setting constant current), 59 is a circuit device, 60 is an N-channel MOSFET, 64 and 66 are circuit devices, and 70 is an NPN transistor (operating current setting) Element, constant current setting element), 73 is a circuit device, 74 is an N-channel MOSFET (operating current setting element, constant current setting element), 82 and 84 are circuit devices, and 88 is a logic circuit (logic circuit section). 89 is an analog circuit (analog circuit portion), 90 is a logic circuit (logic circuit portion), 91 is an analog circuit (analog circuit portion), and 94 is a timer circuit (logic). Road section), 95 and 96 the wake-up circuit (analog circuit), 102 denotes a transceiver circuit (I / O circuit).

Claims (5)

A power-on reset circuit unit that outputs a power-on reset signal to the logic circuit unit based on the state of the power supply voltage;
A constant current circuit unit that generates a constant current based on the power source and supplies the current to the analog circuit unit,
A circuit device comprising an operating current setting element for supplying an operating current in the power-on reset circuit section and a constant current setting element in the constant current circuit section in common. The setting element is composed of a PNP transistor,
2. The circuit device according to claim 1, wherein each circuit element is formed by a trench isolation structure . The output stage of the power-on reset signal is composed of an NPN transistor,
A parasitic PNP transistor having an emitter connected to the base region of the NPN transistor and a collector connected to the emitter region side of the NPN transistor is formed in order to discharge the charge accumulated in the base region of the NPN transistor at high speed. The circuit device according to claim 2. Each circuit element is formed by a CMOS process,
A resistance element for setting a reset release threshold value in the power-on reset circuit section and a resistance element for setting a constant current value in the constant current circuit section are configured using CMOS elements. circuit device according to claim 1 wherein. 5. The circuit device according to claim 1 , wherein the circuit device is configured as a part of a vehicle control ECU and is applied to an I / O circuit that outputs a signal to a CPU constituting the ECU. .

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