JP4118169B2 - Gas discharge panel - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a gas discharge panel. More particularly, the present invention relates to a gas discharge panel of accidental discharge or dielectric discharge breakdown is prevented. The gas discharge panel of the present invention is particularly useful for an AC plasma display panel having a three-electrode surface discharge structure.
[0002]
[Prior art]
As the gas discharge panel, a plasma display panel (PDP), a plasma address liquid crystal device (PALC), and the like are known. Among them, the PDP is large and thin, and is one of the display devices that are widely sold at present.
FIG. 1 is a schematic perspective view of an AC type PDP having a typical three-electrode surface discharge structure in practical use. The PDP in FIG. 1 includes a front side substrate and a back side substrate.
[0003]
First, the front substrate 10 generally includes a plurality of display electrodes (X, Y) formed on a glass substrate 11, a dielectric layer 17 formed so as to cover the display electrodes (X, Y), a dielectric The protective film 18 is formed on the body layer 17 and exposed to the discharge space.
The display electrode (X, Y) includes a transparent electrode film 41 and a bus electrode 42 narrower than the transparent electrode film laminated on the edge of the transparent electrode film 41 for reducing the resistance of the transparent electrode film. Become.
[0004]
Next, the back substrate 20 is generally formed of a plurality of address electrodes A formed on the glass substrate 21, a dielectric layer 24 covering the address electrodes A, and a dielectric layer 24 between adjacent address electrodes. A plurality of strip-shaped partition walls 29 formed, and a phosphor layer (28R, 28G, 28B) formed between the partition walls 29 including a wall surface.
The front substrate and the rear substrate are opposed to each other with the electrodes facing inside so that the display electrodes and the address electrodes are orthogonal to each other, the periphery of the substrate is sealed with seal glass, and the space surrounded by the partition walls 29 is formed. The PDP 100 can be formed by filling a discharge gas (eg, Ne—Xe gas). In FIG. 1, R, G, and B respectively indicate red, green, and blue unit light-emitting areas, and each pixel is configured with RGB arranged in the horizontal direction.
[0005]
The PDP having the above configuration is first reset by applying a large voltage between the display electrodes X and Y, and then plasma-discharged between the display electrode Y that also serves as a scan electrode and the address electrode A, and is maintained between the electrodes X and Y. Using the wall charges accumulated by applying a voltage, a sustain discharge is performed according to the desired luminance. The discharge gas is excited and ionized by the sustain discharge, whereby vacuum ultraviolet rays are emitted. When the emitted vacuum ultraviolet rays hit the phosphor, visible light is emitted from the phosphor, and this visible light is used for display.
[0006]
As a result of the plasma discharge generated between the scan electrode Y and the address electrode A, space charge is generated, and most of it is accumulated on the dielectric layer on the electrodes X and Y. Further, a part of the generated space charge is used as a seed discharge for writing discharge between the adjacent scan electrode Y and address electrode A.
Part of the generated space charge moves in the extension direction of the address electrode along with the scanning of the electrode, and is accumulated in the vicinity of the first and last scan electrodes Y. When the accumulated space charge becomes large, it may be accidentally discharged (accidental discharge). In addition, the dielectric layer is destroyed (dielectric discharge destruction) by accidental discharge, and as a result, a non-lighting defect may occur, thereby degrading the image quality.
In order to prevent accidental discharge and dielectric discharge breakdown, a technique is known in which excessively accumulated space charge is released by mixing a conductive filler in the dielectric layer (Japanese Patent Laid-Open No. 10-64434: Patent Document). 1)
[0007]
[Patent Document 1]
Japanese Patent Laid-Open No. 10-64434
[Problems to be solved by the invention]
In recent years, the amount of accumulated space charge has increased due to the increase in size, definition, and speed of driving of the PDP, and it is desired to provide a dielectric layer that can release the space charge more effectively.
[0009]
[Means for Solving the Problems]
In order to solve the above-mentioned problems, the inventors of the present invention tried to reduce the thickness of the dielectric layer and increase the amount of the conductive filler. However, the former reduction in the thickness of the dielectric layer has led to diffusion of the electrode material into the dielectric layer, and it has been found that the breakdown voltage between the electrodes is significantly deteriorated due to the deterioration of the film quality of the dielectric layer. It has been found that the increase in the amount of the latter conductive filler causes aggregation of the filler itself, and the charge retention characteristics cannot be obtained over the entire panel surface.
[0010]
As a result of further studies, the inventors of the present invention have found that the dielectric layer contains a filler having conductivity or semiconductor characteristics so that the charge retention amount of the dielectric layer falls within a specific range, thereby allowing accidental discharge or dielectric. Surprisingly, it has been found that body discharge breakdown can be effectively prevented, and the present invention has been achieved.
[0011]
Thus, according to the present invention, the discharge space Nde clamping a pair of substrates separated by opposing partition walls, comprising a plurality of display electrodes on a surface of one of the discharge space side of the substrate, the substrate of the other side A gas discharge panel comprising a plurality of address electrodes on the surface of the discharge space and a dielectric layer covering the address electrodes, the dielectric layer comprising a spherical filler exhibiting electrical conductivity or semiconductor characteristics contained, have a following charge retention amount 0.8 kV, the filler is at least partially protrudes from the surface of the dielectric layer, the average particle size of the filler is greater than the thickness of the dielectric layer, wherein the filler gas discharge panel is provided protruding amount from the surface of the dielectric layer, characterized in 2~12μm der Rukoto.
[0013]
DETAILED DESCRIPTION OF THE INVENTION
A gas discharge panel according to the present invention includes a pair of substrates separated by a partition wall with a discharge space therebetween, an electrode formed on the surface of at least one of the substrates on the discharge space side, and a dielectric layer covering the electrode. It is not particularly limited as long as it is a panel that provides and displays using gas discharge, and examples thereof include PDP and PALC.
One feature of the present invention is that the dielectric layer contains a filler having conductivity or semiconductor characteristics and has a charge retention of 0.8 KV or less.
[0014]
The dielectric layer that can be used in the present invention is not particularly limited, and a known dielectric layer can be used as long as a predetermined charge retention amount can be obtained. For example, a dielectric layer made of low-melting glass such as PbO—B ₂ O ₅ —SiO series or ZnO—B ₂ O ₅ —Bi series can be used.
Examples of the filler that can be used in the present invention include conductive fillers such as tin oxide and indium tin oxide, and fillers having semiconductor characteristics such as silicon, silicon carbide, and titanium oxide. Further, the surface of insulating particles such as silicon oxide and boron nitride, a conductive film such as tin oxide and indium tin oxide, or a film having semiconductor characteristics such as silicon, silicon carbide, and titanium oxide (for example, 0.05 to 2 μm). May be used. The shape of the filler is not particularly limited as long as a predetermined charge retention amount can be obtained. Specifically, it is preferably spherical.
[0015]
Among the fillers, a filler or a coating made of tin oxide is preferable from the viewpoint of reactivity with a dielectric layer material (PbO—B ₂ O ₅ —SiO or ZnO—B ₂ O ₅ —Bi-based material).
Examples of the method for producing the filler include (1) a method of pulverizing a bulk, and (2) a chemical synthesis method as a method of obtaining particles of μm order. Among these, the latter method is preferable because there is little variation in particle size. Furthermore, a sol-gel method can be cited as a method for forming a film on the filler. Specifically, the film can be formed by immersing a filler in a precursor solution of the film and baking it.
Furthermore, in the present invention, the dielectric layer has a charge holding amount of 0.8 KV or less. The reason why the charge retention amount is specified will be described below.
[0016]
FIG. 2 shows the relationship between the charge retention amount and the failure occurrence rate (incidence of accidental discharge and dielectric discharge breakdown). The charge retention amount was a value obtained when 10 KV was applied to the dielectric layer film by using corona discharge and saturated. At that time, a panel is manufactured so that electric charge leaks from the address electrode through the conductive filler. FIG. 10 shows the configuration of the panel used for measuring the relationship between the charge retention amount and the defect occurrence rate.
The charge retention amount was measured using a STATIC HONESTEMETER H-0110 model manufactured by Shindo Denki Co., Ltd., and the defect occurrence rate was determined by panelizing a substrate manufactured under the same conditions as the substrate whose charge retention amount was measured in advance. Was measured by counting.
[0017]
FIG. 2 shows that the defect occurrence rate has increased since the charge retention amount has exceeded 0.8 KV, and the charge retention amount of the dielectric film needs to be 0.8 KV or less. I understand that. Note that the lower limit of the charge holding amount is determined by the charge holding amount capable of writing discharge. In this experiment, discharge was sufficiently generated even at 0.4 KV. In FIG. 2, a dotted line along the vertical axis means a line having a charge holding amount of 0.8 KV.
The thickness of the dielectric layer is not particularly limited as long as a predetermined charge retention amount can be obtained. A preferable thickness is 8 μm or more. In the present invention, the thickness means an average thickness.
[0018]
FIG. 3 shows the relationship between the thickness of the dielectric layer and the dielectric layer defect width. Here, the dielectric layer defect width means α in FIG. Specifically, an oxide film b is usually formed on the surface of the electrode a (FIG. 4A). A dielectric layer forming material film c is formed so as to cover the electrode a (FIG. 4B). When the dielectric layer forming material film c is baked, the oxide film d diffuses into the dielectric layer e (FIG. 4C). When the oxide film exceeds the diffusion limit, a defect is generated on the surface of the dielectric layer eno (FIG. 4D). The width α where the defect occurs is the dielectric layer defect width.
[0019]
In FIG. 3, the thickness of the dielectric layer was measured with a stylus type step difference measuring machine. Further, PbO—B ₂ O ₃ —SiO ₂ glass was used for the dielectric layer, and the firing temperature was 590 ° C. In FIG. 3, electrode condition 1 means an electrode oxide film of about 10 μm, electrode condition 2 means an electrode oxide film of about 8 μm, electrode condition 3 means an electrode oxide film of about 5 μm, and electrode condition 4 is an electrode. The oxide film means about 2 μm, and the electrode condition 5 means about 0 μm of electrode oxide film. The electrode oxide film thickness was measured by observing a cross section of the electrode with an SEM and using a line width measuring instrument attached to the SEM. The electrode condition is a condition in which the diffusion amount of the oxide film increases from 5 to 1. The amount of diffusion means a value obtained by observing the dielectric surface with a metal microscope and measuring with an attached scale.
[0020]
From FIG. 3, even if the diffusion amount of the oxide film of the electrode material changes, the dielectric layer defect width α can be suppressed, that is, the more preferable thickness of the dielectric layer that does not deteriorate the film quality of the dielectric layer is 10 μm. It is above, Especially preferably, it is 11 micrometers or more. In FIG. 3, a dotted line along the vertical axis means a line having a thickness of 11 μm.
Next, it is preferable that the filler protrudes from the surface of the dielectric layer.
The relationship between the amount of filler protruding from the surface of the dielectric layer and the charge retention amount is shown in FIGS. The filler used is a conductive filler in which the surface of spherical silicon oxide is coated with tin oxide at a thickness of 0.2 μm. In FIG. 5, particles having an average particle diameter of 12 μm, and in FIG. 6, particles having an average particle diameter of 18 μm are classified, so that particles having particle diameter distributions of 12 ± 3 μm and 18 ± 3 μm are formed in the dielectric layer. 1% by volume is used. The method for measuring the charge retention is the same as in FIG.
[0021]
5 and 6, it can be seen that an amount of protrusion larger than 0 μm is preferable in order to secure a charge holding amount of 0.8 KV or less. Furthermore, it can be seen that the amount of protrusion is preferably 12 μm or less in order to suppress the occurrence of manufacturing defects in the partition forming step. The dotted line along the left vertical axis in FIGS. 5 and 6 means a line having an amount of 2 μm protruding from the dielectric layer, and the dotted line along the right vertical axis in FIG. 6 means a 12 μm line.
The content of the filler in the dielectric layer is not particularly limited as long as a predetermined charge retention amount can be obtained.
[0022]
FIG. 7 shows the relationship between the filler content and the charge retention amount. The measurement conditions in FIG. 7 are the same as the conditions in FIG. 5 except that the filler content is changed. It can be seen from FIG. 7 that it is preferable to contain 1% by volume or more in order to secure a charge holding amount of 0.8 KV or less. The inventors have confirmed that this content is less than that in which the particle size distribution of the filler is not adjusted when trying to obtain the same charge retention amount. In addition, the upper limit of content is 3 volume% from a viewpoint of the process malfunction by particle aggregation. In FIG. 7, a dotted line along the vertical axis means a line having a filler content of 1% by volume.
[0023]
The method for forming the dielectric layer is not particularly limited, and any known method can be used. For example, a method of forming a dielectric layer containing the filler by applying a paste containing at least a filler and a dielectric material on a substrate so as to cover the electrode, and firing the obtained coating film. A thickener or a solvent for adjusting the viscosity may be added to the paste.
[0024]
The board | substrate, electrode, and partition which comprise the gas discharge panel of this invention are not specifically limited, All can use a board | substrate, an electrode, and a partition well-known in the said field | area.
Furthermore, the present invention relates to an AC type PDP having a three-electrode surface discharge structure comprising a front side substrate having a pair of display electrodes and a back side substrate having an address electrode facing the display electrodes and covered with a dielectric layer. A dielectric layer containing a filler is preferably used for the dielectric layer covering the address electrodes.
Hereinafter, a three-electrode AC type surface discharge PDP in which the present invention can be used will be described with reference to FIG.
[0025]
The PDP 100 in FIG. 1 includes a front side substrate and a back side substrate.
First, the front substrate is composed of a plurality of display electrodes formed on the substrate 11, a dielectric layer 17 formed so as to cover the display electrodes, and a protective layer 18 formed on the dielectric layer 17 and exposed to the discharge space. It consists of.
The substrate 11 is not particularly limited, and examples thereof include a glass substrate, a quartz glass substrate, and a silicon substrate.
[0026]
The display electrode is made of a transparent electrode 41 such as ITO. Further, in order to reduce the resistance of the display electrode, a bus electrode (for example, a three-layer structure of Cr / Cu / Cr) 42 may be formed on the transparent electrode 41.
The dielectric layer 17 is formed of a material usually used for PDP. Specifically, it can be formed by applying a paste made of a low melting point glass and a binder on a substrate and baking it.
The protective layer 18 is provided to protect the dielectric layer 17 from damage caused by ion collision caused by discharge during display. The protective layer 18 is made of, for example, MgO, CaO, SrO, BaO or the like.
[0027]
Next, the back side substrate includes a plurality of address electrodes A formed on the substrate 21 in a direction intersecting with the display electrodes, a dielectric layer 27 covering the address electrodes A, and a dielectric layer between the adjacent address electrodes A. 27 includes a plurality of stripe-shaped partition walls 29 formed on the surface 27 and a phosphor layer 28 formed between the partition walls 29 including a wall surface. In FIG. 1, R, G, and B mean unit light emitting regions (discharge cells) that emit red, green, and blue light.
As the substrate 21, the same type as the substrate 11 constituting the front side substrate can be used.
[0028]
As the dielectric layer 27, the dielectric layer of the present invention having a charge retention characteristic of 0.8 KV or less including a filler can be used.
The address electrode A is made of, for example, a metal layer such as Al, Cr, or Cu, or a three-layer structure of Cr / Cu / Cr.
The partition walls 29 can be formed by applying a paste made of a low melting point glass and a binder on the dielectric layer 27, drying, and then cutting by a sandblast method. Further, when a photosensitive resin is used for the binder, it can be formed by baking after exposure and development using a mask having a predetermined shape.
[0029]
The formation method of the fluorescent substance layer 28 is not specifically limited, A well-known method is mentioned. For example, the phosphor layer 28 is formed by applying a paste in which a phosphor and an inorganic oxide are dispersed in a solution in which a binder is dissolved in a solvent, between the barrier ribs 29 and baking in an inert atmosphere. Can do.
Next, the front substrate and the rear substrate are opposed to each other with the electrodes facing inward so that the display electrodes (41, 42) and the address electrodes A are orthogonal to each other, and a discharge gas is introduced into the space surrounded by the partition walls 29. The PDP 100 can be formed by filling.
[0030]
【Example】
EXAMPLES Hereinafter, the present invention will be described more specifically with reference to examples, but the present invention is not limited thereto.
Example 1
Particles having an average particle diameter of 12 μm, in which tin oxide 2 was coated on the surface of spherical silicon oxide particles 1 by 0.2 μm, were classified to obtain filler 3a having a particle size distribution of 12 ± 3 μm. Next, on the substrate 21 on which the address electrode A (material: Cr / Cu / Cr) is formed with a film thickness of 2 μm, the frit glass (78 wt%), the filler (1 wt%), the ethyl cellulose binder (˜2). A coating film was formed by printing a paste mixed with (weight%), and baked at 590 ° C. for 30 minutes in a conveyor type baking furnace to form a dielectric layer 27 having a thickness of 8 μm. In the obtained dielectric layer 27, the filler 3a was exposed from the average surface of 4 μm. The charge retention amount of the dielectric layer 27 was measured and found to be 0.78 KV.
[0031]
Next, the rear side substrate was obtained by forming the partition walls 29 and the phosphor layer 28 by a known method.
Further, the substrate 11 obtained by a known method is opposed to the front side substrate having the display electrode 4 composed of a transparent electrode and a bus electrode, the dielectric layer 17 (thickness 30 μm) and the protective film 18, By sealing and injecting discharge gas, a three-electrode surface discharge PDP having a structure shown in FIG. 8A and a partially enlarged view of FIG. 8B was obtained.
[0032]
A specific PDP configuration will be described below.
Display electrode Transparent electrode width: 280 μm, Bus electrode width 100 μm
Discharge gap between display electrodes 100μm
Partition height 100μm
Partition arrangement pitch 360μm
Ne-Xe (5%) discharge gas pressure 500 Torr
The obtained PDP had no accidental discharge or dielectric layer discharge breakdown.
[0033]
Example 2
A back side substrate was obtained in the same manner as in Example 1 except that a filler having a particle size distribution of 14 ± 3 μm was used and the thickness of the dielectric layer was 12 μm. In the obtained dielectric layer, the filler was exposed from the surface having an average of 2 μm. The charge retention of the dielectric layer was measured and found to be 0.71 KV.
When a PDP was fabricated in the same manner as in Example 1, no accidental discharge or dielectric layer discharge breakdown occurred.
In the PDP of Example 1, since the dielectric layer is thin, defects may occur in the dielectric layer due to diffusion of the oxide film generated in the address electrode, and display characteristics may be problematic. In the PDP of Example 2, such a problem did not occur.
[0034]
Comparative Example 1
A back side substrate was obtained in the same manner as in Example 1 except that 2% by weight of filler 3b made of Cr particles having an average particle diameter of 8 μm was used and the thickness of the dielectric layer was 10 μm. It was 1.57 KV when the electric charge retention of the dielectric material layer was measured.
When a PDP was fabricated in the same manner as in Example 1, accidental discharge and dielectric layer discharge breakdown occurred. 9A is a cross-sectional view of the PDP of Comparative Example 1, and FIG. 9B is a partially enlarged view of FIG. 9A.
[0035]
Comparative Example 2
A back side substrate was obtained in the same manner as in Example 1 except that 6% by weight of filler composed of Cr particles having an average particle diameter of 8 μm was used. Aggregation of fillers was confirmed in the obtained dielectric layer. When the charge retention amount of the dielectric layer was measured, it was uneven within the plane and could not be measured.
When a PDP was fabricated in the same manner as in Example 1, accidental discharge and dielectric layer discharge breakdown occurred.
[0036]
【The invention's effect】
According to the present invention, the dielectric layer constituting the gas discharge panel contains a filler having conductivity or semiconductor characteristics and has a charge retention of 0.8 KV or less, so that accidental discharge or dielectric discharge breakdown can be prevented. A prevented gas discharge panel can be provided.
[Brief description of the drawings]
FIG. 1 is a schematic perspective view of an AC type PDP having a three-electrode surface discharge structure.
FIG. 2 is a graph showing a relationship between a charge retention amount and a failure occurrence rate (incidence of accidental discharge and dielectric discharge breakdown).
FIG. 3 is a graph showing the relationship between the thickness of the dielectric layer and the defect width of the dielectric layer.
FIG. 4 is a diagram for explaining a dielectric layer defect width;
FIG. 5 is a graph showing the relationship between the amount of filler protruding from the surface of a dielectric layer and the charge retention amount.
FIG. 6 is a graph showing the relationship between the amount of filler protruding from the surface of the dielectric layer and the charge retention amount.
FIG. 7 is a graph showing the relationship between filler content and charge retention.
FIG. 8 is a cross-sectional view of the PDP according to the first embodiment.
9 is a cross-sectional view of a PDP of Comparative Example 1. FIG.
FIG. 10 is a configuration diagram of a panel used for measuring the relationship between the charge retention amount and the defect occurrence rate.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 Silicon oxide particle 2 Tin oxide 3a, 3b Filler 4 Display electrode 11, 21 Board | substrate 17, 27 Dielectric layer 18 Protective layer 28 Phosphor layer 29 Partition 41 Transparent electrode 42 Bus electrode 100 PDP
A Address electrode R Region that produces red light emission G Region that produces green light emission B Region that produces blue light emission a Electrode b Oxide film c Dielectric layer forming material film d Diffused oxide film e Dielectric layer α Dielectric layer defect width

Claims (6)

The discharge space Nde clamping a pair of substrates separated by opposing partition walls, comprising a plurality of display electrodes on a surface of one of the discharge space side of the substrate, other side of the substrate in the discharge space side of the surface A gas discharge panel comprising a plurality of address electrodes and a dielectric layer covering the address electrodes, wherein the dielectric layer contains a spherical filler exhibiting electrical conductivity or semiconductor characteristics, and is 0.8 KV or less the have a charge holding amount, the filler is at least partially protrudes from the surface of the dielectric layer, the average particle size of the filler is greater than the thickness of the dielectric layer, from the surface of the dielectric layer of the filler gas discharge panels protruding amount and wherein 2~12μm der Rukoto. The filler is a gas discharge panel according to claim 1 consisting of particles having a particle size distribution of the average particle diameter ± 3 [mu] m.   The gas discharge panel according to claim 1, wherein the dielectric layer has a thickness of 10 μm or more. The gas discharge panel according to any one of claims 1 to 3 , wherein the filler is present in an amount of 1 to 3% by volume with respect to the dielectric layer. The filler, the conductive film or a gas discharge panel according to any one of claims 1 to 4 which is a silicon compound particles covered with the semiconductor film. The gas discharge panel according to claim 5 , wherein the conductive film or the semiconductor film is selected from films made of tin oxide, indium tin oxide, silicon, silicon carbide, and titanium oxide.

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