JP4113316B2 - Method and apparatus for programming non-volatile memory by controlling source current pull-down rate - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
BACKGROUND OF THE INVENTION
The present invention relates to memory cell circuit devices, and in particular to methods for programming non-volatile memory cells. The programming current is controlled through the use of current pull-down circuits at the source gate of the cell. The pull-down circuit is speed controllable and can be configured to change its speed to compensate for device process variations.
[Description of related technology]
Non-volatile memory cells are CMOS devices arranged to implement EPROM (electrically programmable read-only memory) and EEPROM (electrically erasable programmable read-only memory), Includes devices such as NMOS devices and bipolar transistor devices. The storage transistor used in a memory cell is generally a variation of an NMOS transistor, where the cell charges a section of polysilicon floating in a region of silicon dioxide above the P-substrate material of the device. This floating region (called floating gate) is located between the P-substrate material, including the drain and source gate, and the control gate. Silicon dioxide is generally about 8-12 nanometers thick and insulates the floating gate polysilicon from the control gate on the N-channel device.
[0002]
An electrically induced avalanche injection mechanism is used to charge the floating gate from the substrate. Application of a high voltage across the device drain and source gates induces a current to flow through the substrate. As this current flows, various hot electrons jump from the substrate material to the floating gate, creating a useful charge on the device. This charge is retained until released by various techniques including, for example, the application of ultraviolet light or X-rays or the formation and use of electrical tunneling effects (eg, Fowler-Nordheim tunneling mechanism).
[0003]
In applying a voltage across the substrate, if the voltage is too high, related side effects such as punch-through and drain turn-on can impact reliability and predictability when programming memory devices. In an actual product configuration, there are generally other cells placed in parallel with the programming cells. Such a configuration may make the side effects even more severe and may increase the programming current than required. And it is inefficient. Such concerns become even more common as the size of memory cell devices decreases and the substrate thickness decreases. The layers associated with thinner substrates are more susceptible to damage from excessive programming currents.
[0004]
Yet another concern with the device is the ability to have enough current available to program the device. Today, there is a tendency to use less power, thereby creating devices that can contain only a single power supply for many cell arrangements or configurations. The internal high voltage is created through a charge pump circuit and then tied to the drain gate of the memory element to achieve the required voltage drop across the drain gate and source gate. Without sufficient voltage, the memory element cannot be programmed properly.
[0005]
For any voltage applied across the cell, the current flow through the device is affected by the relative conductivity of the cell. Such conductivity is affected by process variations in making the cell. Although manufacturers strive to obtain similarities with known results in device formation, process variations are inevitable to some extent and expensive to control. For example, if the overall process variation in building the device creates a higher conductivity, a larger programming current is created across the device when a voltage is applied. Larger currents than expected can cause punch-through and similar problems as described above. On the other hand, if the process variation produces a lower conductivity, a smaller programming current will occur with the application of the same voltage. Small currents beyond expectations can lead to invalid programming of the cell.
[0006]
Conventional attempts compensate for device processing characteristics by biasing the memory cell circuit. U.S. Pat. No. 5,218,571 provides a circuit that uses a process dependent reference power supply generator during a programming cycle. When the transistor conductivity is low, a lower source voltage is set. The low conductivity helps to increase the drain-source voltage drop and increases the resulting cell pass programming current. Conversely, higher transistor conductivity sets a higher source voltage, but higher conductivity helps to reduce the drain-source difference, thereby reducing the resulting current. This solution, however, does not help to control the current value of the programming current. The reference voltage is set to a particular level, depends on process variations and is maintained at that level for programming the memory cell device.
[0007]
Therefore, what is needed in the art is a method and apparatus that takes into account the controlled current value for programming the memory cell. When programming conditions are applied to the memory cell, the programming current must be controllable to a current value small enough to prevent hot electronic effects such as punch-through. The programming current must also be variable as needed to achieve current value programming goals and must be sensitive to device process variations.
[0008]
SUMMARY OF THE INVENTION
In accordance with the present invention, when a memory cell device is being programmed, the nonvolatile memory cell device and device are programmed to take into account a controlled current value for the current flow through the memory cell device. A method is provided. The device circuit includes a current limiter consisting of a transistor device connected to the source of the memory cell being programmed. The device circuit also includes a current mirror device connected to the EPROM miniarray at its drain node. A miniarray is used to control or pre-determine the amount of current that flows through the mirror device. The mirror device is further connected to a bias circuit that generates a gate voltage. The gate voltage is reflected from a predetermined current. This gate voltage is connected to the gate of the current limiter transistor device at the source of the memory cell. In addition, a high voltage source is connected to the drain-node of the memory cell to generate the drain-source voltage difference required for programming. Memory cells are selectively programmed through switching lines that provide access to individual cells.
[0009]
In order to program each memory cell device, the device is first selected to be switchable through memory block, column and row select lines. The drain and source nodes for the cell are then simultaneously connected to a high voltage level to reduce or eliminate the programmed cell drain-source voltage. At the same time, the gate of the programmed cell is tied to a specific voltage level. Thereafter, the voltage at the source node of the cell is lowered by a current limiter, while the pull-down rate is controlled by a current setting predetermined by a current mirror and mini-array. During this pull-down phase, the current flowing in the programmed cell is limited by the current limiter. And it prevents harmful hot electronic effects. When the drain-source voltage reaches a sufficiently large difference, cell programming begins. After source-side voltage pull-down, the gate of the programming cell is ultimately tied directly to the final voltage level or alternatively to a time-dependent function (eg, ramp signal).
[0010]
Accordingly, one aspect of the present invention is to provide a device circuit for programming a memory cell device that controls or limits the programming current through the memory cell to prevent harmful hot electronic effects. .
[0011]
Another aspect of the present invention provides a device circuit for maintaining proper and / or non-excessive programming current through a memory cell even though process variations result in higher or lower cell conductivity. That is.
[0012]
Yet another aspect of the present invention is to provide a circuit that results in a smaller source pull-down current and a higher source voltage if the cell conductivity is relatively low.
[0013]
Another related aspect of the present invention is to provide a circuit that results in a larger source pull-down current and a lower source voltage if the cell conductivity is relatively high.
[0014]
Yet another aspect of the present invention is to provide a programming method utilizing the above circuit to limit the memory cell current according to a controlled rate during programming. The speed is then set by a predetermined current passing through the current mirror device.
[0015]
Other aspects and advantages of the present invention can be appreciated by reference to the figures, the detailed description that follows, and the claims.
[Detailed explanation]
A detailed description of the present invention is provided with respect to FIGS. 1-2. Referring to FIG. 1, a circuit diagram 100 detailing the interconnection of the device of the present invention useful for providing a current through a memory cell at a controlled current value during a particular programming step is shown. A current mirror 102 is provided, which comprises P-type and N-type MOS transistor devices 104 and 106, as shown, connected to a voltage supply source VDD and an EPROM miniarray 108. The mini array 108 functions as a current source and includes a drain node coupled to the current mirror 102, a source node connected to ground, and a gate node supplied with a gate voltage PG. The level of the gate voltage PG defines the level of the current Ir flowing through the current mirror 102.
[0016]
Memory cells 150, 152 are arranged into a plurality of blocks and are selected for individual programming through block, row and column select lines. Two memory cells are shown. It shows that these representative cells labeled c0,0 and c31,0 are arranged with 32 rows. The switching word lines labeled SWL 0 and SWL 31 are used to program the individual gates of the selected memory cell. Switching line BWL n and transistor devices MBn, 0 and MBn, l are shown as representative devices for selecting a memory cell block. Transistor device MYS is used to select each memory cell column. A high voltage source 154 (also labeled DIBUF) is connected to the drain side of the memory cell through the column selection device MYS. The power supply 154 then functions to set the data line (DL) high during programming. The DIBUF element also functions as an input buffering device for data.
[0017]
Current mirror 102 is coupled to bias circuit 120. Circuit 120 comprises P-type and N-type MOS transistor devices 122-132 as shown and is coupled to power supply voltage VDD and ground. The circuit 120 functions to provide a bias voltage VGP that reflects the level of the set current Ir from the current mirror 102. VGP is used as the input to the gate of current limiter transistor device 140 (also labeled MTG). The device 140 is connected to the source side of the memory cell through the network of switching lines described above. In operation, the current passing through the current limiter 140 is a function of a constant multiple of the current Ir passing through the mirror device 102 (eg, m times the current Ir, ie, m * Ir). When current limiter 140 functions to pull down the source side of the selected memory cell (150 or 152), it controls the current value of the current flowing in the memory cell programmed with current m * Ir It works like As VGP changes, the value of m * Ir changes as well. Therefore, by controlling and / or defining the current through the current mirror 102, the source pull-down rate is similarly controlled on the memory cell. This pull-down rate functions to control the flow of programming current through the memory cell.
[0018]
Also referring now to FIG. 2, a representative timing diagram is shown for various input lines or nodes of device 100 from FIG. A program enable signal 200 is shown with a program period 202. The following methods can be used to program the device 100: Initially, and across the selected memory cell (eg, 0-31 selected above), the high voltage is applied to the signals ND (204) and NS (206, respectively) to minimize the drain-source voltage. ) Applied to both the source node and the drain node shown as. Immediately thereafter, a voltage source 154 is used to connect the data line DL, shown as signal 208, and hence the drain node ND, to a high voltage level. In such an example, an example of an applied voltage is approximately 6.5 volts. A voltage is then applied to the gate node of the selected cell through the SWL word line (SWLO to SWL31) shown in FIG. An example of the voltage (212) applied during this initial programming period is approximately 8 volts.
[0019]
Thereafter, the source side of the selected memory cell is pulled down by the current limiter 140 at a controlled and relatively slow rate. A known reference voltage Vcc is applied to the gate node PG of the EPROM miniarray 108 as shown by signal 212. As a result, a predetermined current Ir flows in the current mirror 102. A connected bias circuit 120 provides a power supply signal VGP that directly reflects the level of the current Ir.
[0020]
The VGP shown as signal 214 has a level of approximately 1.4 volts. Signal VGP is tied to the gate input node of current limiter device 140. VGP turns on the limiter and causes a current equal to m * Ir to flow. This signal is then shown as 216 at a level of approximately 100-250 microamps. In the period of application shown as 218, the current limiter functions as a pull-down of the source node of the memory cell shown as 220. By controlling the level of the current Ir of the current mirror, the pull-down speed indicated by the sloped curve 220 can be controlled to be a relatively slow speed. At some point along curve 220, the voltage difference between the drain and source of the memory cell is large enough to cause programming of the memory cell. The word line SWL of the memory cell is then also connected to one of the following final levels. (1) a level stepped up from the previous SWL voltage, as indicated by step 222, or (2) a time-dependent sloped upward level from the previous SWL voltage, as indicated by ramp 224. . Both provide proper programming of the cell, but time-dependent functions help to provide additional programming efficiency.
[0021]
If an improper voltage is applied for a particular conductivity condition, the overall cell conductivity of the memory element can affect programmability, leading to unexpected hot electronic effects. is there. Thus, the pull-down speed of the current limiter can be configured to compensate for the change in conductivity. In the present invention, the EPROM miniarray 108 can be made from the same process as the memory cells. It then relies on the same process used to build the memory cell. In general, if the overall device conductivity is low, the VGP created through the miniarray 108 is low. A lower VGP means that a smaller pull-down current is created through the limiter 140. Eventually, after the pull-down occurs, this smaller current creates a higher final voltage on the source node. In FIG. 2, this is indicated by portion 230 of the NS signal. Controlled pull-down of the source occurs at a relatively slower rate that aids in programming the memory cell with a relatively low conductivity. In general, the required drain-source difference is required for a longer period to allow for cell programming. Conversely, if the overall device conductivity is high, the VGP created is also high and the pull-down speed is relatively higher.
[0022]
A simplified example is as follows. Referring now to FIG. 3 (a), a floating gate memory cell device 240 is shown. The drain node, source node, and gate node are labeled D, S, and G, respectively. A current limiter 242 is shown tied to the source node and used to pull down the source node of the device. It is intended that this device 240 be implemented in accordance with the circuitry described above to achieve a controlled pull-down rate on the source. The speed is a function of the mirror current Ir. In this example, the conductivity of the cell is low, and as previously mentioned, the miniarray, current mirror, and bias circuit help to provide a lower VGP and hence a lower pull-down rate. FIG. 3 (b) shows a diagram of the supply voltage NS being pulled down from the first high level 243 at pull down point 244. Pull-down speed 246 is slower as a function of smaller Ir. Because of the smaller Ir, the final power supply voltage (shown as 248) after pulldown is relatively higher.
[0023]
Examples of high conductivity are shown in FIGS. 4 (a) and 4 (b). FIG. 4 (a) shows a similar floating gate memory cell device 260 having nodes labeled drain (D), source (S), and gate (G), respectively. A current limiter 262 is shown tied to the source node and is also used to pull down the source node of the device. In this case, the conductivity of the cell is high and the circuit described above provides a higher VGP and hence a higher pull-down speed. FIG. 4 (b) shows a diagram of the power supply voltage NS being lowered from the first high level 263 at the pull-down point 264. Pull-down speed 266 is relatively faster as a function of higher Ir. Due to the higher Ir, the final supply voltage after pull-down (shown as 268) is shown relatively low in FIG. 3 (b).
[0024]
Thus, process variations that may affect the formation and conductivity of memory cells can be used to affect devices that produce current values for pull-down currents on the source of memory devices as well. The devices described in the present invention can therefore be configured to provide advantageous source pull-down rates. It is then corrected according to cell conductivity conditions.
[0025]
The description of the preferred embodiment of the present invention has been presented for the purposes of illustration. It is not intended to be exhaustive or to limit the invention to the precise form disclosed. Obviously, many modifications and variations will be apparent to practitioners skilled in this field. It is intended that the scope of the invention be defined by the following claims and their equivalents.
[Brief description of the drawings]
FIG. 1 is a circuit diagram of a memory cell device, a switching line for selecting a memory cell to be programmed, a current limiter for a source node, and a bias circuit for generating a bias voltage for controlling the current limiter. 2 shows a current mirror of a predetermined current for selecting a bias voltage and a miniarray for setting a predetermined current.
FIG. 2 is a timing diagram showing voltages and resulting currents at various nodes on the circuit of FIG. 1 during a programming procedure.
FIG. 3 (a) is a circuit diagram showing a device having low cell conductivity and correspondingly lower pull-down speed applied to the source node of the device.
(b) is a diagram of the device power supply voltage NS showing the effect of a relatively low pull-down rate at the source node of the device.
FIG. 4 (a) is a circuit diagram showing a device having high cell conductivity and correspondingly higher pull-down speed applied to the source node of the device.
(b) is a diagram of the device power supply voltage NS showing the effect of a relatively higher pull-down rate at the source node of the device.

Claims (10)

A circuit that provides, at a controlled current value, a programming current that passes through a programmable memory cell device, the memory cell device being selectable for programming from a set of similar such devices for each memory The cell device has a respective drain node, source node, and gate node, the circuit comprising:
A current mirror device coupled to the current source device and generating a mirror current level defined by an input stimulus applied to the current source device;
Coupled to the current mirror device and coupled to the source node of the voltage biasing device and selected memory cell device that generates a bias voltage at a level proportional to the mirror current level, and is driven by the bias voltage And a current limiter device that generates a limiter current that is directly proportional to the mirror current level, the current limiter device pulling down the source node of the memory cell device at a controlled rate according to the mirror current are used to, the current source device is created during the same process as the memory cell device, therefore Chi lifting similar device conductivity, the current source device is a drain node, the source node, a gate node An EPROM array having a known voltage Is applied to the gate node of the EPROM array as the input stimulus for generating a mirror current. The lower device conductivity in the memory cell device and in the current source device results in a smaller mirror current for the input stimulus applied to the EPROM array, and the smaller mirror current is proportional. 2. The circuit of claim 1 , wherein the circuit results in a lower bias voltage and results in a smaller limiter current proportional to the bias voltage for pulling down the source node of the memory cell. Wherein in the memory cell devices, and, for higher device conductivity input stimuli given to the EPROM array in the current source device, and a larger mirror current result is greater than the mirror current proportional 2. The circuit of claim 1 , wherein the circuit results in a higher bias voltage and results in a larger limiter current proportional to the bias voltage for pulling down the source node of the memory cell. 2. The circuit of claim 1, wherein the current mirror device and the voltage bias applying device comprise N and P type MOS devices. A method of programming a non-volatile memory cell device having a drain node, a source node, and a gate node, the memory cell device having a word line coupled to the gate node and a drain node. The memory cell device is coupled to a current source device so as to be selectable by a coupled data line, and a current mirror that generates a mirror current and a bias applied voltage proportional to the mirror current are generated. A voltage biasing circuit coupled to a source node of the memory cell device and including an associated circuit including a current limiter driven by the biasing voltage;
In order to generate a small drain-source voltage difference, the drain node and source node of the selected memory cell device are coupled to a high voltage level,
Coupling the gate node of the selected memory cell device to a specific voltage level;
Coupling the data line of the selected memory cell device to a high voltage level;
Pull down the source node of the selected memory cell device at a controlled rate depending on a predetermined level;
The gate node of the selected memory cell device is coupled to a final programming level, and the current source device and the memory are configured such that process variations affecting device conductivity are common. look including the preceding process to create a cell device, said current source device drain node consists EPROM array having a source node, a gate node, a known voltage, said input for generating a mirror current A method comprising applying to a gate node of the EPROM array as a stimulus . Said step of pulling down the source node of the memory cell at a controlled rate depending on a predetermined level;
(I) activate the current source device associated with the current mirror to generate a defined mirror current; and (ii) use the voltage bias application circuit to generate a bias applied voltage proportional to the mirror current. And then
6. The method of claim 5 , further comprising the step of: (iii) using the bias applied voltage to generate a current limiter current proportional to the mirror current, the current limiter pulling down a source node. A method of programming selectable memory cell devices. 6. The non-volatile selectable according to claim 5 , wherein said last step of coupling a gate node couples the gate node to a final programming level that is a step increase from a previous level applied to the gate node. To program a simple memory cell device. The last step of coupling the gate node of claim 5 further comprising coupling the gate node from before that was applied to the gate node level to increase a is final programming level which depends on the time Of programming non-volatile selectable memory cell devices. 9. The method of programming a non-volatile selectable memory cell device according to claim 8, wherein the time-dependent increase is a ramp increase from a previous level that was applied to the gate node. 6. The non-volatile selectable memory cell of claim 5 , wherein when the conductivity of the fabricated device changes from low to high, the source current is set to a predetermined level that changes proportionally from low to high. How to program a device.

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