JP4112050B2 - コヒーレントメモリシステムにおいて強い順序づけを維持する方法およびシステム - Google Patents

コヒーレントメモリシステムにおいて強い順序づけを維持する方法およびシステム Download PDF

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Publication number
JP4112050B2
JP4112050B2 JP26432797A JP26432797A JP4112050B2 JP 4112050 B2 JP4112050 B2 JP 4112050B2 JP 26432797 A JP26432797 A JP 26432797A JP 26432797 A JP26432797 A JP 26432797A JP 4112050 B2 JP4112050 B2 JP 4112050B2
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Japan
Prior art keywords
memory
order
processor
transaction
arbitrator
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Expired - Fee Related
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JP26432797A
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English (en)
Japanese (ja)
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JPH10187534A5 (enExample
JPH10187534A (ja
Inventor
ケネス・チャニー
デイヴィッド・エム・チャスティーン
デイヴィッド・エム・パトリック
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HP Inc
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Hewlett Packard Co
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
    • G06F13/1652—Handling requests for interconnection or transfer for access to memory bus based on arbitration in a multiprocessor architecture
    • G06F13/1657—Access to multiple memories

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Multi Processors (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
JP26432797A 1996-09-27 1997-09-29 コヒーレントメモリシステムにおいて強い順序づけを維持する方法およびシステム Expired - Fee Related JP4112050B2 (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US720330 1985-04-05
US08/720,330 US5930822A (en) 1996-09-27 1996-09-27 Method and system for maintaining strong ordering in a coherent memory system

Publications (3)

Publication Number Publication Date
JPH10187534A JPH10187534A (ja) 1998-07-21
JPH10187534A5 JPH10187534A5 (enExample) 2005-06-16
JP4112050B2 true JP4112050B2 (ja) 2008-07-02

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JP26432797A Expired - Fee Related JP4112050B2 (ja) 1996-09-27 1997-09-29 コヒーレントメモリシステムにおいて強い順序づけを維持する方法およびシステム

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US (1) US5930822A (enExample)
JP (1) JP4112050B2 (enExample)

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9092595B2 (en) 1997-10-08 2015-07-28 Pact Xpp Technologies Ag Multiprocessor having associated RAM units
JP2002500395A (ja) * 1997-12-24 2002-01-08 クリエイティブ、テクノロジー、リミテッド 最適な多チャネル記憶制御システム
US6587931B1 (en) * 1997-12-31 2003-07-01 Unisys Corporation Directory-based cache coherency system supporting multiple instruction processor and input/output caches
US6081874A (en) * 1998-09-29 2000-06-27 International Business Machines Corporation Non-uniform memory access (NUMA) data processing system that speculatively issues requests on a node interconnect
US6167492A (en) 1998-12-23 2000-12-26 Advanced Micro Devices, Inc. Circuit and method for maintaining order of memory access requests initiated by devices coupled to a multiprocessor system
US6189061B1 (en) * 1999-02-01 2001-02-13 Motorola, Inc. Multi-master bus system performing atomic transactions and method of operating same
US6681320B1 (en) 1999-12-29 2004-01-20 Intel Corporation Causality-based memory ordering in a multiprocessing environment
KR100841130B1 (ko) * 2003-10-22 2008-06-24 인텔 코오퍼레이션 상호접속 네트워크를 통한 효율적인 순서화 저장을 위한방법 및 장치
US8117392B2 (en) * 2003-10-22 2012-02-14 Intel Corporation Method and apparatus for efficient ordered stores over an interconnection network
US7774562B2 (en) * 2004-09-17 2010-08-10 Hewlett-Packard Development Company, L.P. Timeout acceleration for globally shared memory transaction tracking table
US7600023B2 (en) * 2004-11-05 2009-10-06 Hewlett-Packard Development Company, L.P. Systems and methods of balancing crossbar bandwidth
US7694064B2 (en) * 2004-12-29 2010-04-06 Hewlett-Packard Development Company, L.P. Multiple cell computer systems and methods
GB2469299B (en) * 2009-04-07 2011-02-16 Imagination Tech Ltd Ensuring consistency between a data cache and a main memory

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0776942B2 (ja) * 1991-04-22 1995-08-16 インターナショナル・ビジネス・マシーンズ・コーポレイション マルチプロセッサ・システムおよびそのデータ伝送装置
JPH07114515A (ja) * 1993-10-19 1995-05-02 Hitachi Chem Co Ltd 同期通信用ネットワークを有する分散メモリ計算機
JP3599381B2 (ja) * 1994-09-12 2004-12-08 キヤノン株式会社 情報処理システム及びその方法
JPH09244984A (ja) * 1996-03-08 1997-09-19 Nippon Telegr & Teleph Corp <Ntt> イベント順序補正方法
JPH09282296A (ja) * 1996-04-10 1997-10-31 Hitachi Ltd 多重化ノード間通信制御方式

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JPH10187534A (ja) 1998-07-21
US5930822A (en) 1999-07-27

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