JP4108704B2 - Laser diode drive circuit - Google Patents

Description

  The present invention relates to a laser diode drive circuit, and more particularly to a laser diode drive circuit capable of accurately controlling the drive current of a laser diode used in a printer, an optical disk device, optical communication, or the like.

Semiconductor lasers are small and inexpensive, and can easily obtain laser light simply by flowing current. Therefore, semiconductor lasers are widely used in fields such as printers, optical disk devices, and optical communications.
FIG. 12 is a diagram showing a circuit example of a conventional laser diode driving circuit.
In FIG. 12, a laser diode drive circuit 100 includes a current source 101 whose output current changes according to an input control signal SCa, and an N-channel MOSFET (hereinafter referred to as an NMOS transistor) to which a current ia from the current source 101 is input. And a current mirror circuit 104 formed of 102 and 103. Further, the laser diode driving circuit 100 includes a current mirror circuit 107 formed by P-channel MOSFETs (hereinafter referred to as PMOS transistors) 105 and 106 using the output current ib of the current mirror circuit 104 as an input current. ing. A laser diode LD is connected between the drain of the PMOS transistor 106 of the current mirror circuit 107 and the negative power supply voltage Vss.

Further, a switch 108 is provided between the drain of the NMOS transistor 103 of the current mirror circuit 104 and the drain of the PMOS transistor 105 of the current mirror circuit 107.
The current ia output from the current source 101 in response to the control signal SCa is turned back by the current mirror circuit 104 and input to the current mirror circuit 107, and becomes the drain current of the PMOS transistor 106 of the current mirror circuit 107. The drain current is supplied as a drive current iLD to the laser diode LD, and the laser diode LD emits light. The magnitude of the optical output of the laser diode LD is determined by the output current ia output from the current source 101 according to the control signal SCa. The switch 108 is controlled by a control signal output from a control circuit (not shown), and controls light emission or extinction of the laser diode LD.

In addition, as a conventional LD drive circuit, optical output is achieved by inserting an LD drive current in series with a transistor that controls the current of the LD drive current, and eliminating the resistor for detecting the change in the LD drive current at the same time as setting the LD drive current. In some cases, the power supply voltage can be lowered at the same time as stabilization (for example, see Patent Document 1).
JP-A-10-270784

However, normally, in order to make the input current and output current of the current mirror circuit the same, the source-gate voltage Vgs of the MOS transistor constituting the current mirror circuit and the source-drain Vds match. Must be.
FIG. 13 is a diagram showing a characteristic example of the drain current id and the drain voltage Vds of the NMOS transistor using the gate voltage Vgs as a parameter.
As shown in FIG. 13, even if the gate voltage Vgs is constant in the saturation region, the drain current id increases as the drain voltage Vds increases. This phenomenon is known as the channel length modulation effect.

  The current mirror circuit 107 in FIG. 12 will be described as an example. The PMOS transistors 105 and 106 constituting the current mirror circuit 107 have sources connected to the positive power supply voltage Vdd and gates connected to the source- The gate-to-gate voltage is the same voltage. However, the drain voltage Vb changes according to the control signal SCa, that is, according to the current ia from the current source 101, as shown in FIG. This is because in the MOS transistor, when the drain current increases, the voltage between the source and the gate also increases, so that the drain voltage Vb of the PMOS transistor 105 decreases, and the laser diode LD also increases when the drive current iLD increases. This is because the voltage VLD on the anode side of the LD also increases.

While the current ia from the current source 101 is small, that is, in the region B in FIG. 14A, the drain voltage Vb of the PMOS transistor 105 is larger than the drain voltage VLD of the PMOS transistor 106, but as the current ia increases, the PMOS transistor 105 The voltage difference between the drain voltage Vb of the PMOS transistor 106 and the drain voltage VLD of the PMOS transistor 106 becomes smaller and reverses at point A.
As shown in FIG. 14B, due to the channel length modulation effect, in the conventional circuit, in the B region where the current ia from the current source 101 is smaller than the current value at the point A, the current iLD supplied to the laser diode LD is When the current ia exceeds the target value and the current ia exceeds the point A and enters the C region, the current iLD becomes smaller than the target value. Further, the current iLD supplied to the laser diode LD also fluctuates due to fluctuations in the power supply voltage. Such a phenomenon due to the channel length modulation effect and the fluctuation of the power supply voltage also occurs in the current mirror circuit 104 in the same manner.

How the currents ia, ib and iLD in FIG. 12 are determined will be described with reference to FIGS. 15 and 16.
FIG. 15 shows a section in which the output current ia from the current source 101 is small, that is, a region B in FIG. The operating point N1 of the NMOS transistor 102 is determined by the current ia from the current source 101. The gate voltage of the NMOS transistor 103 is the same as that of the NMOS transistor 102. However, since the drain voltage Vb of the NMOS transistor 103 is larger than the gate voltage Va, the operating point of the NMOS transistor 103 has moved the gate voltage Va to the right. N2. The current at the operating point N 2 becomes the drain current ib of the NMOS transistor 103.

  The operating point N2 is also an operating point of the PMOS transistor 105. The gate voltage Vb of the PMOS transistor 106 is the same as that of the PMOS transistor 105. However, since the drain voltage VLD of the PMOS transistor 106 is smaller than the gate voltage Vb, the operating point is P2 moved to the left. The current at the operating point P2 becomes the drive current iLD for the laser diode LD. From FIG. 15, it can be seen that the drive current iLD is increased as compared with the current ia from the current source 101.

  Next, FIG. 16 shows a section in which the current ia from the current source 101 is large, that is, the region C in FIG. In FIG. 16, the operating point N1 of the NMOS transistor 102 is determined by the current ia from the current source 101. The gate voltage Va of the NMOS transistor 103 is the same as that of the NMOS transistor 102. However, when the drain voltage Vb of the NMOS transistor 103 is smaller than the gate voltage Va, the operating point of the NMOS transistor 103 moves the gate voltage Va leftward. N2. The current at the operating point N2 is the drain current ib of the NMOS transistor 103. The operating point N2 is also an operating point of the PMOS transistor 105.

  The gate voltage Vb of the PMOS transistor 106 is the same as the gate voltage of the PMOS transistor 105. However, since the drain voltage VLD of the PMOS transistor 106 is larger than the gate voltage Vb, P2 moved to the right becomes the operating point. The current at the operating point P2 becomes the drive current iLD for the laser diode LD. It can be seen from FIG. 16 that the drive current iLD is reduced as compared with the current ia from the current source 101. Thus, under the influence of the channel length modulation effect, there is a problem that the current iLD for driving the laser diode LD deviates from the target current value given by the control signal SCa.

The present invention has been made to solve the above-described problems, and is a difference between a target current value and a current value actually supplied to a laser diode, which are generated due to fluctuations in power supply voltage and channel length modulation effects. by correcting, an object of the present invention to provide a laser diode driving circuits capable of supplying a current close to the target value to the laser diode.

The laser diode driving circuit according to the present invention changes the current value of the current source in accordance with a control signal input from the outside, and supplies the laser diode with a current that is the same as or proportional to the current value. In the laser diode drive circuit that emits light,
Wherein according to the target drive current supplied to the laser diode, generates a reference forward voltage is a forward voltage of the laser diode as a reference, the actual of the forward voltage corresponding to the supplied current to the reference sequence A correction circuit unit that corrects and controls the current supplied to the laser diode so as to be the same as the directional voltage is provided .

According to the laser diode driving circuits of the present invention, even if the driving current of the laser diode is extensively from minute current to the large current, the driving current of the laser diode which has deviated from the target drive current by the channel length modulation effect, corrected By adding a circuit portion, it is possible to drive with an accurate target current. Furthermore, since the channel length modulation effect can be canceled by the correction circuit unit, even if the power supply voltage fluctuates, fluctuations in the laser diode drive current can be suppressed.

    In addition, since the current proportional to the target current is supplied to the pseudo laser diode proportional to the characteristics of the laser diode, and the current inversely proportional to the current is supplied to the laser diode, the target current is accurately supplied to the laser diode. Can be supplied.

  In addition, since the pseudo laser diode can be realized with a simple configuration and the circuit can be simplified, the cost can be reduced along with the miniaturization of the IC chip.

Next, the present invention will be described in detail based on the embodiments shown in the drawings.
First embodiment.
FIG. 1 is a diagram showing a circuit example of a laser diode driving circuit according to the first embodiment of the present invention.
In FIG. 1, a laser diode drive circuit 1 includes a current source 2 in which an output current i1 changes according to an input control signal SC, a laser diode LD, a current iLD supplied to the laser diode LD, and a laser diode LD. The first pseudo-laser diode LD1 and the second pseudo-laser diode LD2 having characteristics substantially similar to or proportional to the characteristics of the anode-side voltage VLD, which is a forward voltage, are provided.

  The laser diode driving circuit 1 includes a first current mirror circuit 3 that supplies current to the first pseudo laser diode LD1 and a second current mirror that supplies current to the second pseudo laser diode LD2. The circuit 4, the third current mirror circuit 5 that supplies current to the laser diode LD, and the output current i 1 from the current source 2 are input, and the first current mirror circuit 3, the second current mirror circuit 4, And a fourth current mirror circuit 6 for supplying input currents i2, i4, i6 corresponding to the third current mirror circuit 5, respectively.

  Further, the laser diode driving circuit 1 includes NMOS transistors N5 and N6, an operational amplifier circuit AMP for controlling the operation of the NMOS transistors N5 and N6, and first and second switches SW1 and SW2. The first switch SW1 controls the light emission and extinction of the laser diode LD, and the second switch SW2 is used to correct the impedance of the first switch SW1 when the first switch SW1 is turned on. The The first and second pseudo laser diodes LD1 and LD2, the first to fourth current mirror circuits 3 to 6, the NMOS transistors N5 and N6, the operational amplifier circuit AMP, and the first and second switches SW1. , SW2 form a correction circuit unit. The NMOS transistors N5 and N6 and the operational amplifier circuit AMP constitute a correction circuit. The NMOS transistor N5 forms a first transistor and the NMOS transistor N6 forms a second transistor.

  The first current mirror circuit 3 is a stacked current mirror circuit, and is formed of PMOS transistors P1 to P4. The second current mirror circuit 4 is formed by PMOS transistors P5 and P6, and the third current mirror circuit 5 is formed by PMOS transistors P7 and P8. The fourth current mirror circuit 6 is formed by NMOS transistors N1 to N4.

  Between the positive power supply voltage Vdd and the negative power supply voltage Vss (for example, ground voltage), the current source 2 and the NMOS transistor N1 are connected in series, and the gate of the NMOS transistor N1 is connected to the drain. Further, the gates of the NMOS transistors N1 are connected to the gates of the NMOS transistors N2 to N4, respectively, and the sources of the NMOS transistors N2 to N4 are connected to the negative power supply voltage Vss.

  In the first current mirror circuit 3, PMOS transistors P1 and P3 are connected in series between the positive power supply voltage Vdd and the drain of the NMOS transistor N2, and the positive power supply voltage Vdd and the first pseudo laser diode LD1 are connected. PMOS transistors P2 and P4 are connected in series with each other. The cathode of the first pseudo laser diode LD1 is connected to the negative power supply voltage Vss. The gates of the PMOS transistors P1 and P2 are connected, and the connection is connected to the drain of the PMOS transistor P2. The gates of the PMOS transistors P3 and P4 are connected, and the connection is connected to the drain of the PMOS transistor P3.

  In the second current mirror circuit 4, the sources of the PMOS transistors P5 and P6 are connected to the positive power supply voltage Vdd, the gates are connected, and the connection is connected to the drain of the PMOS transistor P5. A switch SW2 and an NMOS transistor N3 are connected in series between the drain of the PMOS transistor P5 and the negative power supply voltage Vss, and a second pseudo laser is connected between the drain of the PMOS transistor P6 and the negative power supply voltage Vss. A diode LD2 is connected.

  In the third current mirror circuit 5, the sources of the PMOS transistors P7 and P8 are connected to the positive power supply voltage Vdd, the gates are connected, and the connection is connected to the drain of the PMOS transistor P7. A switch SW1 and an NMOS transistor N4 are connected in series between the drain of the PMOS transistor P7 and the negative power supply voltage Vss, and a laser diode LD is connected between the drain of the PMOS transistor P8 and the negative power supply voltage Vss. Has been.

  In the operational amplifier circuit AMP, the non-inverting input terminal is connected to the connection portion between the drain of the PMOS transistor P4 and the anode of the first pseudo laser diode LD1, and the inverting input terminal is connected to the drain of the PMOS transistor P6 and the second pseudo-laser. The laser diode LD2 is connected to the connection portion with the anode. The output terminal of the operational amplifier circuit AMP is connected to the gates of the NMOS transistors N5 and N6, respectively. The NMOS transistor N5 is connected in parallel with the NMOS transistor N3, and the NMOS transistor N6 is connected in parallel with the NMOS transistor N4.

  Each of the first and second pseudo laser diodes LD1 and LD2 has a configuration as shown in FIGS. 2 to 4, and in FIG. 2, is constituted by a series circuit of a constant voltage power supply circuit 11 and a resistor 12, and FIG. 4 includes an NMOS transistor 13 having a gate and a drain connected, and FIG. 4 includes a series circuit of NMOS transistors 14 and 15 having a gate and a drain connected to each other. In each of the first and second pseudo laser diodes LD1 and LD2, the flowing current and the forward voltage between the anode and the cathode are set to be the same as or proportional to those of the laser diode LD.

  The second current mirror circuit 4 uses a circuit in which the element size of the MOS transistor constituting the circuit is smaller than that of the third current mirror circuit 5. The current consumption is set to 1 / minute. The iLD2-VLD2 characteristic that is the characteristic of the current iLD2 supplied to the second pseudo laser diode LD2 and the anode-side voltage VLD2 that is the forward voltage of the second pseudo laser diode LD2, and the laser diode LD The current ratio between the current iLD and the iLD-VLD characteristic that is the characteristic of the anode-side voltage VLD of the laser diode LD is the current consumption M2i of the second current mirror circuit 4 and the current consumption M3i of the third current mirror circuit 5. It is set to be the same as the ratio. That is, the transistor sizes of the MOS transistors of the second current mirror circuit 4 and the third current mirror circuit 5 are set so that iLD2 / iLD = M2i / M3i.

  The second switch SW2 connected to the second current mirror circuit 4 is always on, and the impedance Z2 of the second switch SW2 connected to the third current mirror circuit 5 is on. The impedance ratio Z2 / Z1 is larger than the impedance Z1 at the time, and the reciprocal of the ratio of the current consumption M2i of the second current mirror circuit 4 and the current consumption M3i of the third current mirror circuit 5, ie, The impedances Z1 and Z2 of the first and second switches SW1 and SW2 are set so that Z2 / Z1 = M3i / M2i.

Since the first current mirror circuit 3 has a configuration in which two stages of current mirror circuits are stacked as described above, the current asymmetry due to the channel length modulation effect can be greatly improved. As the first current mirror circuit 3, in addition to the stack type shown in FIG. 1, a cascode type current mirror circuit in which PMOS transistors as shown in FIG. 5 are cascode connected, or a Wilson type current mirror as shown in FIG. A circuit or the like can also be used.
In the fourth current mirror circuit 6, the current i1 from the current source 2 is supplied to the drain of the NMOS transistor N1, and the current corresponding to the current i1 is output as each drain current of the NMOS transistors N2 to N4. The first to third current mirror circuits 3 to 5 are inputted.

  In such a configuration, the current i1 from the current source 2 according to the control signal SC becomes the drain current of the NMOS transistor N1 of the fourth current mirror circuit 6. The current is turned back by the NMOS transistor N 2 and input to the first current mirror circuit 3, and further supplied to the first pseudo laser diode LD 1 connected to the output terminal of the first current mirror circuit 3. Further, the drain current i1 of the NMOS transistor N1 of the fourth current mirror circuit 6 is turned back by the NMOS transistor N3 and input to the second current mirror circuit 4, and further to the output terminal of the second current mirror circuit 4. It is supplied to the connected second pseudo laser diode LD2.

  The element size of the NMOS transistor N2 is larger than the element size of the NMOS transistor N3 so that the drain current i2 of the NMOS transistor N2 at the same gate voltage is larger than the drain current i4 of the NMOS transistor N3. As a result, the current iLD1 flowing through the first pseudo laser diode LD1 becomes larger than the current iLD2 flowing through the second pseudo laser diode LD2. Since the current-voltage characteristics of the first pseudo laser diode LD1 and the second pseudo laser diode LD2 are the same, the voltage VLD2 of the second pseudo laser diode LD2 is the forward voltage of the first pseudo laser diode LD1. Is smaller than the anode-side voltage VLD1.

  The voltage VLD1 of the first pseudo laser diode LD1 is connected to the non-inverting input terminal of the operational amplifier circuit AMP, and the voltage VLD2 of the second pseudo laser diode LD2 is connected to the inverting input terminal of the operational amplifier circuit AMP. The operational amplifier circuit AMP controls the gate voltage of the NMOS transistor N5 connected to the output terminal so that the voltage VLD2 of the second pseudo laser diode LD2 becomes equal to the voltage VLD1 of the first pseudo laser diode LD1. The input current i4 of the second current mirror circuit 4 is increased to increase the output current i5 of the second current mirror circuit 4.

  Further, since the gate of the NMOS transistor N6 is connected to the output terminal of the operational amplifier circuit AMP, the input current i6 of the third current mirror circuit 5 is increased. The increment of the current i6 is determined by the drain current ratio at the same gate voltage in the NMOS transistor N5 and the NMOS transistor N6. The drain current ratio is the same as the current consumption M2i of the second current mirror circuit 4 and the current consumption M3i of the third current mirror circuit 5, and the current iLD supplied to the laser diode LD is Can be made proportional to the current iLD2 supplied to the pseudo laser diode LD2.

  The current iLD2 supplied to the second pseudo laser diode LD2 is the same as the current iLD1 supplied to the first pseudo laser diode LD1, and the current iLD1 supplied to the first pseudo laser diode LD1 is Therefore, the current iLD supplied to the laser diode LD becomes a current proportional to the current i1 output from the current source 2.

In FIG. 1, the operational amplifier circuit AMP and NMOS transistors N5 and N6 are used to adjust the input currents of the second and third current mirror circuits. However, the operational amplifier circuit AMP and NMOS transistor N5 are adjusted. , N6 may be used to adjust the current supplied to each of the second pseudo laser diode LD2 and the laser diode LD.
A circuit example of the laser diode driving circuit in such a case is shown in FIG. In FIG. 7, the same or similar elements as those in FIG. 1 are denoted by the same reference numerals, and the description thereof is omitted here, and only the differences from FIG.

  7 differs from FIG. 1 in that the voltage VLD1 is input to the inverting input terminal of the operational amplifier circuit AMP of FIG. 1, the voltage VLD2 is input to the non-inverting input terminal of the operational amplifier circuit AMP of FIG. Are connected in parallel to the second pseudo laser diode LD2 and the NMOS transistor N6 is connected in parallel to the laser diode LD, so that the element size of the NMOS transistor N2 is the same as or slightly smaller than the element size of the NMOS transistor N3. Thus, the drain current i2 of the NMOS transistor N2 at the same gate voltage is made smaller than the drain current i4 of the NMOS transistor N3.

  In FIG. 7, since the drain current i2 of the NMOS transistor N2 is made smaller than the drain current i4 of the NMOS transistor N3, the current iLD2 flowing through the second pseudo laser diode LD2 flows through the first pseudo laser diode LD1. It becomes larger than the current iLD1. Therefore, in place of the additional current added to the input terminals of the second current mirror circuit 4 and the third current mirror circuit 5, the extra current is output from the output terminals of the second current mirror circuit 4 and the third current mirror circuit 5. Therefore, the current supplied to the laser diode LD is proportional to the current i1 output from the current source 2.

  As described above, in the laser diode driving circuit according to the first embodiment, the fourth current mirror circuit 6 is configured to supply a current corresponding to the current i1 output from the current source 2 to each of the first to third current mirrors. The first current mirror circuit 3 and the first pseudo laser diode LD1 that are supplied to the circuits 3 to 5, respectively, generate a forward voltage VLD1 that serves as a reference for the laser diode LD corresponding to the current i1, and generate the first voltage VLD1. An actual forward voltage VLD2 of the laser diode LD corresponding to the current i1 is generated by the second current mirror circuit 4 and the second pseudo laser diode LD2, and the forward voltage VLD2 becomes the reference forward voltage VLD1. Thus, the current iLD flowing through the laser diode LD is controlled. From this, it is possible to correct the difference between the target current value and the current value actually supplied to the laser diode LD caused by fluctuations in the power supply voltage and the channel length modulation effect. It can be supplied to the LD.

Second embodiment.
In the first embodiment, the first current mirror circuit 3 with high accuracy is used. However, the first current mirror circuit 3 is eliminated, and the first pseudo laser diode LD1 is connected to the first pseudo laser diode LD1 from the current source 2. The output current i1 may be supplied, and this is the second embodiment of the present invention.
FIG. 8 is a diagram showing a circuit example of a laser diode driving circuit according to the second embodiment of the present invention. In FIG. 8, the same or similar parts as those in FIG. 1 are denoted by the same reference numerals, and the description thereof is omitted here.

  In FIG. 8, a laser diode drive circuit 21 includes a current source 2, a laser diode LD, a first pseudo laser diode LD1 and a second pseudo laser diode LD2, a second current mirror circuit 4, and a third current mirror circuit 4. A current mirror circuit 5, NMOS transistors N3 and N4, an operational amplifier circuit AMP for controlling the operation of the NMOS transistors N3 and N4, and first and second switches SW1 and SW2 are provided. The first and second pseudo laser diodes LD1 and LD2, the second current mirror circuit 4, the third current mirror circuit 5, the NMOS transistors N3 and N4, the operational amplifier circuit AMP, and the first and second Each switch SW1, SW2 forms a correction circuit unit. The NMOS transistors N3 and N4 and the operational amplifier circuit AMP constitute a correction circuit, the NMOS transistor N3 forms a first transistor, and the NMOS transistor N4 forms a second transistor.

Between the positive power supply voltage Vdd and the negative power supply voltage Vss, the current source 2 and the first pseudo laser diode LD1 are connected in series, and the connection between the current source 2 and the anode of the first pseudo laser diode LD1 is connected. The unit is connected to the non-inverting input terminal of the operational amplifier circuit AMP.
In the second current mirror circuit 4, the sources of the PMOS transistors P5 and P6 are connected to the positive power supply voltage Vdd, the gates are connected, and the connection is connected to the drain of the PMOS transistor P5.

  A switch SW2 and an NMOS transistor N3 are connected in series between the drain of the PMOS transistor P5 and the negative power supply voltage Vss, and the gate of the NMOS transistor N3 is connected to the output terminal of the operational amplifier circuit AMP. A second pseudo laser diode LD2 is connected between the drain of the PMOS transistor P6 and the negative power supply voltage Vss, and the connection between the anode of the second pseudo laser diode LD2 and the drain of the PMOS transistor P6 is an operational amplifier circuit. It is connected to the inverting input terminal of AMP.

  In the third current mirror circuit 5, the sources of the PMOS transistors P7 and P8 are connected to the positive power supply voltage Vdd, the gates are connected, and the connection is connected to the drain of the PMOS transistor P7. A switch SW1 and an NMOS transistor N4 are connected in series between the drain of the PMOS transistor P7 and the negative power supply voltage Vss, and the gate of the NMOS transistor N4 is connected to the output terminal of the operational amplifier circuit AMP. A laser diode LD is connected between the drain of the PMOS transistor P8 and the negative power supply voltage Vss.

  In such a configuration, the current i1 output from the current source 2 in response to the control signal SC is supplied to the first pseudo laser diode LD1. The anode voltage VLD1, which is the forward voltage in the first pseudo laser diode LD1, is input to the non-inverting input terminal of the operational amplifier circuit AMP. The anode voltage VLD2 that is the forward voltage of the second pseudo laser diode LD2 is input to the inverting input terminal of the operational amplifier circuit AMP. Thus, the operational amplifier circuit AMP supplies a current to the second pseudo laser diode LD2 such that the anode voltage VLD2 of the second pseudo laser diode LD2 is equal to the anode voltage VLD1 of the first pseudo laser diode LD1. The gate voltage of the NMOS transistor N3 is controlled so as to be supplied.

Since the second current mirror circuit 4 is in the feedback loop of the operational amplifier circuit AMP, the current asymmetry due to the channel length modulation effect generated in the second current mirror circuit 4 is corrected, and the second pseudo laser is corrected. The current iLD2 flowing through the diode LD2 becomes accurate to a current proportional to the current i1 output from the current source 2.
Since the currents flowing through the second current mirror circuit 4 and the third current mirror circuit 5 are made to be in a completely proportional relationship, a current proportional to the second pseudo laser diode LD2 flows through the laser diode LD. . That is, a current proportional to the current i1 output from the current source 2 flows through the laser diode LD. Since the first switch SW1 and the second switch SW2 are the same as those in the first embodiment, description thereof is omitted.

  As described above, the laser diode drive circuit according to the second embodiment can obtain the same effects as those of the first embodiment, and flows to the laser diode LD in the first embodiment. Since the current could only be added to or extracted from the current, the current supplied to the first pseudo laser diode LD1 and the second pseudo laser diode LD2 had a difference in the initial setting. Both addition and extraction can be performed on the current flowing through the laser diode LD, and the high-precision current mirror circuit and the fourth current mirror circuit 6 composed of the NMOS transistor N1 and the NMOS transistor N2 are not required. The current asymmetry due to the channel length modulation effect generated in current mirror circuits It can be.

Third embodiment.
In the second embodiment, the operational amplifier circuit AMP is used. However, the first current mirror circuit 3 is eliminated without using the operational amplifier circuit AMP, and the first pseudo laser diode LD1 is connected to the first pseudo laser diode LD1 from the current source 2. The output current i1 may be supplied, and this is the third embodiment of the present invention.
FIG. 9 is a diagram showing a circuit example of a laser diode driving circuit according to the third embodiment of the present invention. In FIG. 9, the same or similar elements as those in FIG. 1 are denoted by the same reference numerals, and the description thereof is omitted here.

  In FIG. 9, a laser diode drive circuit 31 includes a current source 2, a laser diode LD, a second current mirror circuit 4, a third current mirror circuit 5, and a fourth current composed of NMOS transistors N1 and N2. A mirror circuit 32, NMOS transistors N3 and N4, and first and second switches SW1 and SW2 are provided. The second current mirror circuit 4, the third current mirror circuit 5, the fourth current mirror circuit 32, the NMOS transistors N3 and N4, and the first and second switches SW1 and SW2 form a correction circuit unit. . The NMOS transistors N3 and N4 form a current supply circuit, the NMOS transistor N3 forms a first MOS transistor, and the NMOS transistor N4 forms a second MOS transistor.

Between the positive power supply voltage Vdd and the negative power supply voltage Vss, the current source 2 and the NMOS transistor N1 are connected in series, and the connection portion between the current source 2 and the NMOS transistor N1 is connected to each of the NMOS transistors N3 and N4. Each is connected to a gate.
In the second current mirror circuit 4, the sources of the PMOS transistors P5 and P6 are connected to the positive power supply voltage Vdd, the gates are connected, and the connection is connected to the drain of the PMOS transistor P5. A switch SW2 and an NMOS transistor N3 are connected in series between the drain of the PMOS transistor P5 and the negative power supply voltage Vss.

In the third current mirror circuit 5, the sources of the PMOS transistors P7 and P8 are connected to the positive power supply voltage Vdd, the gates are connected, and the connection is connected to the drain of the PMOS transistor P7. A switch SW1 and an NMOS transistor N4 are connected in series between the drain of the PMOS transistor P7 and the negative power supply voltage Vss.
In the fourth current mirror circuit 32, the sources of the NMOS transistors N1 and N2 are connected to the negative power supply voltage Vss, the gates are connected, and the connection is connected to the drain of the NMOS transistor N2. The NMOS transistor N1 has the drain supplied with the current i1 from the current source 2 to form the first pseudo laser diode LD1, and the NMOS transistor N2 has the drain supplied with the current i5 from the PMOS transistor P6 to receive the second pseudo laser diode LD1. A laser diode LD2 is formed.

  In such a configuration, the current i1 output from the current source 2 in response to the control signal SC becomes the drain current of the NMOS transistor N1 forming the first pseudo laser diode LD1. The drain voltage of the NMOS transistor N1 becomes the anode voltage VLD1, which is the forward voltage of the first pseudo laser diode LD1, and the voltage VLD1 is the gate of the NMOS transistor N3 connected to the input terminal of the second current mirror circuit 4. Therefore, a feedback loop is formed, and the drain current i5 of the NMOS transistor N2 becomes equal to the current i1 output from the current source 2. As a result, the drain voltage VLD1 of the NMOS transistor N1 becomes the gate voltage of the NMOS transistor N3 such that the output current i5 of the PMOS transistor P6 of the second current mirror circuit 4 substantially matches the current i1.

Furthermore, since the drain voltage VLD1 of the NMOS transistor N1 is also input to the gate of the NMOS transistor N4 connected to the input terminal of the third current mirror circuit 5, the drain current i6 of the NMOS transistor N4 is The current is proportional to the drain current i4 of N3.
Since the second current mirror circuit 4 and the third current mirror circuit 5 have the same circuit configuration, the drain current i5 of the PMOS transistor P6 and the drain current iLD of the PMOS transistor P8 are proportional to each other. That is, since the drain current iLD of the PMOS transistor P8 is a current flowing through the laser diode LD, a current proportional to the current i1 output from the current source 2 flows through the laser diode LD.

  Since the drain voltage VLD1 of the NMOS transistor N1 and the drain voltage VLD2 of the NMOS transistor N2 do not match, the fourth current mirror circuit 32 may have a minute error due to the channel length modulation effect. For this reason, when better characteristics are required, the gate channel length of the NMOS transistors N1 and N2 is increased, or the fourth current mirror circuit 32 is connected to the NMOS transistor as shown in FIG. A highly accurate current mirror circuit such as a mirror circuit or a Wilson current mirror circuit as shown in FIG. 11 may be used.

  In the case of FIG. 10, the series circuit of the NMOS transistors N11 and N12 forms the first pseudo laser diode LD1, and the series circuit of the NMOS transistors N21 and N22 forms the second pseudo laser diode LD2. In the case of FIG. 11, the NMOS transistor N13 forms the first pseudo laser diode LD1, and the series circuit of the NMOS transistors N23 and N24 forms the second pseudo laser diode LD2.

  As described above, the laser diode drive circuit according to the third embodiment can obtain the same effects as those of the second embodiment, and many elements that are necessary in the second embodiment. The operational amplifier circuit AMP that requires a relatively large area on the IC chip can be eliminated, and the area of the IC chip can be greatly reduced.

  The operations performed by the PMOS transistors used in the first to third embodiments are realized by NMOS transistors, and the operations performed by the NMOS transistors used in the first to third embodiments. May be realized by a PMOS transistor.

It is the figure which showed the circuit example of the laser diode drive circuit in the 1st Embodiment of this invention. It is the figure which showed the example of a structure of each 1st and 2nd pseudo laser diode LD1, LD2. It is the figure which showed the other structural example of each 1st and 2nd pseudo | simulation laser diode LD1, LD2. It is the figure which showed the other structural example of each 1st and 2nd pseudo | simulation laser diode LD1, LD2. FIG. 6 is a diagram showing another circuit example of the first current mirror circuit 3; FIG. 6 is a diagram showing another circuit example of the first current mirror circuit 3; It is the figure which showed the other circuit example of the laser diode drive circuit in the 1st Embodiment of this invention. It is the figure which showed the circuit example of the laser diode drive circuit in the 2nd Embodiment of this invention. It is the figure which showed the circuit example of the laser diode drive circuit in the 3rd Embodiment of this invention. FIG. 10 is a diagram showing another circuit example of the fourth current mirror circuit 32 in FIG. 9. FIG. 10 is a diagram showing another circuit example of the fourth current mirror circuit 32 in FIG. 9. It is the figure which showed the circuit example of the conventional laser diode drive circuit. It is the figure which showed the example of a characteristic of the drain current id of the NMOS transistor, and the drain voltage Vds. It is the figure which showed the example of a relationship with the voltage of each part of FIG. 12, and the electric current iLD which flows into the laser diode LD with respect to the change of the electric current ia. It is the figure which showed the example of a relationship of the voltage of each part of FIG. 12, and the electric current in the B area | region of FIG. It is the figure which showed the example of a relationship of the voltage of each part of FIG. 12, and the electric current in the C area | region of FIG.

Explanation of symbols

1, 21, 31 Laser diode driving circuit 2 Current source 3 First current mirror circuit 4 Second current mirror circuit 5 Third current mirror circuit 6, 32 Fourth current mirror circuit SW1 First switch SW2 Second Switch LD laser diode LD1 first pseudo laser diode LD2 second pseudo laser diode AMP operational amplifier circuit N5, N6 NMOS transistor

Claims (1)

In a laser diode driving circuit that changes the current value of a current source according to a control signal input from the outside, supplies the laser diode with a current that is the same as or proportional to the current value, and emits the laser diode.
Wherein according to the target drive current supplied to the laser diode, generates a reference forward voltage is a forward voltage of the laser diode as a reference, the actual of the forward voltage corresponding to the supplied current to the reference sequence A laser diode drive circuit comprising: a correction circuit unit that corrects and controls a current supplied to the laser diode so as to be equal to a directional voltage.

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