JP4105295B2 - Pattern defect detection method and pattern defect detection apparatus - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a pattern defect detection method and a pattern defect detection apparatus for performing defect detection by comparing a pattern such as a printed wiring board, an IC mask pattern, and a lead frame with a master pattern for each area of a predetermined size.
[0002]
[Prior art]
FIG. 18 is a diagram for explaining an outline of processing for pattern defect inspection by a conventional comparison method.
[0003]
Conventionally, a defect inspection method called a comparison method is known as a method for inspecting a pattern defect such as a printed wiring board. In this method, an object pattern that is a pattern to be inspected and a master pattern that is a reference pattern are overlaid and compared. At that time, these object patterns and master patterns are given as multi-value image data with gradation by first A / D converting image data obtained by an image sensor such as a CCD. Then, after binarizing each of the object pattern and master pattern as such multi-valued image data with a predetermined threshold value to obtain binary image data, they are superimposed, and a portion where both images are different from each other is defective. It was detected as D.
[0004]
[Problems to be solved by the invention]
By the way, when binarizing a multi-valued image as shown in FIG. 18, the quantization error of one pixel or less is present at the edge of the pattern in the binary image data as shown in FIG. Q may occur. However, since these are not inherently defects, it is not desirable to detect them as defects. Therefore, conventionally, the quantization error Q is not determined as a defect by setting the window to a size of one pixel or more such as 2 × 2 pixels or 3 × 3 pixels as the minimum unit of defect detection.
[0005]
However, this method has a problem that a defect of about one pixel cannot be detected.
[0006]
The present invention is intended to overcome the above-described problems in the prior art, and provides a pattern defect detection method and a pattern defect detection apparatus capable of performing highly accurate defect detection without detecting a quantization error as a defect. The purpose is to provide.
[0007]
[Means for Solving the Problems]
  In order to achieve the above object, a method according to claim 1 of the present invention is a pattern defect detection method for performing defect detection by comparing a two-dimensional object pattern with a two-dimensional master pattern for each area of a predetermined size. There,(a)Two-dimensionally across the inspection area of the object pattern and the extended area where the number of pixels is expanded around the area of the master pattern that should be positioned relative to the inspection areaSmaller than the size of one pixelSet multiple master zones that are offset by a certain amount by unit amountAnd a process of (b)Multi-level image signal for multiple master areas and multi-level image signal for inspection areasBased on the inspection area for all pixels of multiple master areasObtaining a gradation difference absolute value that is an absolute value of the gradation difference of the multi-value image signal for each corresponding pixel of(c) Compare the absolute value of the gradation difference with a predetermined threshold value to determine whether there is a defect in the inspection area.Determining.
[0008]
  According to a second aspect of the present invention, there is provided a pattern defect detection apparatus for performing defect detection by comparing a two-dimensional object pattern with a two-dimensional master pattern for each area of a predetermined size. Means for inputting a multi-value image signal; means for storing a multi-value image signal of a master pattern; a multi-value image signal in an inspection area of an object pattern; and an area of a master pattern to be positioned corresponding to the inspection area. Two-dimensionally over the extended area around the required number of pixels as the centerSmaller than the size of one pixelExtracting means for extracting multi-value image signals in a plurality of master areas, each of which is displaced by a predetermined amount by a unit amount, multi-value image signals in a plurality of master areas, and multi-value image signals in an inspection area inputWhenInspecting means, wherein the inspecting means comprises a plurality of master areas.For all pixels,Find the absolute value of the gradation difference, which is the absolute value of the gradation difference of the multilevel image signal, for each corresponding pixel in the inspection area.Calculated by the tone difference calculating means and the tone difference calculating means.Compare the absolute value of the gradation difference with a predetermined threshold,A result judging means for judging the presence or absence of defects in the inspection area.It is characterized by being.
[0009]
  An apparatus according to claim 3 of the present invention is the pattern defect detection apparatus according to claim 2., ExtractionThe output means interpolates the multi-value image signal of the master patternSmaller than the size of one pixelA multi-value image signal of a plurality of master areas that are displaced by a predetermined amount by unit amount is obtained.
[0010]
According to a fourth aspect of the present invention, there is provided the pattern defect detecting apparatus according to the third aspect, wherein the interpolation is performed for each direction of a two-dimensional orthogonal axis.
[0011]
  An apparatus according to claim 5 of the present invention is the pattern defect detection apparatus according to any one of claims 2 to 4,Result judgmentMeansObtained by means of gradation difference calculation meansTonal difference absolute valueWithin each of the multiple master areasMaximum valueSeekingMaximum difference holding means for holding together,Held in the maximum difference holding meansMinimum value selection means for selecting the minimum value of the maximum values;Compare the threshold with the minimum value selected by the minimum value selection means,If the minimum value is less than the thresholdAbout inspection areaJudge no defects,The minimum value isIf it is above the thresholdAbout inspection areaAnd a determination means for determining whether there is a defect.
[0012]
  An apparatus according to claim 6 of the present invention is the pattern defect detection apparatus according to any one of claims 2 to 4,Result judgmentMeansCompare all gradation difference absolute values and thresholds in one master area,When the absolute value of gradation difference is less than the threshold value1'sThe master area is determined to match the pattern,Of all the gradation difference absolute valuesWhen at least one absolute value of gradation difference is equal to or greater than the threshold value1'sA match determination means for determining that the master area is a pattern mismatch, a comparison result holding means for holding a comparison result by the match determination means for each of the plurality of master areas,WithInspection area when all comparison results held in the comparison result holding means do not match the patternMissing aboutIf there is a defect, and at least one comparison result is a pattern match, the inspection areaMissing aboutJudgment of no fallUmbrellaIt is characterized by that.
[0013]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings.
[0014]
      <1. Principle of Embodiment>
  FIG. 1 is a diagram conceptually showing a “shaking method” in the pattern defect detection method according to the embodiment of the present invention. In this embodiment, the object pattern inspection area P0 is centered on the area M0 of the master pattern that corresponds to the position, and the area (area) is expanded to the area around the required number of pixels. Set a plurality of master areas that are displaced by a predetermined amount by / 5 (0.2) pixels.(Defect detection is performed by comparing the M11 to MBB suffixes in hexadecimal) and the inspection area P0. In this case, the setting range of the extended area is a range that can absorb the displacement error due to the displacement or distortion of the inspection object. In FIG. 1, the area M0 (= master area M66) is centered on the top, bottom, left, and right. A case where the position is shifted by one pixel is illustrated.
[0015]
However, the multi-value image signal of the base master pattern is a pixel unit. On the other hand, this embodiment is different in that a multi-value image signal that is displaced (shaken) in units of less than one pixel by interpolation is generated.
[0016]
FIG. 2 is a diagram for explaining the concept of a multi-value image signal displaced in units of less than one pixel in this embodiment. As shown in FIG. 2, in this embodiment, generation of an image of a master pattern in a state in which 0.2 pixels are displaced will be described as an example.
[0017]
In this embodiment, in order to obtain a deviation image signal in units of less than one pixel, such a deviation image signal is obtained by using linear interpolation based on a gradation signal of an adjacent pixel.
[0018]
Hereinafter, the image signal (gradation value) at the pixel position i of the master pattern as a base is represented as Gi, and the image signal (gradation value) corresponding to the pixel i displaced in units of less than one pixel is represented as Hi. At this time, the formula for obtaining Hi is as follows.
[0019]
Hi = INT {Gi-1 · (1-x) + Gi · x} (1)
However, x = 0.2, 0.4, 0.6, 0.8
For example, when the gradation values of adjacent pixels are Gi-1 = 100 and Gi = 60 and x = 0.2, Hi = 92 from the above equation.
[0020]
In this embodiment, an image signal of a master pattern in which x = 0 or 1 is required to perform ± 1 pixel shaking, but for these, an image signal at a pixel position i or a pixel position adjacent thereto is used. Interpolation is not necessary because it can be used as it is. Further, equation (1) is an equation for one-dimensional deviation as the pixel position, but this is performed two-dimensionally. That is, an interpolated image is generated using equation (1) for each of the main scanning direction and the sub-scanning direction.
[0021]
In this way, by setting a plurality of master areas M11 to MBB displaced in units of less than one pixel, even if the inspection object is displaced by less than one pixel, the master corresponding to the inspection area P0 in position. The pattern will be present in any one of the master areas M11 to MBB. In the example of FIG. 1A, it is assumed that the object pattern P corresponding to the inspection area is shifted by 0.8 pixel in the upward direction and 0.8 pixel in the left direction with respect to the reference position. The master pattern that exactly matches the area P0 is not the master area M66 that should originally match at this position, but the master pattern at a position shifted by 0.8 pixels downward from the master area M66 and 0.8 pixels rightward. Zone MAA.
[0022]
After setting such a master area group, the image signal in the inspection area P0 shown in FIG. 1A and the image symbols in the master areas M11 to MBB shown in FIG. Compare each. That is, defect inspection windows W and W ′ having a predetermined pixel size, in this embodiment, one pixel size are set in each area, and the inspection windows W and W ′ are positioned in correspondence with each other over the entire area. Scanning is performed to obtain the absolute value of the gradation difference of each pixel in the defect inspection windows W and W ′ of the master pattern and the object pattern.
[0023]
FIG. 3 is a diagram showing an example of comparison by the “shaking method” using a displacement image signal in units of less than one pixel. In FIGS. 3A to 3D, the horizontal axis is the pixel position. 3 (a) and (c), the vertical axis represents the gradation of the image signal, and in FIGS. 3 (b) and (d), the vertical axis represents the gradation of the image signal in FIGS. 3 (a) and (c). The absolute value of the difference is used. However, although the pixel positions are actually distributed two-dimensionally, they are represented here one-dimensionally for the sake of simplicity.
[0024]
FIG. 3A shows a case where a positional deviation of less than one pixel occurs between the object pattern P and the master pattern M, or more precisely when a positional deviation of about 0.4 pixels occurs. Shown together. Here, since the defect inspection windows W and W ′ having the size of one pixel are used, the floors of both patterns are moved while moving the windows W and W ′ along the horizontal axis representing the pixel position in FIG. FIG. 3B shows the absolute value of the difference. As can be seen from FIG. 3B, it can be seen that there are many gradation differences between the two patterns even though there is no defect in the object pattern. As is clear from FIG. 3A, even if both patterns are relatively displaced in units of one pixel with respect to such an object pattern P and master pattern M, in that case, FIG. Since the state of (a) is the state in which both patterns are the same, the gradation difference is not reduced as compared with FIG.
[0025]
For this reason, in this embodiment, the problem is overcome as shown below by performing the swing of less than one pixel by interpolation.
[0026]
FIG. 3C shows a state where the master pattern is overlapped when interpolation is performed by shifting the master pattern to the right in the figure by about 0.4 pixels with respect to the positional relationship of both patterns in FIG. Show. As can be seen from FIG. 3 (d) showing the absolute value of the difference between the gradations of both patterns in FIG. 3 (c), the difference in the gradation of both patterns is reduced compared to FIG. 3 (b). It can be seen that the two patterns match in the positional relationship between the object pattern P and the master pattern M.
[0027]
In this embodiment, the gradation difference, which is the absolute value of the gradation difference between each of the master areas M11 to MBB and the inspection area P0, in which the width of the unit of less than one pixel is shaken as described above. Absolute values are obtained for all pixels in all positional relationships (master areas M11 to MBB), and are equal to or greater than a predetermined threshold value (hereinafter referred to as “determination threshold value”) in all master areas M11 to MBB. If the absolute value of gradation difference is included, it is determined that there is a defect in the inspection area P0, and if all absolute values of gradation difference are less than the determination threshold value in one or more master areas M11 to MBB, the inspection area. It is determined that there is no defect at P0.
[0028]
However, as a specific method of this determination, in each of the first and second embodiments, for each of the master areas M11 to MBB, the maximum gradation difference absolute value (hereinafter, “ If the minimum value among the maximum gradation differences for all the master areas M11 to MBB is smaller than the determination threshold value, it is determined that there is no defect, and if it is equal to or greater than the determination threshold value. It is determined that there is a defect.
[0029]
That the minimum maximum gradation difference is equal to or greater than the determination threshold includes the absolute value of the gradation difference that is equal to or greater than the determination threshold in all master areas, and the minimum maximum gradation difference is determined. Being less than a value means that all the gradation difference absolute values are less than the determination threshold in at least one master area.
[0030]
In the third and fourth embodiments, the gradation difference absolute value is compared with the determination threshold value for all the pixels in each of the master areas M11 to MBB. If at least one pixel is equal to or greater than the judgment threshold value, the pattern mismatch result is held in that area. If all the master areas M11 to MBB do not match, an inspection is performed. The area P0 is determined to be defective, and if there is a pattern match to at least one of the master areas M11 to MBB, the inspection area P0 is determined to be free of defects.
[0031]
According to the method of this embodiment described above, since the comparison inspection is performed based on the multi-value image signal of the object pattern and the master pattern, a quantization error does not occur and even a small defect of one pixel unit is detected. Thus, highly accurate defect detection can be performed.
[0032]
Hereinafter, a pattern defect detection apparatus and a pattern defect detection using the pattern defect detection apparatus according to some embodiments using such a method will be described.
[0033]
<2. First Embodiment>
<< 2-1. Device configuration >>
Hereinafter, a pattern defect inspection apparatus having a circuit configuration configured to perform pattern defect detection corresponding to the example of FIG. 1 will be described.
[0034]
FIG. 4 is a diagram for explaining inspection areas in the object pattern and the master pattern according to the first embodiment. In this detection apparatus, as shown in FIG. 4, inspection areas A11, A12... And A′11, A′12... Having a size of 508 × 508 pixels are set in the object pattern and the master pattern. It is configured to perform defect detection every time. Each inspection area corresponds to an inspection area P0 in the object pattern and an area M0 (master area M66) in the master pattern.
[0035]
FIG. 5 shows a schematic configuration diagram of the pattern defect detection apparatus. As shown in the figure, this apparatus has an XY table 5 that can hold an inspection object 4 such as a printed wiring board with positioning accuracy within a predetermined range, and the X direction (main scanning direction) of the XY table 5. ) Is driven by the X direction drive unit including the motor 6, and the drive in the Y direction (sub-scanning direction) is performed by the Y direction drive unit including the motor 7.
[0036]
Above the XY table 5, eight CCD line sensors 8 are installed at predetermined intervals on the X direction line. (However, in FIG. 5, only one unit is shown for convenience, and the others are not shown.) These CCD line sensors 8 each have 2048 light receiving elements arranged in a line on the X direction line. Is used. The image of the printed wiring board 4 by these eight CCD line sensors 8 is read by moving the XY table 5 in the Y direction by the motor 7 while scanning in the X direction by the CCD line sensor 8. Scanning is performed in a band shape with a scan width a, and scanning on the forward path side is performed. When the forward scanning is finished, the XY table 5 is moved by the motor 6 in the X direction by a width slightly smaller than the scan width a so that the inspection areas overlap, and then the XY table 5 is moved to-(minus). ) Move in the Y direction to perform return side scanning. As a result, the entire area of the printed wiring board 4 is scanned and an image is read. FIG. 4A shows an object pattern P obtained by taking the image data on the forward path side by one CCD line sensor 8.
[0037]
The analog image signal read by the CCD line sensor 8 is amplified by the buffer amplifier 9 and then converted into a digital image signal by the A / D converter 10.
[0038]
A switching circuit 13 is connected to the output terminal side of the A / D converter 10, and this switching circuit 13 is switched to the contact 13a side when the master pattern is input and to the contact 13b side when the object pattern is input. .
[0039]
That is, when the master pattern is input, in other words, when the printed wiring board 4 serving as the inspection reference is arranged on the XY table 5 and the image is read by the CCD line sensor 8, the A / D converter 10 Are stored in the memory 15 through the contact points 13a. On the other hand, when the object pattern is input, in other words, when the printed wiring board 4 to be inspected is placed on the XY table 5 and the image is read by the CCD line sensor 8, the A / D conversion unit 10 The multi-value image signal output in time series is input to one input terminal of the defect inspection unit 16 through the contact 13b.
[0040]
In the defect inspection section 16 (details will be described later), defect inspection processing is performed based on the image signal, that is, object data, and master data that is called from the memory 15 in time. The defect inspection unit 16 includes a delay unit 16a and a comparison unit 16b.
[0041]
Further, the pattern defect detection apparatus is provided with a bus line BL, and the bus line BL includes motors 6 and 7, an A / D conversion unit 10, a switching circuit 13 and a comparison unit 16b in the defect inspection unit 16, The CPU 17, the monitor 18, and the operation unit 19 are electrically connected.
[0042]
The CPU 17 controls the motors 6 and 7, the A / D conversion unit 10, the switching circuit 13 and the comparison unit 16 b in the defect inspection unit 16 while synchronizing them.
[0043]
The monitor 18 displays a setting input by the operator and a defect inspection result.
[0044]
The operation unit 19 is input means such as a keyboard and a mouse for the operator who has confirmed the display on the monitor 18 to perform various settings and input instructions.
[0045]
FIG. 6 is a diagram showing a schematic circuit configuration of the comparison unit 16b of the defect inspection unit 16 of the pattern defect inspection apparatus. Multi-valued image data (object data OD) of the inspection area P0 in the object pattern obtained by scanning the inspection object is input to the defect inspection unit 16 in time series. At the same time, the multi-value image data (master data MDa) of the area M0 in the master pattern called from the memory 15 is input in time series in synchronization with the input of the object data OD.
[0046]
The input object data OD is input to the comparison detection blocks B11 to B33. The comparison detection blocks B11, B21, B31, B12, B22, B32, B13, B23, B33 are respectively master areas M11, M16, M1B, which are shifted from each other by an integer number of pixels in the master areas M11 to MBB in FIG. M61, M66, M6B, MB1, MB6, and MBB are provided.
[0047]
On the other hand, the master data MDa input to the defect inspection unit 16 is delayed by one line by the shift registers SR1 and SR2 in the delay unit 16a and shifted by one line for each horizontal stage of the comparison detection blocks B11 to B33. Are respectively inputted as master data MDa, MDb, MDc and delayed by one pixel for each vertical stage by a delay circuit (not shown) inserted for each vertical stage. As a result, the master data given to each comparison detection block Bij (i = 1 to 3, j = 1 to 3) are all shifted by one pixel in two dimensions.
[0048]
FIG. 7 is a diagram showing a specific circuit configuration of the comparison detection block Bij (i = 1 to 3, j = 1 to 3). Since each comparison detection block Bij has the same configuration, only the circuit of one block is shown here.
[0049]
The comparison detection block Bij is provided with an image interpolation unit Ca and a detailed comparison block Cij (i = 1 to 5, j = 1 to 5).
[0050]
For the input master data MD, only x = 0, 0.2, 0.4, 0.6, 0.8 pixels in the main scanning direction and the sub-scanning direction according to the expression (1) in the image interpolation unit Ca. A total of 25 types of displaced interpolated image signals are generated and transmitted to the detailed comparison block Cij. Of these, the image shifted by 0 pixels in the main scanning and sub-scanning directions outputs the input master data MD as it is.
[0051]
FIG. 8 is a diagram showing a specific circuit configuration of the detailed comparison block Cij.
[0052]
When the object data OD and the master data are input to the detailed comparison block Cij as MD, the gradation difference calculation circuit Da calculates the absolute value of the difference between the gradations and transmits it to the selection output circuit Db.
[0053]
In the selection output circuit Db, the maximum value of the absolute value of the gradation difference stored in the maximum gradation difference holding circuit Dc is read in advance before the absolute value of the gradation difference described later is input. A comparison is made. Only those greater than a predetermined value are output.
[0054]
The maximum gradation difference holding circuit Dc sequentially holds the values output from the selection output circuit Db as maximum values, and is the maximum absolute value of the gradation difference in the detailed comparison block Cij finally obtained. The maximum gradation difference is output.
[0055]
In this way, the maximum gradation difference output by each detailed comparison block Cij shown in FIG. 7 is collected in the minimum difference selection circuit Cb, and the minimum difference selection circuit Cb is the minimum maximum gradation difference candidate which is the minimum value of them. Is output.
[0056]
In this way, the minimum and maximum gradation difference candidates output from each comparison detection block Bij shown in FIG. 6 are collected in the minimum difference determination circuit Ba, and the minimum value which is the minimum value among these minimum and maximum gradation difference candidates. The maximum gradation difference is obtained and further transmitted to the defect determination circuit Bb.
[0057]
Then, the defect determination circuit Bb compares the minimum maximum gradation difference with the determination threshold value. If the defect determination circuit Bb is smaller than the determination threshold value, it is determined that there is no defect in the inspection area P0. It is determined that there is a defect, and one of the results is output as an inspection result signal.
[0058]
<< 2-2. Processing procedure >>
Next, the procedure of defect detection processing by the pattern defect detection apparatus described above will be described with reference to FIG.
[0059]
First, capturing of an image to be a master pattern is started (step S1). Thereafter, an image is read by the CCD line sensor 8, and the obtained analog image signal is converted into a digital image signal by the A / D converter 10.
[0060]
Next, it is determined whether or not it is the master pattern input mode (step S2). If it is the master pattern input mode, the process proceeds to step S3, and the inputted master data is stored in the memory 15 (step S3). Then, a comparison inspection is performed when the object pattern input is completed (step S4).
[0061]
FIG. 10 is a flowchart for explaining in detail the comparison inspection processing procedure in step S4 of FIG. Hereinafter, the process of step S4 will be described in more detail with reference to FIG.
[0062]
First, the image is divided into blocks of a predetermined size (FIG. 10: Step S41).
[0063]
Next, it is determined whether or not the following processing has been completed for all the blocks (FIG. 12: step S42). If completed, the comparison inspection processing in step S4 is terminated, and if the following processing has not been completed. Proceed to step S43.
[0064]
  Next, the object data in the inspection area P0 of the object pattern corresponding to the specified block, and the master data that anticipates the deviation amountTheCut out and read (FIG. 10: Step S43).
[0065]
Next, the shaking process is performed, and the inspection (comparison) is executed for all the positional relationships shown in FIG. 1 (FIG. 10: step S44).
[0066]
FIG. 11 is a flowchart for explaining in detail the shaking process in step S44 of FIG.
[0067]
First, master data of the master areas M11 to MBB shifted by interpolation is obtained (FIG. 11: Step S441).
[0068]
In the first embodiment, interpolation is performed on the master pattern. FIG. 12 is a diagram for explaining how defect detection errors occur when interpolation is performed on an object pattern.
[0069]
Consider a case where a defect inspection of an object pattern having a defect d0 as shown in FIG. 12B is performed on a master pattern as shown in FIG. That is, the object pattern in the inspection object often has a minute defect of about one pixel. FIG. 12C shows such an object pattern that is displaced in units of less than one pixel by interpolation as described above. FIG. 12C shows an object pattern in which 0.2, 0.6, and 0.8 images are displaced in order from the left. As shown in FIG. 12B, since the defect d0 is larger than the determination threshold in FIG. 12B, an inspection result with a defect should be obtained. However, in each interpolation image of FIG. As a result, since none of the defects d1, d2, and d3 exceeds the determination threshold value, it is not recognized as a defect, and the inspection result becomes “no defect”.
[0070]
In this way, if the object data is interpolated and displaced, the possibility of overlooking a defect of about one pixel increases. On the other hand, since there are few patterns that change in units of one pixel in the master pattern, it is unlikely that the above-described defect is overlooked if interpolation is performed on the master pattern. For this reason, the apparatus according to the first embodiment obtains an offset image by interpolation with respect to the master pattern. As a result, it is possible to suppress the occurrence of the defect oversight as described above and perform defect detection with higher accuracy.
[0071]
Next, it is determined whether or not the inspection has been completed for the master data of all the master areas M11 to MBB (FIG. 11: step S442). If the inspection has been completed, the maximum gradation difference obtained from all the inspection results is determined. The minimum maximum gradation difference, which is the minimum value among them, is obtained (FIG. 11: Step S443), and if not completed, the master data of the next master area M11 to MBB and the object data of the inspection area P0 are compared. (FIG. 11: Step S444).
[0072]
Here, the comparison in step S444 is to calculate the absolute value of the gradation difference for each pixel, and the maximum gradation difference among them is stored (FIG. 11: step S447).
[0073]
Returning to FIG. 10, next, it is determined whether or not the minimum maximum gradation difference obtained in step S443 (FIG. 11) is equal to or larger than the determination threshold value (FIG. 10: step S45). The inspection result of the block thus determined is “defective” (FIG. 10: step S46), and if NO, the inspection result is “defective” (FIG. 10: step S47).
[0074]
When the above steps are performed for all the blocks, the process of step S4 ends.
[0075]
Returning to FIG. 9, next, it is determined whether the inspection result is “defect” or “no defect” (step S5), and the inspection result is determined to be “no defect” (no defect in all blocks). In step S1, the process proceeds to step S6 when it is determined that “there is a defect” (there is a defect in any block).
[0076]
Next, an image of the defective part is displayed on the monitor 18 according to the inspection result, and the operator confirms it (step S6). Then, the operator checks whether or not it is a defect and takes measures.
[0077]
Next, it is determined whether or not the inspection has been completed for all the inspected objects (object patterns) (step S7). If not completed, the process returns to step S1, and if completed, the defect inspection is terminated.
[0078]
As described above, according to the first embodiment, defect detection is performed by comparing the multi-value image signals of the object pattern and the master pattern, so there is no need to binarize the image signal. Therefore, since the quantization error is not included, it is possible to detect a defect of about one pixel without detecting the quantization error as a defect, so that highly accurate defect detection can be performed. Further, since the defect is detected by the “shaking method”, it is possible to detect the defect with high accuracy without performing accurate alignment of the inspection object.
[0079]
In addition, it is possible to interpolate the multi-valued image data of the master pattern and perform the “swing method” with a width smaller than the size of one pixel, so that more accurate defect detection can be performed without performing accurate alignment. It can be performed.
[0080]
In addition, since inspection is performed using a master pattern that has been interpolated in each direction of the two-dimensional orthogonal axis, even if there is a two-dimensional misalignment, defects can be reliably detected without accurate alignment. can do.
[0081]
Further, since interpolation is performed on the master pattern, it is possible to detect defects with high accuracy while suppressing false detection even when a defect of about one pixel occurs in the object pattern as compared with the case of interpolating the object pattern. it can.
[0082]
Further, in order to maintain the maximum gradation difference in each of the master areas M11 to MBB, the inspection accuracy can be easily changed by changing the setting of the determination threshold value. it can.
[0083]
<3. Second Embodiment>
The pattern defect inspection apparatus according to the first embodiment uses a window having a size of one pixel. The pattern defect inspection apparatus according to the second embodiment uses a window having 2 × 2 pixels. . Therefore, in the apparatus according to the second embodiment, the configurations of the detailed comparison blocks Cij of the comparison detection blocks Bij of the comparison unit 16b in the defect inspection unit 16 are different. Further, in the delay unit 16a of the defect inspection unit 16 in FIG. 5, the object data OD is directly used as the object data OD1, and is delayed by one line by a delay circuit (not shown) and input to the comparison unit 16b as object data OD2. It is the composition to do. Other configurations are the same as those of the apparatus according to the first embodiment.
[0084]
FIG. 13 is a diagram showing a specific circuit configuration of the detailed comparison block Cij in the second embodiment. Hereinafter, pattern defect detection by the apparatus according to the second embodiment will be described with reference to FIGS. 13, 6, and 7.
[0085]
When the object data OD1 and the master data MD1 are input to the detailed comparison block Cij, the gradation difference calculation circuit Da1 calculates the absolute value of these gradation differences, transmits it to the addition circuit De, and sends it to the latch circuit Dd1. Latch the value.
[0086]
When the next object data OD1 and master data MD1 are input to the gradation difference calculation circuit Da1, the absolute value of the gradation difference between the two data is similarly calculated and transmitted to the addition circuit De and latched in the latch circuit Dd1. Let At this time, the data of the previous pixel that has been latched by the latch circuit Dd1 is output to the adder circuit De. As a result, the absolute value of the gradation difference between the object data OD1 and master data MD1 for two pixels continuous in the main scanning direction is input to the adder circuit De.
[0087]
Similarly, object data OD2 and master data MD2 delayed by one line with respect to the object data OD1 and master data MD1 are sequentially input to the gradation difference calculation circuit Da2, and the absolute values of the gradation differences are obtained. The absolute value of the gradation difference between the latched object data OD2 and master data MD2 is transmitted to the adder circuit De while being transmitted to the adder circuit De.
[0088]
As described above, the absolute value of the gradation difference between the two data corresponding to the window of 2 × 2 pixels is input to the adder circuit De, and the adder circuit De calculates the sum and transmits it to the selection output circuit Db.
[0089]
When the sum of absolute values of gradation differences is input to the selection output circuit Db, the maximum value of the sum of absolute values of gradation differences stored in the maximum gradation difference holding circuit Dc is read and compared. Do. Then, the smaller data is sent to the maximum gradation difference holding circuit Dc. In this way, the maximum gradation difference holding circuit Dc sequentially holds the values output from the selection output circuit Db as the maximum values, and finally the levels in each window in the detailed comparison block Cij obtained. The maximum gradation difference which is the maximum value of the sum of absolute values of the gradation is output.
[0090]
In the above, shifting the data in the shift register to the right means that the inspection windows W and W ′ shown in FIG. 1 are scanned to the right, and therefore, input to the detailed comparison block Cij. The maximum gradation difference output at the end of scanning of the entire pattern area is the maximum gradation difference obtained in the positional relationship between the corresponding object pattern and the master pattern in FIG. 1, and this is obtained from all the detailed comparison blocks Cij. Are output and collected in the minimum difference selection circuit Cb (see FIG. 9), where the minimum and maximum gradation difference candidates are output, which are further output from all the comparison detection blocks Bij (see FIG. 6). Collected in the decision circuit Ba, the minimum maximum gradation difference, which is the minimum of them, is obtained. Then, the obtained minimum / maximum gradation difference is transmitted to the defect determination circuit Bb, where it is compared with the determination threshold value, and defect detection is performed in the same manner as in the first embodiment. Thus, the comparison process between the inspection area P0 and all of the master areas M11 to MBB shown in FIG. 1 is performed. Then, the defect inspection of the entire inspection object is performed by making such a determination on all blocks of all the inspection images.
[0091]
With this configuration, this apparatus performs defect detection with a window size of 2 × 2 pixels. By the way, there may be a case where a defect having a plurality of pixel sizes in which the gradation difference does not exceed a threshold value in the object pattern such as the defects d1 to d3 in FIG. This is likely to occur when the center of the defect is located at the pixel boundary when the analog image signal is digitized. In such a case, since the apparatus of the first embodiment uses one pixel as the window, such defects d1 to d3 cannot be detected. However, in the second embodiment, the window size is set to 2. X2 pixels, and the sum of the absolute values of the difference between the gradation values of the object data and the master data in each pixel in the window is taken and compared with the determination threshold value, so that the defect is detected. Such defects d1 to d3 can also be detected.
[0092]
In addition to such an effect, according to the second embodiment, it is possible to obtain an effect other than the effect that “a defect of about one pixel can be detected” in the first embodiment.
[0093]
<4. Third Embodiment>
The apparatus according to the first embodiment detects a defect by obtaining the maximum value of the absolute value of the gradation difference in each block Cij and comparing the minimum maximum gradation difference, which is the minimum value among them, with a determination threshold value. However, in the third embodiment, each comparison detection block Bij holds the result obtained by comparing the absolute value of the gradation difference with the determination threshold value, and collects them and performs a logical product operation. Thus, the defect detection result is obtained. Therefore, in the apparatus of the third embodiment, the configuration of the comparison unit 16b in the defect inspection unit 16 is different. The other configuration is the same as that of the apparatus of the first embodiment, and the window is also one pixel size. The configuration of the comparison unit 16b in the apparatus according to the third embodiment and the defect detection process using the same will be described below.
[0094]
FIG. 14 is a diagram showing a schematic circuit configuration of the comparison unit 16b of the defect inspection unit 16 of the pattern defect inspection apparatus according to the third embodiment. FIG. 15 shows a comparison detection block Bij (i) of the comparison unit 16b of FIG. = 1 to 3, j = 1 to 3). FIG. 16 is a diagram illustrating a specific circuit configuration of the detailed comparison block Cij in FIG.
[0095]
As shown in FIG. 16, the detailed comparison block Cij obtains the absolute value of the gradation difference between the input master data MD and the object data OD and transmits it to the determination circuit Df.
[0096]
The determination circuit Df compares the transmitted signal with a determination threshold value, and if it is less than the determination threshold value, the object data OD and the master data MD match and “0” is set. Since the data does not match, “1” is transmitted as a result signal to the OR gate Dg.
[0097]
The OR gate Dg receives the result signal from the determination circuit Df and the result signal held in the result holding circuit Dh so far, performs a logical sum operation of the result signals, and holds the output in the result holding circuit Dh. Is done. Once the result signal “1” is input, the result holding circuit Dh holds the state until the inspection (comparison) on the block to be inspected is completed.
[0098]
In FIG. 15, the result signals obtained from the detailed comparison blocks Cij are collected in the AND gate Cc and subjected to AND operation, and the result signal is output to the AND gate Bc (FIG. 14).
[0099]
In FIG. 14, the result signals output from the respective comparison detection blocks Bij are collected in the AND gate Bc and subjected to AND operation, and the result is output as the final inspection result signal.
[0100]
As a result, the logical product operation of the result signals obtained by the comparison processing between the inspection area P0 and the master pattern areas M11 to MBB shown in FIG. 1 is performed, so that the inspection area P0 and the master areas M11 to MBB are performed. If it is determined that the two patterns match (result signal “0”), the inspection result signal is also “0”, and it is determined that there is no defect in the inspection area P0. On the other hand, if it is determined that the two patterns do not match (result signal “1”) in all comparisons of both areas, the inspection result signal is also “1”, and it is determined that the inspection area P 0 has a defect. . Then, the defect inspection of the entire inspection object is performed by performing such a determination on all the blocks of all the inspection images.
[0101]
As described above, according to the third embodiment, in addition to being able to obtain an effect other than the effect of “being a device with good maintainability” in the first embodiment, Since only the 1-bit result signal is held for each of the master areas M11 to MBB, the capacity of the holding circuit can be reduced.
[0102]
<5. Fourth Embodiment>
In the pattern defect inspection apparatus according to the third embodiment, a window of one pixel size is used, and each detailed comparison block Cij outputs only a result signal. The pattern defect inspection apparatus according to the fourth embodiment Uses a window with 2 × 2 pixels, and each detailed comparison block Cij outputs only the result signal. Therefore, in the apparatus of the fourth embodiment, the configuration of each detailed comparison block Cij of each comparison detection block Bij of the comparison unit 16b in the delay unit 16a of the defect inspection unit 16 is different. Other configurations are the same as those of the apparatus according to the third embodiment.
[0103]
FIG. 17 is a diagram showing a specific circuit configuration of the detailed comparison block Cij in the fourth embodiment. Hereinafter, the circuit configuration in the apparatus of the fourth embodiment and pattern defect detection by the apparatus will be described with reference to FIG. 17 (and FIGS. 14 and 15).
[0104]
When the object data OD1 and the master data MD1 are input to the detailed comparison block Cij, the gradation difference calculation circuit Da1 calculates the absolute value of these gradation differences and transmits it to the determination circuit Df1.
[0105]
The determination circuit Df1 compares the absolute value of the obtained gradation difference with the determination threshold value. The latch circuit Dd1 latches the result signal as a result signal and transmits the result signal directly to the AND gate Dk.
[0106]
When a result signal based on the comparison between the next object data OD1 and master data MD1 is input to the latch circuit Dd1, a result signal based on both data is also obtained and transmitted to the AND gate Dk and latched by the latch circuit Dd1. At this time, the result signal of the previous pixel that has been latched in the latch circuit Dd1 is output to the AND gate Dk. As a result, a result signal obtained by comparing the object data OD1 for two pixels continuous in the main scanning direction and the master data MD1 is input to the AND gate Dk.
[0107]
Similarly, object data OD2 and master data MD2 delayed by one line with respect to the object data OD1 and master data MD1 are sequentially input to the gradation difference calculation circuit Da2, and the absolute values of the gradation differences are obtained. It is transmitted to the determination circuit Df2. A part of the result signal similar to the above obtained by the determination circuit Df2 is directly transmitted to the AND gate Dk, and the other is latched by the latch circuit Dd2, and also latched by the latch circuit Dd2. The result signal of the previous pixel is transmitted to the AND gate Dk.
[0108]
As described above, the result signal for each pixel of both data corresponding to the window of 2 × 2 pixels is input to the AND gate Dk and subjected to AND operation, and the result signal representing the operation result is output to the holding circuit Dj. Is done. Once the result signal of “1” is input, the holding circuit Dj holds the state until the inspection of the block to be inspected is completed.
[0109]
As a result, the result signal is output while the inspection windows W and W ′ shown in FIG. 1 are scanned to the right. Accordingly, the result signal output at the end of scanning of the entire pattern input to the detailed comparison block Cij is the result signal obtained in the positional relationship between the corresponding object pattern and master pattern in FIG. All the detailed comparison blocks Cij are output and collected in an AND gate Cc (see FIG. 15) to perform an AND operation. Further, it is output from all the comparison detection blocks Bij (see FIG. 14) and ANDed. The result is collected in the gate Bc, and further subjected to a logical product operation, and a final inspection result signal is output.
[0110]
Thus, the comparison process between the inspection area P0 and all of the master areas M11 to MBB shown in FIG. 1 is performed. Then, the defect inspection of the entire inspection object is performed by making such a determination on all blocks of all the inspection images.
[0111]
As described above, according to the fourth embodiment, it is possible to obtain effects other than the effect of “can be an apparatus with good maintainability” in the second embodiment.
[0112]
<6. Modification>
In the first to fourth embodiments, an example of the pattern defect detection apparatus and the pattern defect detection process using the pattern defect detection apparatus has been described. However, the present invention is not limited to this.
[0113]
In the first and third embodiments, the window is one pixel size, and in the second and fourth embodiments, the window is 2 × 2 pixels. The shape may not be a square like 2 × 3 pixels. Further, assuming that both of the circuit configurations of the first and second embodiments are provided, the window may be switched between the one pixel and the 2 × 2 pixels through the operation unit 19.
[0114]
In the first to fourth embodiments, the pattern defect detection processing is performed by the circuit in the defect inspection unit 16, but it may be performed by software by providing a CPU, a memory, and the like.
[0115]
In the first to fourth embodiments, the comparative inspection by the “shaking method” is performed using the master areas M11 to MBB that are displaced in units of 0.2 pixels. It may be a unit of shaking from 0 pixels or more.
[0116]
Furthermore, in the first to fourth embodiments, the master pattern is interpolated by linear interpolation, but interpolation methods such as polynomial interpolation and spline interpolation are arbitrary.
[0117]
【The invention's effect】
As described above, according to the inventions of claim 1 and claims 2 to 6, since the multi-value image signals of the object pattern and the master pattern are compared with each other to detect defects, Since it is not necessary to perform digitization, and therefore a defect of about one pixel can be detected without detecting a quantization error as a defect, highly accurate defect detection can be performed.
[0118]
  Also, two-dimensionally over the extended area of the master patternSmaller than the size of one pixelIn order to detect defects by comparing the multi-value image signal of a plurality of master areas displaced by a predetermined amount per unit amount and the multi-value image signal of the inspection area of the object pattern for each of the plurality of master areas, High-accuracy defect detection can be performed without accurately aligning the inspection object.
[0119]
In particular, according to the invention of claim 3, by interpolating the multi-value image signal of the master pattern, the multi-values of a plurality of master areas which are displaced by a predetermined amount by a unit amount smaller than the size of one pixel. Since the image signals are obtained and compared with the multi-value image signals in the inspection area of the object pattern, it is possible to detect a defect with higher accuracy without performing accurate alignment.
[0120]
In particular, according to the fourth aspect of the invention, since inspection is performed using multi-value image signals of a plurality of master pattern areas obtained by performing interpolation for each direction of a two-dimensional orthogonal axis, Even when there is a significant misalignment, it is possible to reliably detect defects without performing accurate alignment.
[0121]
In particular, according to the invention of claim 5, the maximum value among the absolute values of the gradation difference is obtained and held for each of the plurality of master areas, and the minimum value among these maximum values is selected. Since the defect is detected by comparing the minimum value with the threshold value, it is possible to easily change the inspection accuracy by changing the setting of the threshold value, so that an apparatus with good maintainability can be obtained.
[0122]
In particular, according to the invention of claim 6, since the comparison result for each of the plurality of master areas is held and the defect detection is performed based on the held comparison result, the storage capacity can be reduced.
[Brief description of the drawings]
FIG. 1 is a diagram conceptually showing a “shaking method” for pattern defect detection according to an embodiment of the present invention.
FIG. 2 is a diagram for explaining the concept of a multi-valued image signal that is displaced in units of less than one pixel in the embodiment.
FIG. 3 is a diagram illustrating an example in which pattern matching is performed using a deviation image signal in units of less than one pixel.
FIG. 4 is a diagram for explaining inspection areas in an object pattern and a master pattern according to the first embodiment.
FIG. 5 is a diagram showing a schematic configuration of the pattern defect detection apparatus according to the first embodiment;
FIG. 6 is a diagram illustrating a schematic circuit configuration of a comparison unit in the pattern defect detection apparatus according to the first embodiment;
FIG. 7 is a specific circuit diagram of a comparison detection block in the first embodiment.
FIG. 8 is a diagram illustrating a specific circuit configuration of a detailed comparison block according to the first embodiment.
FIG. 9 is a flowchart showing a procedure of defect detection processing in the first embodiment.
FIG. 10 is a flowchart for explaining in detail the comparison inspection processing procedure of FIG. 9;
FIG. 11 is a flowchart illustrating in detail the pattern matching process of FIG. 10;
FIG. 12 is a diagram for explaining generation of a detection error when an object pattern is interpolated.
FIG. 13 is a diagram illustrating a specific circuit configuration of a detailed comparison block according to the second embodiment.
FIG. 14 is a diagram illustrating a schematic circuit configuration of a comparison unit of a defect inspection unit of the pattern defect inspection apparatus according to the third embodiment.
15 is a diagram showing a specific circuit configuration of a comparison detection block of the comparison unit in FIG. 14;
16 is a diagram showing a specific circuit configuration of a detailed comparison block in FIG. 15;
FIG. 17 is a diagram showing a specific circuit configuration of a detailed comparison block in the fourth embodiment.
FIG. 18 is a diagram for explaining an outline of processing for pattern defect inspection by a conventional pattern matching method;
[Explanation of symbols]
8 CCD line sensor (input means)
15 memory
16 Defect inspection department
16a Delay part (extraction means)
16b comparison part
B11-B33 comparison detection block (combined with Ba and Bb)
Ba Minimum difference determination circuit
Bb defect determination circuit
C11-C55 Detailed comparison block
Ca image interpolation unit
Cb minimum difference selection circuit
Da, Da1, Da2 gradation difference calculation circuit
Db selection output circuit
Dc Maximum gradation difference holding circuit
De addition circuit
Df, Df1, Df2 determination circuit
Dh result holding circuit
M11 ~ MBB Master area
P0 inspection area
W, W 'defect inspection window

Claims (6)

A pattern defect detection method for performing defect detection by comparing a two-dimensional object pattern with a two-dimensional master pattern for each area of a predetermined size,
(a) A unit quantity that is two-dimensionally smaller than the size of one pixel over an extended area that extends around the required number of pixels around the inspection area of the object pattern and the area of the master pattern that should be positioned relative to the inspection area Setting a plurality of master areas displaced by a predetermined amount each time ;
(b) and the multi-level image signal of the plurality of master regions, on the basis of the multivalued image signal of the examination zone, for all the pixels of the plurality of master zone, multi each corresponding pixels of the test Zone zone Obtaining a gradation difference absolute value which is an absolute value of the gradation difference of the value image signal;
comparing the (c) gradation difference absolute value with a predetermined threshold value, and determining the presence or absence of a defect in the inspection zone,
A pattern defect detection method comprising: A pattern defect detection device that performs defect detection by comparing a two-dimensional object pattern with a two-dimensional master pattern for each area of a predetermined size,
Means for inputting a multi-value image signal of the object pattern;
Means for storing a multi-value image signal of the master pattern;
The size of one pixel in a two-dimensional manner over the multi-value image signal in the inspection area of the object pattern and the extended area extending around the required number of pixels around the area of the master pattern that should be positionally corresponding to the inspection area Extraction means for respectively extracting multi-value image signals in a plurality of master areas that are displaced by a predetermined amount by smaller unit amounts;
Comprising a multivalued image signal within said plurality of master zone and a test unit for receiving the multi-value image signal of the examination area,
The inspection means includes
For all pixels of said plurality of master zone, a gray level difference calculating means asking you to gradation difference absolute value is an absolute value of the gradation difference between the contone image signal for each pixel of the phase corresponding the test Zone zone,
A result determination means for gradation difference compares the absolute value with a predetermined threshold value, to determine the presence or absence of defects in the examination zone determined by the gray level difference calculating means,
Pattern defect detecting apparatus characterized in that comprises a. The pattern defect detection apparatus according to claim 2,
It is intended that before Ki抽 detecting means to obtain a multi-value image signals of a plurality of master regions of multivalued image signal by interpolating misaligned by the predetermined amount by size smaller than a unit quantity of said one pixel of said master pattern A pattern defect detection device characterized by the above. The pattern defect detection device according to claim 3,
A pattern defect detection apparatus, wherein the interpolation is performed for each direction of a two-dimensional orthogonal axis. The pattern defect detection device according to any one of claims 2 to 4,
The result determination means is
A maximum difference holding means for the maximum value holding determined Umate in each of said plurality of master zone from the gray level difference absolute value obtained by the gray-scale difference calculation means,
Minimum value selection means for selecting the minimum value of the maximum values held in the maximum difference holding means ;
The minimum value selected by the minimum value selection means is compared with the threshold value, and when the minimum value is less than the threshold value, the inspection area is determined as having no defect, and the minimum value is determined. There pattern defect detecting apparatus characterized by the said examination zone equal to or greater than the threshold value is one and a judging means for judging there defect. The pattern defect detection device according to any one of claims 2 to 4,
The result determination means is
All the gradation difference absolute values in one master area are compared with the threshold value, and if all the gradation difference absolute values are less than the threshold value, it is determined that the one master area is a pattern match. and at least one when gradation difference absolute value is equal to or greater than the threshold value the primary master zone coincides determines the pattern mismatch decision means of said every gradation difference absolute value,
Comparison result holding means for holding a comparison result by the match determination means for each of the plurality of master areas;
With
The comparison results when all of the comparison results held is the pattern mismatch holding means makes a determination of defect there for the examination zone, the test if at least one of said comparison result the pattern matching pattern defect detecting apparatus characterized by about areas is to Umo line determination without defects.

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