JP4095002B2 - Random number generator - Google Patents

Description

  The present invention relates to a random number generation circuit, and more particularly to a random number generation circuit that generates random numbers having no regularity.

  Conventionally, encryption using random numbers is used for protecting information such as password generation, encryption key generation, ID information generation, and digital signature additional information generation in electronic commerce and information communication such as wireless communication. As a random number generation method, a method generated by software is widely adopted. However, the random number generation method by software generates a random number based on a mathematical expression described in a program, and thus has a drawback of having some regularity. That is, there is a possibility that encryption having regularity may be decrypted, and personal information cannot be sufficiently protected. That is, a random number that does not depend on frequency characteristics has been demanded.

  On the other hand, there is a method of generating a random number having no periodicity by the 1 / f characteristic by a random number generation circuit based on the noise generated from the noise generation source having the 1 / f characteristic (see Patent Document 1). .

  As shown in FIG. 16, the random number generation circuit described in Patent Document 1 includes noise generation circuits 201 and 202, a differential circuit 203 connected to the output side of each of the noise generation circuits 201 and 202, and a differential circuit 203. The A / D conversion circuit 204 connected to the output side of the A / D converter and the arithmetic circuit 205 connected to the output side of the A / D conversion circuit 204 are configured.

First, the noise generation circuits 201 and 202 output a noise signal having 1 / f characteristics. Next, the differential circuit 203 outputs the differential signal of the two noise signals output from the noise generation circuits 201 and 202 as an analog signal. The A / D conversion circuit 204 converts an analog signal output from the differential circuit into a digital signal. The arithmetic circuit 205 outputs “0” when the digitally converted signal does not reach the threshold level, and outputs “1” when the signal reaches the threshold level. The arithmetic circuit 205 adjusts the threshold level so that the probability that “0” and “1” appear is 0.5.
JP 2002-41281 A

  However, since the random number generation circuit shown in FIG. 16 uses an analog circuit such as a filter and a differential circuit and two noise generation circuits, there is a problem that the occupied area becomes large. Further, it is necessary to set the probability of occurrence of “0” and “1” by changing the threshold level of the arithmetic circuit 205.

  An object of the present invention is to reduce the size without using a plurality of noise generation circuits, generate a random number independent of frequency characteristics, and eliminate the need to adjust the probability of occurrence of “0” and “1”. Is to provide a random number generation circuit capable of

In order to achieve the above object, the first feature of the present invention is that a clock signal and a random signal are input, and the count value of the clock signal is alternately switched between a low level and a high level for each count according to a change in the random signal. 1 and bit counter circuit switched output, and a first latch circuit and outputs the latched first random number signal a count value in response to changes in the random signals, random signals, compared increasing frequency The gist of the present invention is that it is a random number generation circuit having a characteristic that the power spectrum decreases.

  According to the first feature of the present invention, a random number that does not depend on frequency characteristics can be generated without using a plurality of noise generation circuits, and the probability of occurrence of “0” and “1” is adjusted. Can be provided.

In order to achieve the above object, the second feature of the present invention is that a random signal and a clock signal are inputted, and a high frequency and a low level are alternately outputted according to a logical product output of the random signal and the clock signal. Circuit and a latch circuit that latches the count value of the clock signal in response to a change in the random signal and outputs a random number signal, and the random signal has a characteristic that the power spectrum decreases as the frequency increases It is a summary.

  According to the second feature of the present invention, it is possible to reduce the size without using a plurality of noise generation circuits, generate random numbers independent of frequency characteristics, and adjust the probability of occurrence of “0” and “1”. Can be provided.

  According to the present invention, it is possible to reduce the size without using a plurality of noise generation circuits, generate random numbers independent of frequency characteristics, and eliminate the need for adjusting the probability of occurrence of “0” and “1”. Can be provided.

  Next, first to fifth embodiments of the present invention will be described with reference to the drawings. In the following description of the drawings, the same or similar parts are denoted by the same or similar reference numerals.

  First, the “random signal RS” used in the first to fifth embodiments will be described. The “random signal RS” is a digital signal composed of a plurality of rectangular waves whose on width and off width are not constant. Further, the “random signal RS” has a characteristic that the value of the power spectrum is not constant with respect to an increase in frequency, and particularly decreases. The amplitude of the rectangular wave is preferably constant, but is not particularly limited here. For example, the random signal RS is generated by an oscillation circuit that uses the delay time of a CR delay circuit formed of a resistor and a capacitor. Generated by using random fluctuations in resistance and capacitor values. An example of a signal whose power spectrum decreases is a fluctuation signal having a 1 / f characteristic. “1 / f” means that the power spectrum obtained by Fourier analysis has a 45-degree slope in inverse proportion to the Fourier frequency f. That is, when spectrum analysis of time series data such as array and space is performed, the slope obtained by the logarithmic plot shows -1.

(First embodiment)
As shown in FIG. 1, the random number generation circuit 10a according to the first embodiment of the present invention is connected to a clock input CK that inputs a clock signal CS and a clock enable input CE that inputs a random signal RS. A counter circuit 1 that outputs a count value of the clock signal CS according to a change in the random signal RS, and a first latch circuit 3 that latches the count value according to a change in the random signal RS and outputs a random number signal RNS Is provided. Further, the inverter 2 is connected between a connection point between the rectangular wave input 51 and the clock enable input CE of the counter circuit 1 and the clock input CK of the first latch circuit 3. The rectangular wave input 51 inputs a random signal RS to the clock enable input CE of the counter circuit 1. The clock input 52 inputs the clock signal CS to the clock input CK of the counter circuit 1. The output node of the inverter 2 is electrically connected to the clock input CK of the first latch circuit 3. The output Q of the counter circuit 1 is electrically connected to the input D of the first latch circuit 3. The output Q of the first latch circuit 3 is electrically connected to the random number output 53.

  The operation of the random number generation circuit 10a according to the first embodiment of the present invention will be described with reference to FIG.

(A) First, at time t1, as shown in FIG. 2A, the random signal RS input to the rectangular wave input 51 changes from low level to high level.

(B) From time t1 to t2, in the state where the random signal RS is at a high level, the counter circuit 1 outputs the count signal CTS from the output Q. As shown in FIG. 2C, the count signal CTS alternately switches between the high level and the low level every time the rising edge of the clock signal CS shown in FIG. 2B is detected. Here, it is assumed that the counter circuit 1 is, for example, a 1-bit counter in which a low level and a high level are alternately switched every count.

(C) At time t2, the random signal RS changes from the high level to the low level. When the random signal RS becomes low level, the inverter 2 outputs a random inverted signal RS bar that becomes high level as shown in FIG. When the random inverted signal RS is at a high level, the first latch circuit 3 latches the count signal CTS output from the counter circuit 1 at the rising edge of the clock input CK, as shown in FIG. A random number signal RNS is output.

(D) At time t3, the random signal RS again changes from the low level to the high level. The counter circuit 1 alternately switches the level of the count signal CTS every time the rising edge of the clock signal CS is detected while the random signal RS remains in the high level state.

(E) At time t4, the random signal RS changes from the high level to the low level. When the random signal RS becomes low level, the inverter 2 outputs a random inverted signal RS bar that becomes high level as shown in FIG. When the random inverted signal RS is at a high level, the first latch circuit 3 latches the count signal CTS output from the counter circuit 1 at the rising edge of the clock input CK, as shown in FIG. A random number signal RNS is output. Thereafter, similarly, the operation of outputting the random number signal RNS at the falling edge of the random signal RS is repeated.

で表される。 Next, the probability that the output of the random number signal RNS is “0” or “1” will be described with reference to FIG. However, the random signal RS will be schematically described on the assumption that it is a function of y = F (s). Assume that the on width of the random rectangular wave constituting the random signal RS is T, the minimum on width is Tmin, and the maximum on width is Tmax. Further, a value obtained by dividing the ON width region TZ obtained by subtracting the minimum ON width Tmin from the maximum ON width Tmax by the period of the resolution setting clock signal SC is set as the division number N. The on-width region TZ is determined by a resistance that is a source of a random rectangular wave, a frequency characteristic of an element such as a diode, a characteristic of a circuit that outputs the rectangular wave, a characteristic of a filter, and the like. At this time, assuming that the distribution function of a random rectangular wave with an ON width T is F (t), the probability Pt (0) that “0” is output from the random number generation circuit when the division number N is an even number is

It is represented by

で表される。 The probability Pt (1) that 1 is output from the random number generation circuit when the division number N is an even number is

It is represented by

で表される。 The probability Pt (0) that 0 is output from the random number generation circuit when the division number N is an odd number is:

It is represented by

で表される。 The probability Pt (1) that 1 is output from the random number generation circuit when the division number N is an odd number is:

It is represented by

が求められる。 Here, the difference in the frequency of 0 and 1 when the division number N is an even number is represented by Pt (0) -Pt (1). When this is calculated,

Is required.

が求められる。 Further, the difference between the frequency of 0 and 1 when the division number N is an even number is represented by Pt (0) −Pt (1).

Is required.

  Regardless of whether the number of divisions N is an even number or an odd number from the equations (5) and (6), the larger the value of the number of divisions N, the smaller the difference in the appearance frequency of “0” and “1”. That is, as the frequency of the clock signal CS is higher, the frequency of occurrence of “0” and “1” is less biased. That is, when generating a random number, it is necessary to select the frequency of the clock signal in consideration of the characteristics of the random number to be used.

The difference δ (0) between the ideal value 0.5 and the probability of occurrence of 0 is
[Equation 7]
δ (0) = 0.5− | (Pt (0) / (Pt (0) + Pt (1)) |
(7)
It is represented by

Also, the difference δ (1) between the ideal value 0.5 and the probability of occurrence of 1 is
[Equation 8]
δ (1) = 0.5− | (Pt (1) / (Pt (0) + Pt (1)) |
(8)
It is represented by

  The values of δ (0) and δ (1) are determined by usage criteria. For example, if the US Department of Commerce follows the FIPS 140-2 standard test for communication network security, the value of δ (0) or δ (1) must be 0.01375 or less. That is, it is necessary to set the frequency of the clock signal CK to satisfy the reference value.

で表される。 As one of the methods for expressing the random signal RS, a power spectrum is used in which the power of the signal is divided into fixed frequency bands and the power of each band is expressed as a function of frequency. The spectrum of the periodic signal waveform is composed of a fundamental frequency and its harmonic components, and can be represented by the sum of the squares of the amplitudes of the respective components. Assuming that the power spectrum is a time function x (t) and a power spectrum X (f),

It is represented by

  As shown in FIG. 4, the random signal RS input to the random number generation circuit 10a is assumed that the signal intensity of the power spectrum indicated by the vertical axis is inversely proportional to the frequency indicated by the horizontal axis. At this time, as shown in FIG. 5, the distribution of the frequency with which the random signal RS has the ON width T is indicated by a curve in which the horizontal axis direction indicated by the power spectrum characteristics is changed from frequency to period. The output of the random number generation circuit when the ON width is T (s) determines whether “0” or “1” is output for each cycle Tck of the clock signal CS. The smaller the cycle of the clock signal CS, the closer the probability of “0” and “1” appearing to 0.5.

  L1 shown in FIG. 6 represents the power spectrum of the random number signal RNS output from the random number generation circuit 10a shown in FIG. L2 represents the power spectrum of the random signal RS generated from the 1 / f noise source. While the power spectrum for the random signal RS decreases as the frequency increases, the power spectrum L1 of the random number signal RNS can generate the random number signal RNS without depending on the frequency characteristics.

  Further, when the random signal RS is input as 8-bit serial data, the previous data is plotted at 0 to 255 indicated by the vertical axis, and the next acquired data is plotted at 2500 points along the horizontal axis. At this time, the random number signal RNS output from the random number generation circuit 10a is distributed almost uniformly as shown in FIG. On the other hand, the random numbers output from the conventional random number generation circuit vary as shown in FIG.

  According to the random number generation circuit 10a according to the first embodiment of the present invention, it is possible to reduce the size without using a plurality of noise generation circuits, and to generate random numbers that do not depend on frequency characteristics. It is possible to eliminate the need to adjust the probability of occurrence of “1”.

(Second Embodiment)
As shown in FIG. 8, the random number generation circuit 10b according to the second embodiment of the present invention includes a second latch circuit 4 on the output side of the first latch circuit 3 of the random number generation circuit 10a shown in FIG. It is different in that one stage is added. The input D of the second latch circuit 4 is electrically connected to the output Q of the first latch circuit 3. The output Q of the second latch circuit 4 is connected to the random number output 53. The clock input CK is connected to the random number acquisition clock input 54, respectively. The random number acquisition clock input 54 inputs a random number clock acquisition signal having a constant period. Others are substantially the same as those in the first embodiment, and thus redundant description is omitted.

  Next, the operation of the random number generation circuit according to the second embodiment of the present invention will be described with reference to FIG.

(A) First, at time t1, as shown in FIG. 9A, the random signal RS input to the rectangular wave input 51 changes from the low level to the high level.

(B) When the random signal RS is in the high level from time t1 to t2, the level of the count signal CTS output from the output Q of the counter circuit 1 is alternately switched every time the rising edge of the clock signal CS is detected. .

(C) At time t2, the random signal RS changes from the high level to the low level. When the random signal RS becomes low level, the inverter 2 outputs a random inverted signal RS bar that becomes high level as shown in FIG. 9 (d). When the random inverted signal RS is at a high level, the first latch circuit 3 latches the count signal CTS output from the counter circuit 1 at the rising edge of the clock input CK, as shown in FIG. The first random number signal RNS1 is output.

(D) At time t3, as shown in FIG. 9 (f), the random number acquisition clock signal RTS whose cycle is constant changes from low level to high level. The second latch circuit 4 latches the first random number signal RNS1 at the rising edge of the random number acquisition clock signal RTS, and outputs the second random number signal RNS2 as shown in FIG. 9 (g). Thereafter, similarly, the operation of outputting the random number signal RNS at the falling edge of the random signal RS is repeated.

  According to the random number generation circuit 10b according to the second embodiment of the present invention, it is possible to reduce the size without using a plurality of noise generation circuits, and to generate random numbers that do not depend on the frequency characteristics. It is possible to eliminate the need to adjust the probability of occurrence of “1”. Further, by using the random number signal RNS output from the second latch circuit 4, random numbers can be acquired at regular time intervals.

(Third embodiment)
As shown in FIG. 10, the random number generation circuit 10c according to the third embodiment of the present invention is provided between the clock enable input CE and the rectangular wave input 51 of the counter circuit 1 of the random number generation circuit 10a shown in FIG. The difference is that a pulse counter 5 is provided. The pulse counter 5 has an input side electrically connected to the rectangular wave input 51 and an output side electrically connected to the clock enable input CE of the counter circuit 1. Others are substantially the same as those in the first embodiment, and thus redundant description is omitted.

  The operation of the random number generation circuit 10c according to the third embodiment of the present invention will be described with reference to FIG.

(A) First, at time t1, the first random signal RS1 shown in FIG. 11A changes from the low level to the high level. When the pulse counter 5 detects the rising edge of the first random signal RS1, as shown in FIG. 11B, the pulse counter 5 outputs the second random signal RS2 that becomes a high level.

(B) From time t1 to time t2, the random signal RS is in a high level state. At this time, as shown in FIG. 11 (d), the level of the count signal CTS output from the output Q of the counter circuit 1 is alternately switched every time the rising edge of the clock signal CS shown in FIG. 11 (c) is detected. The pulse counter 5 counts rising edges of the random signal RS1. However, the pulse counter 5 is assumed to switch the output when the count value becomes 2, for example.

(C) When the count value of the pulse counter 5 becomes 2 at time t2, the second random signal RS2 changes from high level to low level. When the second random signal RS2 becomes low level, the clock input CK of the first latch circuit 3 becomes high level as shown in FIG. 11 (d). The first latch circuit 3 latches the count signal CTS output from the counter circuit 1 at the rising edge of the clock input CK, and outputs the random number signal RNS to the random number output 53. Thereafter, similarly, the operation of outputting the random number signal RNS at the falling edge of the random signal RS is repeated.

  According to the random number generation circuit 10c according to the third embodiment of the present invention, it is possible to reduce the size without using a plurality of noise generation circuits, and to generate random numbers that do not depend on the frequency characteristics. It is possible to eliminate the need to adjust the probability of occurrence of “1”. Further, even if the minimum on-width Tmin of the random signal is not more than twice the cycle Tck of the clock signal CS, it is possible to operate by generating a new signal having a large minimum on-width.

(Fourth embodiment)
As shown in FIG. 12, the random number generation circuit 10d according to the fourth exemplary embodiment of the present invention receives a random signal RS and a clock signal CS whose on width and off width are not constant, and receives the random signal RS and the clock signal CS. A frequency dividing circuit 6 that outputs a frequency-divided signal DRS that alternately switches between a high level and a low level in response to a change in the logical product output of the signal, and a frequency-divided signal DRS that is latched in response to a change in the random signal RS And a first latch circuit 3 for outputting.

  The frequency dividing circuit 6 has a first input node connected to the rectangular wave input 51 and a second input node connected to the clock input 52, and a frequency divider that connects the output of the AND circuit 20 to the clock input. A latch circuit 21 and an inverter 22 connected between the output Q and the input D of the frequency division latch circuit 21 are provided.

  The operation of the random number generation circuit 10d according to the fourth embodiment of the present invention will be described with reference to FIG.

(A) First, as shown in FIG. 13A, at time t1, the random signal RS input to the rectangular wave input 51 changes from a low level to a high level.

(B) When the random signal RS is at a high level from time t1 to time t2, as shown in FIG. 13C, the clock signal CS shown in FIG. Is output. At this time, as shown in FIG. 13 (d), the level of the frequency-divided signal DRS output from the output Q of the frequency-dividing latch circuit 21 is alternately switched every time the rising edge of the clock signal CS is detected.

(C) When the random signal RS changes from the high level to the low level at time t2, as shown in FIG. 13E, the clock input CK of the first latch circuit 3 becomes the high level. When the clock input CK becomes high level, the first latch circuit 3 latches the frequency-divided signal DRS and outputs the random number signal RNS from the random number output 53 as shown in FIG. Thereafter, similarly, the operation of outputting the random number signal RNS at the falling edge of the random signal RS is repeated.

  According to the random number generation circuit 10d according to the fourth exemplary embodiment of the present invention, it is possible to reduce the size without using a plurality of noise generation circuits, and to generate random numbers that do not depend on the frequency characteristics. It is possible to eliminate the need to adjust the probability of occurrence of “1”.

(Fifth embodiment)
In the random number generation circuit 10e according to the fifth embodiment of the present invention, as shown in FIG. 14, the random number generation circuit 10d shown in FIG. 12 uses a latch circuit 21 (D flip-flop) as a frequency division latch circuit. On the other hand, the latch circuit 23 (JK type flip-flop is used. However, the first latch circuit 3 (D type flip-flop) is used, whereas the latch circuit 7 (JK type is used). The other is substantially the same as that of the first embodiment, and the duplicate description is omitted.

  The operation of the random number generation circuit 10e according to the fifth embodiment of the present invention will be described with reference to FIG.

(A) First, at time t1, as shown in FIG. 15A, the random signal RS changes from the low level to the high level.

(B) When the random signal RS is in the high level from time t1 to time t2, as shown in FIG. 15C, the clock signal CS shown in FIG. Is output. At this time, as shown in FIG. 15D, the level of the frequency-divided signal DRS output from the output Q of the frequency-dividing latch circuit 23 is alternately switched every time the rising edge of the clock signal CS is detected.

(C) When the random signal RS changes from the high level to the low level at time t2, as shown in FIG. 15 (f), the clock input CK of the latch circuit 7 becomes the high level. At this time, the frequency division signal DRS is input to the first input J of the latch circuit 7 as shown in FIG. Further, as shown in FIG. 15E, the frequency division inversion signal DRS bar obtained by inverting the frequency division signal DRS is input to the second input K of the latch circuit 7. The latch circuit 7 latches the frequency-divided signal DRS at the rising edge of the random inverted signal RS bar obtained by inverting the random signal RS, and outputs the random number signal RNS as shown in FIG. The random number signal RNS is output from the random number signal output 53. Thereafter, similarly, the operation of outputting the random number signal RNS at the falling edge of the random signal RS is repeated.

  According to the random number generation circuit 10e according to the fifth embodiment of the present invention, it is possible to reduce the size without using a plurality of noise generation circuits, and to generate random numbers that do not depend on the frequency characteristics. It is possible to eliminate the need to adjust the probability of occurrence of “1”.

(Other embodiments)
As described above, the present invention has been described according to the first to fifth embodiments. However, it should not be understood that the description and drawings constituting a part of this disclosure limit the present invention. From this disclosure, various alternative embodiments, examples, and operational techniques will be apparent to those skilled in the art.

  For the random number generation circuits 10d and 10e according to the fourth to fifth embodiments already described, it is possible to further provide a second latch circuit as shown in the second embodiment. Further, as shown in the third embodiment, the random number generation circuits 10d and 10e can further include a pulse counter at the output of the latch circuit. It is also possible to apply the present invention to the minimum off width by switching the roles of the rising edge and falling edge of the clock signal or random signal.

  The period of the clock signal CS used in the random number generation circuits 10a, 10b, 10c, 10d, and 10e according to the first to fifth embodiments already described is ½ or less of the ON width region Tz of the random signal RS. It is desirable to be. As the period T of the clock signal CS is set to be smaller than the on-width region Tz, the influence due to the difference in power spectrum of the random signal RS can be suppressed.

  As described above, the present invention naturally includes various embodiments not described herein. Therefore, the technical scope of the present invention is defined only by the invention specifying matters according to the scope of claims reasonable from the above description.

It is a figure explaining the random number generation circuit which concerns on the 1st Embodiment of this invention. 3 is an operation timing chart of the random number generation circuit according to the first embodiment of the present invention. It is a figure explaining the random signal input into the random number generation circuit which concerns on the 1st Embodiment of this invention. It is a figure which illustrates typically the power spectrum of the random signal which concerns on the 1st Embodiment of this invention. It is a figure explaining the random number signal produced | generated by the random number generation circuit which concerns on the 1st Embodiment of this invention. It is a figure explaining the power spectrum of the random number signal produced | generated by the random number generation circuit which concerns on the 1st Embodiment of this invention. FIG. 7A illustrates the periodicity of the random number signal generated by the random number generation circuit according to the first embodiment of the present invention. FIG. 7B is a diagram for explaining the periodicity of a random number signal generated by a conventional random number generation circuit. It is a figure explaining the random number generation circuit which concerns on the 2nd Embodiment of this invention. It is an operation | movement timing chart of the random number generation circuit which concerns on the 2nd Embodiment of this invention. It is a figure explaining the random number generation circuit which concerns on the 3rd Embodiment of this invention. It is an operation | movement timing chart of the random number generation circuit which concerns on the 3rd Embodiment of this invention. It is a figure explaining the random number generation circuit which concerns on the 4th Embodiment of this invention. It is an operation | movement timing chart of the random number generation circuit which concerns on the 4th Embodiment of this invention. It is a figure explaining the random number generation circuit which concerns on the 5th Embodiment of this invention. It is an operation | movement timing chart of the random number generation circuit which concerns on the 5th Embodiment of this invention. It is a figure explaining the conventional random number generation circuit.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Counter circuit 2, 22 ... Inverter 3 ... 1st latch circuit 4 ... 2nd latch circuit 5 ... Pulse counter 6 ... Frequency dividing circuit 10a, 10b, 10c, 10d, 10e ... Random number generation circuit 20 ... AND circuit 21 ... frequency division latch circuit 51 ... rectangular wave input 52 ... clock input 53 ... random number output 54 ... random number acquisition clock input 201, 202 ... noise generation circuit 203 ... differential circuit 204 ... D conversion circuit 205 ... arithmetic circuit

Claims (6)

A 1-bit counter circuit that inputs a clock signal and a random signal, and outputs a count value of the clock signal by alternately switching between a low level and a high level for each count according to a change in the random signal;
A first latch circuit that latches the count value according to a change in the random signal and outputs a first random number signal, and the random signal has a characteristic that a power spectrum decreases with an increase in frequency. A random number generation circuit characterized by that.   A second random number acquisition clock signal having a constant period and the first random number signal are input, the first random number signal is latched according to a change in the random number acquisition clock signal, and a second random number signal is output. The random number generation circuit according to claim 1, further comprising: a latch circuit.   The random number generation circuit according to claim 1, further comprising a pulse counter that inputs the random signal, wherein the output of the pulse counter is the random signal. An AND circuit that inputs a random signal and a clock signal and outputs a logical product of the random signal and the clock signal;
A frequency dividing latch circuit that alternately outputs a high level and a low level according to the logical product output;
A first latch circuit that latches the count value of the clock signal in response to a change in the random signal and outputs a random number signal, and the random signal has a characteristic that a power spectrum decreases with an increase in frequency. A random number generation circuit characterized by that.   A second random number acquisition clock signal having a constant period and the first random number signal are input, the first random number signal is latched according to a change in the random number acquisition clock signal, and a second random number signal is output. The random number generation circuit according to claim 4, further comprising: a latch circuit.   The random number generation circuit according to claim 4, further comprising a pulse counter for inputting the random signal, wherein the output of the pulse counter is the random signal.

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