JP4082265B2 - Manufacturing method of semiconductor device - Google Patents

Manufacturing method of semiconductor device Download PDF

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Publication number
JP4082265B2
JP4082265B2 JP2003103979A JP2003103979A JP4082265B2 JP 4082265 B2 JP4082265 B2 JP 4082265B2 JP 2003103979 A JP2003103979 A JP 2003103979A JP 2003103979 A JP2003103979 A JP 2003103979A JP 4082265 B2 JP4082265 B2 JP 4082265B2
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JP
Japan
Prior art keywords
metal layer
semiconductor
dicing
semiconductor wafer
bump
Prior art date
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Expired - Fee Related
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JP2003103979A
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Japanese (ja)
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JP2004311762A (en
Inventor
成樹 常田
宗博 江口
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Corp
Panasonic Holdings Corp
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Panasonic Corp
Matsushita Electric Industrial Co Ltd
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

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  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)

Description

【0001】
【発明の属する技術分野】
本発明は、半導体装置の製造方法に係わるものである。
【0002】
【従来の技術】
従来のチップ型半導体装置の製造方法としては、半導体チップのワイヤボンディング工程の省略を目的として、チップサイズにダイシングされた半導体ウェハを、導電性接着剤を介して金属板でサンドイッチ状に挟み込み、チップの間に封止樹脂を注入し、その後チップサイズにダイシングすることで、チップ型半導体装置を得るものがあった(例えば、特許文献1参照)。
【0003】
図2は、前記特許文献1に記載された従来のチップ型半導体装置の製造工程を示すものである。図2(a)は半導体ウェハを第一の基板に接着する工程であり、図2(b)は半導体ウェハのダイシング工程であり、図2(c)は第二の基板を半導体ウェハに接着する工程であり、図2(d)は樹脂封止工程であり、図2(e)はダイシング工程である。101は全面に電極が形成された第一の基板、102は導電性接着剤、103は何らかのデバイスが構築された半導体ウェハ、104は半導体チップ、105は全面に電極が形成された第二の基板、106はダイシング溝に充填する透光性封止樹脂である。
【0004】
詳細の製造工程を下記に説明する。まず、第一の基板101の全面に導電性接着剤102を塗布し、半導体ウェハ103を載せ、キュア炉に通して導電性接着剤102を硬化させ第一の基板101と半導体ウェハ103を接着する。次に、第一の基板を完全に切断しないようにブレードの深さを調整したダイシングマシーンを用いて、半導体ウェハ103を升目状に切断して半導体チップ104毎に分割する。次いで、上記第一の基板101と同様に、全面に電極が形成された第二の基板105の全面に導電性接着剤102を塗布し、半導体チップ104の上に位置決めして載せ、再びキュア炉に通して導電性接着剤102を硬化し、半導体チップ104と第二の基板105を接着する。そして、ダイシングによって半導体チップ104同士の間に発生した隙間に透光性封止樹脂106を充填して半導体チップ104の周囲を樹脂封止する。最後にダイシング工程で、上述のようにサンドイッチ構造となった第一の基板101、半導体チップ104及び第二の基板105を、ダイシングマシーンによって半導体チップ104毎に一緒に切断する。従って、半導体チップ104の側面に樹脂封止した透光性封止樹脂106を残すことができ、半導体チップ104の周囲を透光性封止樹脂106が取り囲んだチップ型半導体が完成する。
【0005】
【特許文献1】
特開平10−229097号公報
【0006】
【発明が解決しようとする課題】
しかしながら、前記従来の構成では、第一の基板101および第二の基板105と半導体ウェハ103の電気的接合に、導電性接着剤102を用いているため、導電性接着剤102を塗布する工程やキュアする工程等が必要となる。そのため工程が煩雑になる。また、導電性接着剤102を用いているため、第一と第二のそれぞれの基板と半導体ウェハ103との間に気泡が入り込み導通不良が起こるという課題を有していた。
【0007】
本発明は、前記従来の課題を解決するものであり、導電性接着剤102を使わずにウェハレベルで製造可能な半導体チップを提供することを目的とする。
【0008】
【課題を解決するための手段】
従来の課題を解決するために、本発明の半導体装置の製造方法は、半導体ウェハの第一主面に第一の金属層のめっきを施し電極を形成する第一電極形成工程と、次に前記半導体ウェハに形成された半導体素子の第二主面にバンプを形成するバンプ形成工程と、次に前記半導体ウェハを前記第一の金属層を残し個々の半導体素子にダイシングし溝を形成する溝形成工程と、次に前記バンプと第二の金属層とを熱圧着し電極を形成する第二電極形成工程と、次に前記溝に封止用樹脂を充填する樹脂充填工程と、次に前記第一の金属層と半導体素子間の封止樹脂と前記第二の金属層とを一度に半導体素子の個片にダイシングするダイシング工程とを備えたものであり、さらにバンプ表面と前記基板表面の各々に金めっきを備え、基板に封止用樹脂の注入に用いる貫通孔を備えたものである。

【0009】
本構成によって、導電性接着剤を使用せずにウェハレベルでの半導体装置製造が可能であり、めっき技術により外部電極を形成することで工程を削減でき、導電性接着剤の気泡抱き込みによる、導通不良を無くすことができる。
【0010】
【発明の実施の形態】
以下本発明の実施の形態について、図面を参照しながら説明する。
【0011】
(実施の形態)
図1(a)〜(f)は、本発明の実施の形態における半導体装置の製造方法である。図1(a)〜(f)において、図2と同じ構成要素については同じ符号を用い、説明を省略する。
【0012】
図1(a)〜(f)において、1は半導体ウェハ、2はウェハの一方の面に設けられた下地電極上に、電解めっきで形成した第一の金属層、3は半導体ウェハに構築されたデバイスの電極上に形成しためっきバンプ、4はデバイスが構築された半導体素子、5は半導体ウェハをチップ状にダイシングすることで形成された溝、6は半導体ウェハ上に形成されたバンプめっきと熱圧着することで外部電極となる第二の金属層、7はダイシングで形成された溝に充填し、チップの外周を取り囲む封止用樹脂、8は第二の金属層6に設けられた封止樹脂充填用の貫通孔である。
【0013】
(実施の形態の構成)
詳細な構成を下記に説明する。
【0014】
半導体ウェハ1の第一主面に設けられた下地電極(図示せず。)上に、電解めっきで銅等第一の金属層2を形成する(図1(a))。これによれば、半導体ウェハ1に金属層2を形成するときに導電性接着剤を用いる必要がなく、導電性接着剤を用いていた時に発生する気泡の抱き込み等がなく、半導体ウェハ1と金属層2との導通不良を防ぐものである。この金属層2は、そのまま半導体チップ部品の外部電極(図示せず。)となるため、ある程度の厚みが必要で、ダイシング工程を考慮すれば40μm程度の厚さにしておく必要がある。
【0015】
半導体ウェハ1に形成されたデバイスの電極上に銅等の金属のめっきによりバンプ3を形成する。バンプ3は第二の金属層6との熱圧着を行うため表面にはAu/Niめっき(図示せず。)を施している(図1(b))
【0016】
半導体ウェハ1を個々の半導体素子4にダイシングする。このとき、個々の半導体素子4にダイシングすると共に、封止用樹脂7を充填するための溝5を形成する(図1(c))。
【0017】
バンプ3と第二の金属層6として例えば銅の表面にニッケルその上に金めっきを施した金属板を熱圧着する(図1(d))。このとき、200℃程度の熱と1バンプ当たり150〜200g程度の荷重を印加し熱圧着することでバンプ3に施している金と金属層6に施している金とが結合し強固に接着するものである。また、この時圧着される第二の金属層6の中央部には、封止用樹脂7を注入するための貫通孔8が設けられている(図1(d))。
【0018】
第二の金属層6に設けられた貫通孔8より封止用樹脂7を注入することで、溝5に封止用樹脂7を充填し、半導体素子4の外囲に封止用樹脂7を充填させる。充填した後、封止用樹脂7をキュアし硬化させる。貫通孔8は、4インチウェハであればφ1mm程度が必要である(図1(e))。
【0019】
以上のような工程を経てサンドイッチ構造となった、第一の金属層2と封止用樹脂7と第二の金属層6とを、ダイシングにより個々の半導体素子4の寸法に分割する(図1(f))。このとき、第一の金属層2および第二の金属層6と封止用樹脂7の複合した状態で一度にダイシングしても良い。また、金属と樹脂とに分けてそれぞれに適したダイシングブレードを用いダイシングしても良い。さらに、ダイシング時に樹脂注入用の貫通孔8により半導体素子4とスクライブレーンのアライメントをとることも可能である。
【0020】
かかる構成によれば、半導体ウェハ1の一方の電極をめっきで形成し、もう一方側にめっきバンプを形成し金属板と熱圧着することで電極形成をすることで、導電性接着剤を使用することなく、周囲をチップ素子保護用の封止用樹脂7で取り囲んだチップ型半導体装置を、ウェハレベルで製造することができる。
【0021】
なお、本実施の形態において、外部電極として金属層を設けたが、ガラエポ基板等の基板に、金属配線をして、表面にニッケルその上に金めっき処理したものとしても良い。また、半導体ウェハ1に構築されたデバイスの電極上に設けられるバンプ3は、めっきバンプに限定されるものではなく、金等のスタットバンプを設けて金属層との熱圧着を行うことも出来る。
【0022】
また、個々の半導体素子に分割する際にダイシングを用いて説明したがこの方法に限定されることはない。
【0023】
【発明の効果】
以上のように、本発明のチップ型半導体装置の製造工程によれば、めっきで外部電極を形成することで、導電性接着剤を塗布・キュアする工程が削減でき、めっきバンプと金属板をウェハ単位で一度に圧着することで、工程を削減し導電性接着剤等を用いることによって起こる、気泡の抱き込み等の不良を無くすことができる。
【図面の簡単な説明】
【図1】本発明の実施の形態におけるチップ型半導体装置の製造工程図
【図2】従来のチップ型半導体装置の製造工程図
【符号の説明】
1 半導体ウェハ
2 第一の金属層
3 バンプ
4 半導体素子
5 溝
6 第二の金属層
7 封止用樹脂
8 貫通孔
101 第一の基板
102 導電性接着剤
103 半導体ウェハ
104 半導体チップ
105 第二の基板
106 透光性封止樹脂
[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a method for manufacturing a semiconductor device.
[0002]
[Prior art]
As a conventional method of manufacturing a chip-type semiconductor device, a semiconductor wafer diced to a chip size is sandwiched between metal plates via a conductive adhesive for the purpose of omitting the wire bonding process of the semiconductor chip, and the chip In some cases, a chip-type semiconductor device is obtained by injecting a sealing resin in between and then dicing into a chip size (see, for example, Patent Document 1).
[0003]
FIG. 2 shows a manufacturing process of the conventional chip type semiconductor device described in Patent Document 1. 2A is a process of bonding the semiconductor wafer to the first substrate, FIG. 2B is a process of dicing the semiconductor wafer, and FIG. 2C is a process of bonding the second substrate to the semiconductor wafer. 2D is a resin sealing process, and FIG. 2E is a dicing process. 101 is a first substrate with electrodes formed on the entire surface, 102 is a conductive adhesive, 103 is a semiconductor wafer on which some device is constructed, 104 is a semiconductor chip, and 105 is a second substrate with electrodes formed on the entire surface. 106 are translucent sealing resins filled in the dicing grooves.
[0004]
A detailed manufacturing process will be described below. First, the conductive adhesive 102 is applied to the entire surface of the first substrate 101, the semiconductor wafer 103 is placed, and the conductive adhesive 102 is cured by passing through a curing furnace to bond the first substrate 101 and the semiconductor wafer 103. . Next, using a dicing machine in which the blade depth is adjusted so that the first substrate is not completely cut, the semiconductor wafer 103 is cut into a grid shape and divided into semiconductor chips 104. Next, like the first substrate 101, the conductive adhesive 102 is applied to the entire surface of the second substrate 105 on which the electrodes are formed on the entire surface, positioned and placed on the semiconductor chip 104, and then cured again. Then, the conductive adhesive 102 is cured, and the semiconductor chip 104 and the second substrate 105 are bonded. Then, a gap formed between the semiconductor chips 104 by dicing is filled with a translucent sealing resin 106 to seal the periphery of the semiconductor chip 104 with resin. Finally, in the dicing process, the first substrate 101, the semiconductor chip 104, and the second substrate 105 having the sandwich structure as described above are cut together for each semiconductor chip 104 by a dicing machine. Therefore, the light-transmitting sealing resin 106 sealed with resin can be left on the side surface of the semiconductor chip 104, and the chip-type semiconductor in which the periphery of the semiconductor chip 104 is surrounded by the light-transmitting sealing resin 106 is completed.
[0005]
[Patent Document 1]
JP-A-10-229097 [0006]
[Problems to be solved by the invention]
However, in the conventional configuration, since the conductive adhesive 102 is used for the electrical connection between the first substrate 101 and the second substrate 105 and the semiconductor wafer 103, the step of applying the conductive adhesive 102, A curing step is required. Therefore, the process becomes complicated. Further, since the conductive adhesive 102 is used, there is a problem that air bubbles enter between the first and second substrates and the semiconductor wafer 103 to cause poor conduction.
[0007]
The present invention solves the above-described conventional problems, and an object thereof is to provide a semiconductor chip that can be manufactured at a wafer level without using the conductive adhesive 102.
[0008]
[Means for Solving the Problems]
In order to solve the conventional problems, a method of manufacturing a semiconductor device according to the present invention includes a first electrode forming step in which a first metal layer is plated on a first main surface of a semiconductor wafer to form an electrode; A bump forming step for forming bumps on the second main surface of the semiconductor element formed on the semiconductor wafer, and then groove formation for dicing the semiconductor wafer into individual semiconductor elements, leaving the first metal layer. A second electrode forming step in which the bump and the second metal layer are thermocompression-bonded to form an electrode, a resin filling step in which the groove is filled with a sealing resin, and then the first A dicing step of dicing the sealing resin between the one metal layer and the semiconductor element and the second metal layer into individual pieces of the semiconductor element at a time, and each of the bump surface and the substrate surface With gold plating and sealing resin on the substrate Those having a through hole used for input.

[0009]
With this configuration, it is possible to manufacture a semiconductor device at the wafer level without using a conductive adhesive, and it is possible to reduce the process by forming external electrodes by plating technology, and by incorporating the bubbles of the conductive adhesive, Conduction failure can be eliminated.
[0010]
DETAILED DESCRIPTION OF THE INVENTION
Embodiments of the present invention will be described below with reference to the drawings.
[0011]
(Embodiment)
1A to 1F show a method for manufacturing a semiconductor device according to an embodiment of the present invention. 1A to 1F, the same components as those in FIG.
[0012]
1A to 1F, 1 is a semiconductor wafer, 2 is a first metal layer formed by electrolytic plating on a base electrode provided on one surface of the wafer, and 3 is constructed on a semiconductor wafer. Plating bumps formed on the electrodes of the device, 4 is a semiconductor element in which the device is constructed, 5 is a groove formed by dicing the semiconductor wafer into chips, and 6 is bump plating formed on the semiconductor wafer. A second metal layer that becomes an external electrode by thermocompression bonding, 7 fills a groove formed by dicing, encapsulating resin surrounding the outer periphery of the chip, and 8 a seal provided on the second metal layer 6 It is a through-hole for filling a stop resin.
[0013]
(Configuration of the embodiment)
A detailed configuration will be described below.
[0014]
A first metal layer 2 such as copper is formed by electrolytic plating on a base electrode (not shown) provided on the first main surface of the semiconductor wafer 1 (FIG. 1A). According to this, there is no need to use a conductive adhesive when forming the metal layer 2 on the semiconductor wafer 1, there is no entrapment of bubbles generated when the conductive adhesive is used, and the semiconductor wafer 1 and This prevents poor conduction with the metal layer 2. Since this metal layer 2 directly serves as an external electrode (not shown) of the semiconductor chip component, it needs a certain thickness, and needs to be about 40 μm in consideration of the dicing process.
[0015]
Bumps 3 are formed on the device electrodes formed on the semiconductor wafer 1 by plating a metal such as copper. The bump 3 is subjected to Au / Ni plating (not shown) on the surface for thermocompression bonding with the second metal layer 6 (FIG. 1B) .
[0016]
The semiconductor wafer 1 is diced into individual semiconductor elements 4. At this time, the individual semiconductor elements 4 are diced and grooves 5 for filling the sealing resin 7 are formed (FIG. 1C).
[0017]
As the bump 3 and the second metal layer 6, for example, a metal plate having nickel plated on the surface of copper and subjected to gold plating is thermocompression bonded (FIG. 1D). At this time, by applying a heat of about 200 ° C. and a load of about 150 to 200 g per bump and thermocompression bonding, the gold applied to the bump 3 and the gold applied to the metal layer 6 are combined and firmly bonded. Is. In addition, a through hole 8 for injecting the sealing resin 7 is provided at the center of the second metal layer 6 to be crimped at this time (FIG. 1D).
[0018]
By injecting the sealing resin 7 from the through-hole 8 provided in the second metal layer 6, the groove 5 is filled with the sealing resin 7, and the sealing resin 7 is placed around the semiconductor element 4. Fill. After filling, the sealing resin 7 is cured and cured. If the through hole 8 is a 4-inch wafer, about 1 mm is required (FIG. 1 (e)).
[0019]
The first metal layer 2, the sealing resin 7, and the second metal layer 6, which have a sandwich structure through the above steps, are divided into individual semiconductor element 4 dimensions by dicing (FIG. 1). (F)). At this time, dicing may be performed at once in a state where the first metal layer 2 and the second metal layer 6 and the sealing resin 7 are combined. Further, dicing may be performed using a dicing blade suitable for each of the metal and the resin. Furthermore, the semiconductor element 4 and the scribe lane can be aligned by the through hole 8 for resin injection during dicing.
[0020]
According to such a configuration, one electrode of the semiconductor wafer 1 is formed by plating, a plating bump is formed on the other side, and an electrode is formed by thermocompression bonding with a metal plate, thereby using a conductive adhesive. Without any problem, a chip type semiconductor device having the periphery surrounded by the sealing resin 7 for protecting the chip element can be manufactured at the wafer level.
[0021]
In this embodiment, a metal layer is provided as an external electrode. However, a metal wiring may be provided on a substrate such as a glass-epoxy substrate and nickel may be plated on the surface thereof. Further, the bumps 3 provided on the electrodes of the device constructed on the semiconductor wafer 1 are not limited to plating bumps, and it is possible to perform thermocompression bonding with a metal layer by providing a stat bump such as gold.
[0022]
Moreover, although it demonstrated using dicing when dividing | segmenting into each semiconductor element, it is not limited to this method.
[0023]
【The invention's effect】
As described above, according to the manufacturing process of the chip type semiconductor device of the present invention, by forming the external electrode by plating, the process of applying and curing the conductive adhesive can be reduced, and the plating bump and the metal plate can be attached to the wafer. By performing pressure bonding in units at a time, it is possible to eliminate defects such as entrapment of bubbles, which are caused by reducing the number of processes and using a conductive adhesive or the like.
[Brief description of the drawings]
FIG. 1 is a manufacturing process diagram of a chip-type semiconductor device according to an embodiment of the present invention. FIG. 2 is a manufacturing process diagram of a conventional chip-type semiconductor device.
DESCRIPTION OF SYMBOLS 1 Semiconductor wafer 2 First metal layer 3 Bump 4 Semiconductor element 5 Groove 6 Second metal layer 7 Sealing resin 8 Through hole 101 First substrate 102 Conductive adhesive 103 Semiconductor wafer 104 Semiconductor chip 105 Second Substrate 106 Translucent sealing resin

Claims (3)

半導体ウェハの第一主面に第一の金属層のめっきを施し電極を形成する第一電極形成工程と、次に前記半導体ウェハに形成された半導体素子の第二主面にバンプを形成するバンプ形成工程と、次に前記半導体ウェハを前記第一の金属層を残し個々の半導体素子にダイシングし溝を形成する溝形成工程と、次に前記バンプと第二の金属層とを熱圧着し電極を形成する第二電極形成工程と、次に前記溝に封止用樹脂を充填する樹脂充填工程と、次に前記第一の金属層と半導体素子間の封止樹脂と前記第二の金属層とを一度に半導体素子の個片にダイシングするダイシング工程とを備えたことを特徴とする半導体装置の製造方法。 A first electrode forming step of forming an electrode by plating a first metal layer on the first main surface of the semiconductor wafer; and a bump for forming a bump on the second main surface of the semiconductor element formed on the semiconductor wafer. Forming a groove, then forming a groove by dicing the semiconductor wafer into individual semiconductor elements, leaving the first metal layer, and then thermocompressing the bump and the second metal layer to form an electrode. A second electrode forming step of forming a resin, a resin filling step of filling the groove with a sealing resin, a sealing resin between the first metal layer and the semiconductor element, and the second metal layer And a dicing step of dicing the semiconductor element into individual pieces at once. 前記バンプ表面と前記基板表面の個々に金めっきを備えたことを特徴とする請求項1記載の半導体装置の製造方法。  The method of manufacturing a semiconductor device according to claim 1, wherein the bump surface and the substrate surface are individually provided with gold plating. 前記基板に封止用樹脂の注入に用いる貫通孔を備えたことを特徴とする請求項1または請求項2記載の半導体装置の製造方法。  3. The method of manufacturing a semiconductor device according to claim 1, wherein the substrate is provided with a through hole used for injecting a sealing resin.
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