JP4081350B2 - メモリのためのアドレス構成を生成する方法 - Google Patents

メモリのためのアドレス構成を生成する方法 Download PDF

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Publication number
JP4081350B2
JP4081350B2 JP2002323686A JP2002323686A JP4081350B2 JP 4081350 B2 JP4081350 B2 JP 4081350B2 JP 2002323686 A JP2002323686 A JP 2002323686A JP 2002323686 A JP2002323686 A JP 2002323686A JP 4081350 B2 JP4081350 B2 JP 4081350B2
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JP
Japan
Prior art keywords
address
lines
memory
sequence
column
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Expired - Fee Related
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JP2002323686A
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English (en)
Japanese (ja)
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JP2003187589A (ja
JP2003187589A5 (enExample
Inventor
ジョシュ・エヌ・ホーガン
ロン・エム・ロス
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HP Inc
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Hewlett Packard Co
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Publication of JP2003187589A publication Critical patent/JP2003187589A/ja
Publication of JP2003187589A5 publication Critical patent/JP2003187589A5/ja
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/10—Decoders
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/12—Group selection circuits, e.g. for memory block selection, chip selection, array selection

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • For Increasing The Reliability Of Semiconductor Memories (AREA)
  • Read Only Memory (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Static Random-Access Memory (AREA)
JP2002323686A 2001-11-13 2002-11-07 メモリのためのアドレス構成を生成する方法 Expired - Fee Related JP4081350B2 (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/990,924 US6466512B1 (en) 2001-11-13 2001-11-13 Method of generating address configurations for solid state memory
US09/990,924 2001-11-13

Publications (3)

Publication Number Publication Date
JP2003187589A JP2003187589A (ja) 2003-07-04
JP2003187589A5 JP2003187589A5 (enExample) 2005-08-04
JP4081350B2 true JP4081350B2 (ja) 2008-04-23

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ID=25536657

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2002323686A Expired - Fee Related JP4081350B2 (ja) 2001-11-13 2002-11-07 メモリのためのアドレス構成を生成する方法

Country Status (6)

Country Link
US (1) US6466512B1 (enExample)
EP (1) EP1310960A3 (enExample)
JP (1) JP4081350B2 (enExample)
KR (1) KR20030040101A (enExample)
CN (1) CN100380518C (enExample)
TW (1) TW580711B (enExample)

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6535455B1 (en) * 2001-10-13 2003-03-18 Hewlett-Packard Company Fault-tolerant neighborhood-disjoint address logic for solid state memory
US7003713B2 (en) * 2002-05-16 2006-02-21 Broadcom Corporation Variable Hamming error correction for a one-time-programmable-ROM
US7191380B2 (en) * 2003-09-10 2007-03-13 Hewlett-Packard Development Company, L.P. Defect-tolerant and fault-tolerant circuit interconnections
US7350132B2 (en) * 2003-09-10 2008-03-25 Hewlett-Packard Development Company, L.P. Nanoscale interconnection interface
US7307345B2 (en) * 2005-11-01 2007-12-11 Hewlett-Packard Development Company, L.P. Crossbar-array designs and wire addressing methods that tolerate misalignment of electrical components at wire overlap points
US7495942B2 (en) * 2004-08-13 2009-02-24 University Of Florida Research Foundation, Inc. Nanoscale content-addressable memory
US7489583B2 (en) * 2005-09-06 2009-02-10 Hewlett-Packard Development Company, L.P. Constant-weight-code-based addressing of nanoscale and mixed microscale/nanoscale arrays
US7319416B2 (en) * 2006-01-30 2008-01-15 Hewlett-Packard Development Company, L.P. Tunneling-resistor-junction-based microscale/nanoscale demultiplexer arrays
US7763978B2 (en) * 2007-03-28 2010-07-27 Hewlett-Packard Development Company, L.P. Three-dimensional crossbar array systems and methods for writing information to and reading information stored in three-dimensional crossbar array junctions
US7630246B2 (en) * 2007-06-18 2009-12-08 Micron Technology, Inc. Programming rate identification and control in a solid state memory
KR100892673B1 (ko) 2007-09-05 2009-04-15 주식회사 하이닉스반도체 어드레스 치환 회로 및 이를 포함하는 반도체 메모리 장치
KR100956946B1 (ko) * 2008-04-16 2010-05-11 매그나칩 반도체 유한회사 비휘발성 메모리 장치의 쓰기방법
KR100971654B1 (ko) * 2008-06-25 2010-07-22 (주)아이엘전자 플럭스 유입 방지 택트 스위치

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4064558A (en) * 1976-10-22 1977-12-20 General Electric Company Method and apparatus for randomizing memory site usage
US4092665A (en) * 1976-12-29 1978-05-30 Xerox Corporation Method and means for extracting variable length data from fixed length bytes
US4556960A (en) * 1982-12-13 1985-12-03 Sperry Corporation Address sequencer for overwrite avoidance
US4782340A (en) * 1986-08-22 1988-11-01 Energy Conversion Devices, Inc. Electronic arrays having thin film line drivers
US5550782A (en) * 1991-09-03 1996-08-27 Altera Corporation Programmable logic array integrated circuits
JPH0696598A (ja) * 1992-07-10 1994-04-08 Texas Instr Japan Ltd 半導体メモリ装置及び欠陥メモリセル救済回路
US5721498A (en) * 1995-12-11 1998-02-24 Hewlett Packard Company Block segmentation of configuration lines for fault tolerant programmable logic device
US6172933B1 (en) * 1998-09-04 2001-01-09 Intel Corporation Redundant form address decoder for memory system
KR100326268B1 (ko) * 1998-10-28 2002-05-09 박종섭 디코딩시의동작마진확보를위한디코딩장치및그방법
JP2000285694A (ja) * 1999-03-30 2000-10-13 Mitsubishi Electric Corp 半導体記憶装置および半導体記憶装置を搭載する半導体集積回路装置
US6088287A (en) * 1999-08-23 2000-07-11 Advanced Micro Devices, Inc. Flash memory architecture employing three layer metal interconnect for word line decoding
US6459648B1 (en) * 2001-10-13 2002-10-01 Josh N. Hogan Fault-tolerant address logic for solid state memory

Also Published As

Publication number Publication date
KR20030040101A (ko) 2003-05-22
EP1310960A2 (en) 2003-05-14
TW200300261A (en) 2003-05-16
CN1419240A (zh) 2003-05-21
JP2003187589A (ja) 2003-07-04
EP1310960A3 (en) 2005-01-12
CN100380518C (zh) 2008-04-09
US6466512B1 (en) 2002-10-15
TW580711B (en) 2004-03-21

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