JP4076724B2 - ダイナミック半二重によるループ・フェアネスの保持 - Google Patents

ダイナミック半二重によるループ・フェアネスの保持 Download PDF

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Publication number
JP4076724B2
JP4076724B2 JP2000532850A JP2000532850A JP4076724B2 JP 4076724 B2 JP4076724 B2 JP 4076724B2 JP 2000532850 A JP2000532850 A JP 2000532850A JP 2000532850 A JP2000532850 A JP 2000532850A JP 4076724 B2 JP4076724 B2 JP 4076724B2
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loop
port
data
channel
predetermined amount
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Japanese (ja)
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JP2002504765A5 (enExample
JP2002504765A (ja
Inventor
ミラー、マイケル、エイチ
ウエストビイ、ジュディ、リン
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Seagate Technology LLC
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Seagate Technology LLC
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/54—Store-and-forward switching systems 
    • H04L12/56—Packet switching systems
    • H04L12/5601—Transfer mode dependent, e.g. ATM
    • H04L12/5602—Bandwidth control in ATM Networks, e.g. leaky bucket
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
    • H04L12/42—Loop networks
    • H04L12/427—Loop networks with decentralised control
    • H04L12/433—Loop networks with decentralised control with asynchronous transmission, e.g. token ring, register insertion

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  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Small-Scale Networks (AREA)
  • Information Transfer Systems (AREA)
  • Computer And Data Communications (AREA)
JP2000532850A 1998-02-24 1999-02-24 ダイナミック半二重によるループ・フェアネスの保持 Expired - Fee Related JP4076724B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US7579798P 1998-02-24 1998-02-24
US60/075,797 1998-02-24
PCT/US1999/003955 WO1999043002A2 (en) 1998-02-24 1999-02-24 Preserving loop fairness with dynamic half-duplex

Publications (3)

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JP2002504765A JP2002504765A (ja) 2002-02-12
JP2002504765A5 JP2002504765A5 (enExample) 2005-12-22
JP4076724B2 true JP4076724B2 (ja) 2008-04-16

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JP2000532850A Expired - Fee Related JP4076724B2 (ja) 1998-02-24 1999-02-24 ダイナミック半二重によるループ・フェアネスの保持

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US (2) US6061360A (enExample)
JP (1) JP4076724B2 (enExample)
KR (1) KR100607392B1 (enExample)
CN (1) CN1309849A (enExample)
DE (1) DE19982971T1 (enExample)
GB (1) GB2349319B (enExample)
WO (1) WO1999043002A2 (enExample)

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Also Published As

Publication number Publication date
CN1309849A (zh) 2001-08-22
US6553036B1 (en) 2003-04-22
KR20010086257A (ko) 2001-09-10
US6061360A (en) 2000-05-09
KR100607392B1 (ko) 2006-08-02
WO1999043002A3 (en) 1999-10-28
GB2349319A (en) 2000-10-25
GB0018845D0 (en) 2000-09-20
WO1999043002A2 (en) 1999-08-26
JP2002504765A (ja) 2002-02-12
DE19982971T1 (de) 2001-02-15
GB2349319B (en) 2003-05-28

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