JP4061329B2 - Game machine control device - Google Patents

Description

The present invention relates to a gaming machine control device, and more particularly to a gaming machine control device such as a pachinko gaming machine or a slot machine.

A gaming machine has a large number of control boards, and each control board constitutes a part of a control device that controls various operations of the gaming machine. Various signals are input to CPUs (Central Processing Units) on various boards that execute the electrical control. Due to the unusual usage environment of gaming machines (such as metal gaming balls, the use of gaming medals, high-level noise, signal lines straddling the board, etc.), noise that is not a regular signal is input to the CPU terminal. It often happens. As a countermeasure against such noise, a circuit for removing noise may be provided immediately before various input terminals. In addition, the gaming machine as a whole has measures such as improving the insulation around the control device so that it is not affected by noise by devising the spatial arrangement of the board, the control circuit on the board, the elements on the board, etc. It has been subjected. However, it is impossible to physically isolate the board or device from the noise, and it is difficult to predict what causes the noise. Is not enough. Furthermore, when a circuit for removing noise is provided immediately before the CPU, there is a possibility that the circuit itself may be a place where a signal derived from noise is generated.

In a conventional gaming machine control device, when a CPU on various boards detects a reset signal, the RAM (Random Access Memory) is initialized (cleared) and a restart operation is performed (cold start) or the RAM is simplified. If there is no problem after checking, the stored state is maintained and the continuous operation is executed as it is (hot start), either of which is selected and determined according to the use of various boards and the type of gaming machine . In this circuit configuration, there is no guarantee that the reset signal detected by the CPU is a normal reset signal issued from various boards, and the CPU may recognize a signal such as noise as the same reset signal and cold start. There is. However, when the CPU is cold-started by a signal such as noise, the RAM is initialized, so the gaming machine must take a form of interrupting the operation, which may cause inconvenience to the player. That is, in a CPU that controls a general device, even if a malfunction or runaway of the CPU occurs, there is a case where it is only necessary to perform a normal recovery by resetting and performing a cold start. Of course, in a gaming machine, it is possible to restore the gaming machine to a normal operating state by resetting the CPU and performing a cold start. However, the gaming machine may reset the CPU and perform a cold start. There are circumstances that are undesirable. Specifically, on various boards of gaming machines, information such as lottery information and payout information is stored on the RAM, and information on the game on the RAM is initialized (cleared) and the CPU is cold-started. Then, there is a problem that information in the game on the RAM is lost and the game is restarted from the beginning, which may cause trouble in the game and significantly reduce the interest of the player. There was also a problem that in some cases it could be a compensation issue.

Therefore, the inventor of the present application has already proposed a technique relating to a hot / cold determination circuit that determines whether to start the CPU hot or cold when a signal is input to the reset terminal of the CPU (see Patent Document 1). By adopting this technology, when a signal is input to the reset terminal of the CPU, it is determined whether the signal is a normal reset signal or a signal such as noise, and only when a normal reset signal is input The RAM is initialized (cleared) and the CPU is cold-started. When other signals such as noise are input, the CPU can be hot-started without initializing (clearing) the RAM.

However, in the conventional gaming machine control device, even if the hot / cold determination circuit is adopted, the RAM check used for the hot / cold determination only performs a partial simple check due to time constraints and the like. If a reset occurs due to timing such as during RAM rewriting, the CPU will malfunction or run away, and the input signal from the hot / cold determination circuit will always indicate a hot start, and the software will be in a loop state. There was a possibility of falling into. That is, there is a problem that even if it is determined as a hot start, the CPU may malfunction or run away, and the possibility that the software is in a loop state cannot be completely eliminated.

In order to solve the problem when such a hot / cold determination circuit is adopted, the CPU incorporates a watchdog timer function or a reset integrated circuit (hereinafter referred to as a WDT built-in reset IC) incorporating the watchdog timer function. (Abbreviated as “Integrated Circuit”), and a configuration in which a malfunction or runaway of the CPU is detected by a watchdog timer function can be employed. The watchdog timer function interrupts the software in the CPU every predetermined time and is always reset by a release pulse from the CPU in a normal state. However, in the case of a malfunction or runaway of the CPU, the release pulse from the CPU Is not output and the watchdog timer function resets the CPU.
Japanese Patent No. 3756403

However, as described above, there is a demand for the gaming machine to prevent the CPU from executing a cold start where the information on the game in the RAM is initialized as much as possible, and the CPU has a built-in watchdog timer function or WDT. Even when a built-in reset IC is connected, the CPU must be hot-started as much as possible. For this purpose, a normal reset signal from various substrates is made into a signal having a long pulse width of several tens of milliseconds (ms) so that it is detected by a hot / cold determination circuit and the CPU is cold-started, while a built-in reset of WDT By making the reset signal from the IC a signal having a short pulse width of several microseconds (μm) equivalent to noise, the CPU can be hot-started without being detected by the hot / cold determination circuit.

However, in the conventional gaming machine control device, when the reset IC from the WDT built-in reset IC is connected to the CPU to which the hot / cold determination circuit is connected, the reset signal from the WDT built-in reset IC is reset to the hot start. Even if it is a signal, if the CPU cannot output a release pulse in the event of malfunction or runaway, the WDT built-in reset IC repeatedly outputs a short pulse width hot start reset signal, so the hot start is repeated. Therefore, there is a problem in that it is impossible to cold start by exiting the loop state at the judgment of the CPU itself.

In view of such circumstances, an object of the present invention is to provide a counter that counts the number of times of hot start, and allows a cold start by exiting a loop state in which the hot start is repeated at the judgment of the CPU itself. It is to provide a control device.

Means for Solving the Problems and Effects of the Invention

Therefore, the gaming machine control device of the present invention is
A reset circuit that is connected to a CPU that controls the operation of the gaming machine, and that has a watchdog timer function that outputs a reset signal for hot start every predetermined clock monitoring time unless a release pulse is input from the CPU ;
Logically sums a cold start reset signal output from various boards such as a power monitoring board and / or noise that can hot start the CPU and a hot start reset signal output from the reset circuit, and an output terminal OR circuit connected to the reset terminal of the CPU,
A signal identification circuit that is connected to the output terminal of the OR circuit in the previous stage of the CPU and identifies whether the input signal from the OR circuit to the reset terminal is the cold start reset signal, the noise, or the hot start reset signal When,
When it is a signal input to the reset terminal, and determines a start determination means for determining to cold start the CPU or hot start the CPU on the basis of a hot / cold determination signal from the signal discrimination circuit,
A counter which is counted up when it is determined that the hot start the CPU by the start determination means,
Even if it is determined that the CPU is to be hot-started by the start determination unit, an activation unit that cold-starts the CPU when the count value of the counter becomes equal to or greater than a preset value within a predetermined time ;
It is characterized by providing.
In addition, the gaming machine control device of the present invention,
A game in which a CPU that controls the operation of a gaming machine has a built-in watchdog timer function, and resets the CPU every predetermined clock monitoring time unless the watchdog timer function releases the CPU. In the machine control device,
A signal identification circuit that is connected to the previous stage of the CPU and identifies whether the input signal to the reset terminal is a cold start reset signal output from various boards such as a power monitoring board or noise that can hot start the CPU When,
Start determination means for determining whether to hot start the CPU or cold start the CPU based on an input signal from the signal identification circuit when the CPU is reset;
A counter that is counted up when it is determined by the start determination means that the CPU is hot-started;
Even if it is determined that the CPU is to be hot-started by the start determination unit, an activation unit that cold-starts the CPU when the count value of the counter becomes equal to or greater than a preset value within a predetermined time;
It is characterized by providing.
According to these gaming machine control devices, even when it is determined that the CPU is hot-started, when the count value of the counter that counts the number of hot-starts exceeds a preset value within a certain period of time Since the CPU is cold-started, even if the software goes into a loop state due to a malfunction or runaway of the CPU, the count value of the counter exceeds the preset value within a certain time, so the loop state is exited. Can be cold started. In other words, in a gaming machine, there is a request that the CPU should not be cold started unless there is a problem, so the CPU does not cold start only by receiving a reset signal (including noise) once or twice. However, when a reset signal (including noise) is received a predetermined number of times within a predetermined time, the CPU also gives up to hot start and cold starts the CPU. With such a mechanism, the CPU is cold-started even when it receives noise more than a predetermined number of times within a predetermined time, but since this is a sufficiently abnormal state, it is rather desirable to cold-start the CPU. . If various boards such as a power supply control board need to detect a true power supply drop (designed to ignore instantaneous power outages at noise levels), etc., and reset the system (cold start), etc. In order to output a cold start reset signal having a pulse width, the CPU cold starts.

The said counter means of the game machine control device, when the predetermined time after the hot start of the CPU has passed successfully, or the CPU can be reset the count value when a cold start. According to this gaming machine control device, the count value is reset when a predetermined time has elapsed normally after the hot start of the CPU or when the CPU is cold started, so that it is possible to avoid cold start periodically. it can.

The activation means of the game machine control device, even when it is determined that hot start the CPU by the start determination means, followed by checking the RAM of the CPU checks the result of the RAM is not normal Thus, the CPU can be cold started . According to this gaming machine control device, since it is dangerous to hot start the CPU when the RAM is abnormal, it is possible to prevent malfunction and runaway due to hot start of the CPU by cold starting the CPU.

The external signal of the gaming machine control device may be an output signal from a signal identification circuit that identifies whether the input signal to the reset terminal of the CPU is a cold start reset signal or another signal . According to this gaming machine control device, since the input signal to the CPU reset terminal is determined based on the output signal from the signal identification circuit, it is determined whether the input signal is a cold start reset signal or any other signal. In the case of a cold start reset signal, a cold start is performed, and when the input signal is a hot start reset signal or noise, the CPU can be hot started.

The external signal of the gaming machine control device may be an output signal from a power supply monitoring circuit that determines whether the RAM of the CPU is electrically usable based on a power supply voltage . According to this gaming machine control device, since it is determined whether the RAM of the CPU is electrically usable based on an output signal from the power supply monitoring circuit, the power supply voltage is out of a predetermined voltage range. Since the RAM cannot be used electrically, the CPU can be cold-started, and when the power supply voltage is within a predetermined voltage range, the RAM can be used electrically and the CPU can be hot-started.

Further, the CPU RAM can be electrically used based on a power supply voltage and a signal identification circuit for identifying whether the external signal is an input signal to the reset terminal of the CPU or a cold start reset signal. If the output signal from the hot / cold determination circuit is a power monitoring circuit that determines whether the CPU is hot-started or cold-started based on the output signal from the hot / cold determination circuit When the hot / cold determination circuit instructs hot start, the CPU is hot-started. When the hot / cold determination circuit instructs cold start, the CPU is cold-started. Can do.

When the CPU is determined to hot start, the counter is counted up and the CPU is determined to hot start when the CPU is malfunctioning or running out of control. This is realized by cold-starting the CPU when the count value exceeds a preset value within a certain time.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

Although the gaming machine control device is composed of a large number of control boards having different roles, the respective boards are not distinguished in this specification. This is because the present invention can be applied to any of the CPUs on these substrates. Since elements and circuits around the CPU not shown in the figure are the same as in the past, they are omitted.

FIG. 1 is a circuit block diagram showing the configuration of the gaming machine control device according to the first embodiment of the present invention. The gaming machine control device according to the first embodiment includes a CPU 100, a WDT built-in reset IC 200 connected to the CPU 100, a hot / cold determination circuit 300 connected to the previous stage of the CPU 100, and a power source that monitors the power supply of the gaming machine in general. An OR circuit 400 that ORs a reset signal (including noise) output from various boards such as a monitoring board and a reset signal output from the WDT built-in reset IC 200 constitutes a main part. The reset signal output from various boards such as the power monitoring board has a long pulse width of several tens of milliseconds so that the signal identification circuit 310 can detect it, while the reset signal output from the WDT built-in reset IC 200 is The short pulse width of about several microseconds (μs), which is the same level as the noise, is set so as not to be detected by the signal identification circuit 310. Hereinafter, a reset signal output from various boards such as a power supply monitoring board is referred to as a cold start reset signal, and a reset signal output from a WDT built-in reset IC is referred to as a hot start reset signal to distinguish between the two.

The CPU 100 includes a register group 110, a ROM 120, and a RAM 130, and includes a power supply terminal Vcc, an input port H / C, an output port P1, and a reset terminal RESET. A power supply voltage Vcc (same as the power supply terminal) is applied to the power supply terminal Vcc. The input port H / C is connected to the hot / cold determination circuit 300. The output port P1 is connected to the WDT built-in reset IC 200. The reset terminal RESET is connected to the output terminal of the OR circuit 400. In the first embodiment, the CPU 100 in which the ROM 120 and the RAM 130 are built is used. However, the CPU 100, the ROM 120, and the RAM 130 need not be packaged together.

Referring to FIG. 2, the register group 110 includes various registers R1 to Rn such as a data register, an address register, and a status register. The ROM 120 stores various programs for controlling the gaming machine control device. In particular, a main program 121 that periodically outputs a release pulse from the output port P1 of the CPU 100 to the WDT built-in reset IC 200, and at the time of resetting. A reset processing routine 122 to be started is stored. Further, the RAM 130 is provided with a counter 131 that counts up when it is determined to hot start the CPU 100 based on a hot / cold determination signal that is an external signal and a RAM check result. Furthermore, a specific RAM check data value (for example, hexadecimal “AA55”) is set to a specific address (for example, a head address, an intermediate address, a tail address, etc.) of the RAM 130. A specific RAM check data value is set in the RAM 130 at a cold start, and is used to check whether the data value on the RAM 130 is correct at the RAM check time. Therefore, the RAM check here is a simple check performed by verifying whether the data value of the specific address in the RAM 130 matches the specific data value for RAM check in order to shorten the check time. It is hard to expect completeness. However, as the specific address of the RAM 130, an address that is not normally accessed by various programs in the ROM 120 is selected, and the accuracy of the RAM check is high.

FIG. 3 is a flowchart showing reset processing by the reset processing routine 122. The reset processing routine 122 starts a continuous operation without clearing (initializing) the RAM 130 during a hot start, and starts a restart operation by clearing (initializing) the RAM 130 during a cold start. It has a software structure. Further, even if it is determined that the CPU 100 is hot-started based on an external signal, the software structure is such that the CPU 100 is cold-started if a RAM check is executed after the determination and the result is not normal. Further, a counter 131 that counts up when it is determined to hot start the CPU 100 based on a hot / cold determination signal that is an external signal and a RAM check result is provided. The software structure is such that the CPU 100 is cold-started when the count value of the counter 131 exceeds a preset value within a predetermined time. Step S102 in FIG. 3 constitutes start determination means of the present invention, step S103 constitutes RAM check means of the present invention, steps S104 to S105 constitute counter means, and steps S106 to S111 constitute activation means of the present invention.

Even in the hot start when the hot / cold determination circuit 300 is used, the risk of malfunction or runaway of the CPU 100 cannot be completely eliminated. This is because the RAM check used for the hot / cold determination cannot check all the RAMs 130 but only a partial check. Specifically, it is verified whether or not the data value stored at the specific address of the RAM 130 matches the data value for RAM check (for example, hexadecimal “AA55”). If they match, the RAM check is normal (OK). If there is a match, the RAM check is abnormal (NG). Since the matching verification between the data value stored at the specific address and the data value for RAM check is a partial checking method, there is a possibility that even if the RAM 130 is abnormal, it is determined that the matching verification is normal. is there. If reset due to noise occurs at a timing such as during rewriting of the RAM 130, the CPU 100 will malfunction or run away. In order to avoid this danger, a WDT built-in reset IC 200 having a watchdog timer function for resetting the CPU 100 when the CPU 100 enters a malfunction or a runaway state is used. By using this, software having a mechanism that surely cold-starts when the CPU 100 malfunctions or runs away is constructed. Specifically, as shown in the flowchart of FIG. 3, a timer that counts up at the time of hot start is provided, and if the normal operation can be performed for a predetermined time after that, the timer is cleared, and this is determined in advance within the predetermined time. This is software that cold-starts the CPU 100 when the count value is exceeded. This is a case where the CPU 100 does not improve even if the CPU 100 falls into a malfunction or runaway state and is hot-started, and this state can be detected by adopting this configuration. That is, it is possible to avoid malfunctions and runaway of the CPU 100 during hot start.

The RAM 130 cannot hold the stored data when the power supply voltage Vcc falls below a predetermined threshold. If the reset signal is input to the CPU 100 when the power supply voltage Vcc drops below a predetermined threshold or the CPU 100 may not operate normally, the CPU 100 causes the data on the RAM 130 to be electrically It is judged whether it is held in or not. Conventionally, whether the hot start or the cold start is set based on the reset of the CPU 100 is programmed in advance. In the present invention, the hot start or the cold start is provided separately from the reset terminal RESET. The hot / cold determination signal that is the input state of the input port H / C for determining whether or not the RAM 130 is to be detected is selected, and whether or not the RAM 130 is all cleared (initialized) is selected based on the detection result Execute.

The WDT built-in reset IC 200 has a built-in WDT function (not shown), and generates and outputs a hot start reset signal every predetermined clock monitoring time unless a release pulse is input from the CPU 100. Specifically, if the main program 121 of the CPU 100 is operating normally, the position (point) through which the main program 121 passes within a predetermined time is known in advance, so a release pulse to the reset IC 200 with built-in WDT is issued at such position (point). It is programmed to output from the output port P1. If the WDT function cannot be reset even if a predetermined time (clock monitoring time) elapses due to a malfunction or runaway of the CPU 100, the WDT function timer overflows, so the WDT built-in reset IC 200 outputs a hot start reset signal. The CPU 100 is reset by outputting to the reset terminal RESET of the CPU 100 via the circuit 400.

The hot / cold determination circuit 300 has two functions. If the circuit is divided into two parts, one of the input signals is a cold start reset signal having a long pulse width or a short pulse. A signal identification circuit 310 for identifying whether the width is a hot start reset signal or noise, and the other can be a power supply monitoring circuit 320 for determining whether the RAM 130 is electrically usable.

The signal identification circuit 310 detects the input of a cold start reset signal when the reset terminal RESET of the CPU 100 is at a low level (hereinafter abbreviated as L level). That is, the L level is an active level as a signal. However, depending on the terminal, the high level (hereinafter abbreviated as H level) may be the active level.

When the power supply voltage Vcc is equal to or lower than a predetermined threshold, for example, the voltage at which the RAM 130 is not electrically guaranteed, the power supply monitoring circuit 320 sends a hot / cold determination signal reflecting the change to the CPU 100. .

FIG. 4A is a diagram illustrating a specific circuit example of the hot / cold determination circuit 300. The hot / cold determination circuit 300 includes a signal identification circuit 310 including the inverter Schmitt trigger circuit 10, a resistor 11, and a capacitor 12, and a power supply monitoring circuit 320 including the resistor 11, the capacitor 12, and the diode 13. The CR time constant circuit portion composed of the capacitor 12 is integrated into one circuit as a common one. FIG. 4B shows essential parts of the signal identification circuit 310 and the voltage monitoring circuit 320 extracted from FIG. 4A and described in detail. FIG. 4B shows a complementary metal oxide semiconductor (CMOS) inverter 10 a, which is actually a part of the inverter Schmitt trigger circuit 10. A charging path for the capacitor 12 in the power supply monitoring circuit 320 is secured in a conduction path on the pMOS side in the CMOS inverter 10a. In FIGS. 4A and 4B, the hot start reset signal and noise are basically eliminated by the configuration of the CR time constant circuit and the CMOS inverter 10a. However, the timer IC, the low-pass filter, and the bipolar are used. The hot / cold determination circuit 300 may be configured by applying a transistor or the like.

The CMOS inverter 10a conducts the nMOS to output the GND level when the input potential is at the power supply voltage Vcc level applied to the source of the pMOS, and conducts the pMOS to conduct the power supply voltage Vcc level when the input potential is at the GND level. Is output. Therefore, in a normal time when the cold start reset signal is not input to the signal identification circuit 310 (the reset terminal RESET of the CPU 100 is at the H level), the CMOS inverter 10a has the L level (GND level) once inverted by the inverter Schmitt trigger circuit 10. ) Is input, the power supply voltage Vcc is output. While the power supply voltage Vcc is being output, the capacitor 12 is charged. Since the resistor 11 is inserted, a CR time constant circuit is configured, and the time constant is determined here.

In the OR circuit 400, a cold start reset signal (including noise) is input to one input terminal from various boards such as a power supply monitoring board that monitors the power supply of the gaming machine in general, and the other input terminal from the reset IC 200 with built-in WDT. The hot start reset signal is input. The output terminal of the OR circuit 400 is connected to the input terminal of the hot / cold determination circuit 300 and to the reset terminal RESET of the CPU 100.

Next, the operation of the gaming machine control device according to the first embodiment configured as described above will be described.

For example, a cold start reset signal or noise (L level signal) is input from various boards such as a power supply monitoring board that monitors the power supply of the gaming machine in general, or the WDT built-in reset IC 200 that monitors the operation of the CPU 100 is hot. When a start reset signal is generated, a cold start reset signal, a hot start reset signal, or noise is simultaneously input to the reset terminal RESET and the hot / cold determination circuit 300 of the CPU 100.

Regardless of whether the signal input to the reset terminal RESET of the CPU 100 is a cold start reset signal, a hot start reset signal, or noise, the CPU 100 is reset. As a result, the setting value temporarily stored in the register group 110 of the CPU 100 is volatilized and cleared. Further, the values of the input / output ports including the reset output port Pn of the CPU 100 are undefined.

Next, the CPU 100 sets a program counter at the head address of the reset processing routine 122 and starts executing the reset processing routine 122.

When the execution of the reset processing routine 122 is started, the CPU 100 first performs an initial setting (S101 in FIG. 3). For example, the value of the input / output port and the setting of the port direction register are sequentially performed.

On the other hand, a signal that is input to the reset terminal RESET of the CPU 100 and simultaneously input to the hot / cold determination circuit 300 is input at the H level so as to be inverted once by the inverter Schmitt trigger circuit 10. When an H level signal is input, the CMOS inverter 10a inverts the conduction path and outputs the GND level. Then, the electric charge accumulated in the capacitor 12 until then starts to be discharged to the GND of the CMOS inverter 10a. Up to this point, the same is true whether the input signal is a cold start reset signal, a hot start reset signal, or noise. The hot start reset signal and the L level duration of noise are very short compared to the cold start reset signal. Although it depends on the case, it is almost never less than millisecond, and can hardly last for more than 10 milliseconds. On the other hand, the cold start reset signal can be easily output over several tens of milliseconds.

When the H level duration of the signal input to the CMOS inverter 10a is longer than the time constant of the CR time constant circuit, that is, when it is a cold start reset signal, the capacitor 12 is sufficiently discharged, The signal level determined by the electrode potential is inverted to L level. Accordingly, an L level cold start reset signal (hot / cold determination signal) can be transmitted to the input port H / C of the CPU 100 with the inverter Schmitt trigger circuit 10 for waveform shaping interposed therebetween. That is, the cold start reset signal input to the input port H / C of the CPU 100 via the signal identification circuit 310 is delayed by the time constant of the CR time constant circuit.

When the signal input to the hot / cold determination circuit 300 is a hot start reset signal or noise, the conduction path of the CMOS inverter 10a is switched before the charge of the capacitor 12 is sufficiently discharged. Is resumed. That is, since the electrode potential of the capacitor 12 is maintained at the H level, an L level signal cannot be output to the input port H / C of the CPU 100.

On the other hand, since the power supply voltage Vcc is applied to the capacitor 12, the input signal at the input port H / C determined by the electrode potential of the capacitor 12 is kept at the H level unless there is an abnormality such as a drop in the power supply voltage Vcc. Be drunk. However, when the power supply voltage Vcc has dropped to 0 V even momentarily, the charge accumulated in the capacitor 12 is discharged instantaneously, for example, by flowing backward through the diode 13 to the power supply unit. Since the electrode potential of the capacitor 12 is immediately switched to the L level, the L level is output accordingly, and the input port H / C of the CPU 100 also changes to the L level. When the power supply voltage Vcc returns to a normal value, the capacitor 12 starts to be charged (exactly, when the electrode potential of the capacitor 12 becomes smaller than the power supply voltage Vcc), but the configuration of the CR time constant circuit sandwiching the resistor 11 Therefore, in order for the electrode potential of the capacitor 12 to change to the H level defined by the threshold of the inverter Schmitt trigger circuit 10, a time longer than a predetermined time constant is required.

That is, when the H level is output from the power supply monitoring circuit 320 and the input port H / C of the CPU 100 becomes the H level, it is after the time when the power supply voltage Vcc is restored. In the meantime, if the CPU 100 detects the input state of the input port H / C, history information as to whether or not the RAM 130 is electrically held can be obtained, and the RAM 130 is initialized based on the result. You can choose whether or not. Further, not only when the power supply voltage Vcc drops momentarily, but also when the CPU 100 starts reset processing when a cold start reset signal, hot start reset signal, or noise is input, processing is performed based on the history. Is effective, and the probability that malfunctions can be avoided is surely improved.

In the input state of the reset terminal RESET and the input port H / C of the CPU 100 when the power supply voltage Vcc drops to 0V and returns to the normal value again, the power supply voltage Vcc is restored, and the CPU 100 starts reset processing and starts the input port. The H / C input state is detected. At this time, the input state of the input port H / C remains at the L level. Thereafter, when a predetermined time elapses, the output of the power supply monitoring circuit 320 changes to the H level. This predetermined time, that is, the time taken for the input state of the input port H / C to change to the H level after the power supply voltage Vcc is restored is meaningless unless it is longer than the time required for restarting the CPU 100. Please be careful. Considering this, a CR time constant circuit is constructed.

Returning to the reset processing of the CPU 100, after the initial setting is completed, the CPU 100 hot-starts the CPU 100 based on the hot / cold determination signal (input port H / C) output from the hot / cold determination circuit 300 or sets the CPU 100. It is determined whether or not to cold start (S102 in FIG. 3). If the input port H / C is at the H level (S102: High in FIG. 3), it is determined that the CPU 100 is hot-started. If the input port H / C is at the L level (S102: Low in FIG. 3), the CPU 100 is Judged to be cold start.

When it is determined that the CPU 100 is hot-started (S104 in FIG. 3: High), the CPU 100 further checks the RAM 130 (S103 in FIG. 3). Specifically, it is verified whether or not the data value stored at the specific address of the RAM 130 matches the data value for RAM check (for example, hexadecimal “AA55”). If they match, the RAM check is normal (OK). If there is a match, the RAM check is abnormal (NG).

When the RAM check is normal (S103 in FIG. 3: OK), the CPU 100 increments the counter 131 by 1 (S104 in FIG. 3), and checks the counter 131 (S105 in FIG. 3). If the value of the counter 131 is less than 10, the CPU 100 performs a hot start. Specifically, the CPU 100 resumes the operation from the position (point) indicated by the program counter at the time of reset held in the RAM 130 without clearing the RAM 130, and continues the operation before the reset (S106 in FIG. 3). After the elapse of time (S107 in FIG. 3), the counter 131 is cleared (S108 in FIG. 3). Although described as “predetermined time”, an actual gaming machine control device can be designed not to have a dedicated timer but to reset the counter each time one symbol change is completed. That is, the “predetermined time” does not have to be a fixed time.

When it is determined that the CPU 100 is cold-started (S104: Low in FIG. 3), the RAM check is abnormal (S104: NG in FIG. 3), or the value of the counter 131 is 10 or more (FIG. 3). (S105: NG), the CPU 100 performs a cold start. Specifically, the CPU 100 clears (initializes) the RAM 130 (S109 in FIG. 3), and performs processing at power-on such as loading various programs and data in the ROM 120 into the RAM 130 (S110 in FIG. 3). When all data in the RAM 130 is cleared, the CPU 100 returns to the initial state. Subsequently, the CPU 100 sets a RAM check data value (for example, hexadecimal “AA55”) as a specific address of the RAM 130 (S111 in FIG. 3). Thereafter, the CPU 100 sets the program counter to the top address of the main program 121 and starts the operation from the initial state.

According to the first embodiment, even when it is determined that the CPU 100 is hot-started, the CPU 100 is cold-started when the count value of the counter becomes a preset value within a predetermined time. Even if the software enters a loop state due to malfunction or runaway of the CPU 100, the count value becomes equal to or greater than a preset value within a predetermined time, so that the CPU 100 can be exited from the loop state and cold-started.

FIG. 5 shows a circuit diagram of a control device for gaming machines according to Embodiment 2 of the present invention. In the gaming machine control device according to the first embodiment shown in FIG. 1, the hot start reset signal is generated using the WDT built-in reset IC 200, but in the gaming machine control device according to the second embodiment, The CPU 100 incorporating the WDT 140 makes the WDT built-in reset IC 200 and the OR circuit 400 unnecessary. Therefore, since the other part is comprised similarly to the control apparatus for game machines which concerns on Example 1, detailed description is omitted.

In the gaming machine control device according to the second embodiment configured as described above, not only when the cold start reset signal (including noise) is input to the reset terminal RESET of the CPU 100, but also from the main program 121. Even when the WDT 140 does not cancel the count value count up and the count value is counted up to a predetermined value, the CPU 100 is reset. However, since the port H / C of the CPU 100 is at the H level at the time of this reset, the determination in step S102 in FIG. Therefore, the reset process of the reset process routine 122 shown in FIG. 3 can be applied to the gaming machine control device according to the second embodiment in exactly the same manner.

Therefore, the gaming machine control device according to the second embodiment can achieve the same effects as the gaming machine control device according to the first embodiment. That is, even if it is determined that the CPU 100 is to be hot-started, the CPU 100 is cold-started when the count value exceeds a preset value within a predetermined time. Even if the CPU enters a loop state, the count value becomes equal to or greater than a preset value within a predetermined time, so that the CPU 100 can be cold-started out of the loop state.

In each of the above embodiments, the circuit for inputting the hot / cold determination signal to the input port H / C of the CPU 100 is the hot / cold determination circuit 300, but either the signal identification circuit 310 or the power supply monitoring circuit 320 is used. Needless to say, it may be.

In each of the above embodiments, the case where the reset terminal RESET of the CPU 100 is L-active has been described as an example. However, it goes without saying that the present invention can be similarly applied even when the reset terminal RESET is H-active.

Further, in each of the embodiments described above, the case where the reset process is started based on the reset signal has been described. However, the reset process is started based on a signal other than the reset signal, such as an interrupt signal or a non-maskable interrupt signal. In this case, it goes without saying that the present invention can be similarly applied.

The embodiments of the present invention have been described above. However, these are merely examples, and the present invention is not limited to them, and the knowledge of those skilled in the art can be used without departing from the spirit of the claims. Various modifications based on this are possible.

The circuit block diagram showing a part of circuit of the gaming machine control device according to the first embodiment of the present invention. The figure which illustrates the contents of the register group of CPU, ROM, and RAM. The flowchart which shows the reset process by a reset process routine. The circuit diagram which shows an example of the hot / cold determination circuit which coexisted the signal identification circuit and the voltage monitoring circuit. The circuit block diagram showing a part of circuit of the gaming machine control device according to the second embodiment of the present invention.

Explanation of symbols

100 CPU
110 Register group 120 ROM
121 Main program 122 Reset processing routine 130 RAM
131 Counter 140 WDT
200 WDT built-in reset IC
300 hot / cold determination circuit 310 signal identification circuit 320 power supply monitoring circuit 400 OR circuit

Claims (4)

A reset circuit that is connected to a CPU that controls the operation of the gaming machine, and that has a watchdog timer function that outputs a reset signal for hot start every predetermined clock monitoring time unless a release pulse is input from the CPU ;
Logically sums a cold start reset signal output from various boards such as a power monitoring board and / or noise that can hot start the CPU and a hot start reset signal output from the reset circuit, and an output terminal OR circuit connected to the reset terminal of the CPU,
A signal identification circuit that is connected to the output terminal of the OR circuit in the previous stage of the CPU and identifies whether the input signal from the OR circuit to the reset terminal is the cold start reset signal, the noise, or the hot start reset signal When,
When it is a signal input to the reset terminal, and determines a start determination means for determining to cold start the CPU or hot start the CPU on the basis of a hot / cold determination signal from the signal discrimination circuit,
A counter which is counted up when it is determined that the hot start the CPU by the start determination means,
Even if it is determined that the CPU is to be hot-started by the start determination unit, an activation unit that cold-starts the CPU when the count value of the counter becomes equal to or greater than a preset value within a predetermined time ;
A gaming machine control device comprising: The cold start reset signal has a long pulse width so that it can be detected by the signal identification circuit, and the hot start reset signal has the same level as the noise so as not to be detected by the signal identification circuit. The gaming machine control device according to claim 1, wherein the gaming machine control device is set to a short pulse width . A game in which a CPU that controls the operation of a gaming machine has a built-in watchdog timer function, and resets the CPU every predetermined clock monitoring time unless the watchdog timer function releases the CPU. In the machine control device,
A signal identification circuit that is connected to the previous stage of the CPU and identifies whether the input signal to the reset terminal is a cold start reset signal output from various boards such as a power monitoring board or noise that can hot start the CPU When,
Start determination means for determining whether to hot start the CPU or cold start the CPU based on an input signal from the signal identification circuit when the CPU is reset;
A counter that is counted up when it is determined by the start determination means that the CPU is hot-started;
Even if it is determined that the CPU is to be hot-started by the start determination unit, an activation unit that cold-starts the CPU when the count value of the counter becomes equal to or greater than a preset value within a predetermined time;
A gaming machine control device comprising: The cold start reset signal has a long pulse width so that it can be detected by the signal identification circuit, and the signal identification circuit is configured not to detect a signal having a short pulse width at the same level as the noise. The gaming machine control device according to claim 3 .

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