JP4055909B2 - Wipe pattern generator - Google Patents

Description

  The present invention relates to a wipe pattern generation apparatus used for video production and the like, and more particularly to a wipe pattern generation apparatus that can generate various types of wipe patterns corresponding to high-resolution images.

  For example, in a video produced as a moving image such as a television broadcast, normally, a large number of frame images that are continuous in time series are sequentially switched and output at regular time intervals (for example, a frame period of 1/60 seconds). Will do. However, when switching scenes within the same program, or when switching the program itself, the continuity of the frame images that are output sequentially is suddenly interrupted, which may give the viewer an unnatural feeling. is there. In such a case, by gradually switching from the frame image of the previous scene to the frame image of the subsequent scene, it is possible to clearly notify the viewer that the scene changes.

  At the time of switching, two areas are formed in the same screen, the frame image of the scene before switching is displayed in one area, and the frame image of the scene after switching is displayed in the other area. By this, it becomes possible to convey the change of scene more clearly to the viewer. In the simplest example, it is conceivable to use a straight line as the boundary between a plurality of areas on the screen. However, the scene can be switched effectively by selectively using figures of various shapes. In order to generate such a boundary pattern, a wipe pattern generation device is used.

  As a technique related to a conventional wipe pattern generation device, for example, a technique disclosed in Patent Document 1 is known. This type of wipe pattern generation device uses coordinate information expressing each position on the display screen in polar coordinates, and according to the value of the result of comparing the distance of each position from the center coordinate on the screen with a threshold value, Switch between two video inputs for display.

  For example, as shown in FIG. 21, the conventional wipe pattern generation device includes a polar coordinate conversion unit 103, a graphic memory 106, a multiplier 108, and a comparator 109. In the input of the polar coordinate conversion unit 103, coordinates representing the scanning position on the display screen as shown in FIG. 22 are input as a combination of the x coordinate 101 and the y coordinate 102. The x coordinate 101 represents the pixel position in the horizontal direction on the screen, and the y coordinate 102 represents the pixel position in the vertical direction on the screen.

  Actually, scanning is performed in the order of (1), (2), (3), and (4) for each scanning line shown in FIG. 22, and the current scanning position is a combination of the x coordinate 101 and the y coordinate 102. Input to the polar coordinate conversion unit 103. The polar coordinate conversion unit 103 converts the input combination of the x coordinate 101 and the y coordinate 102 into position information in polar coordinate expression.

  In polar coordinate representation, the coordinates of each position are represented by an angle θ and a distance r. That is, as shown in FIG. 23, with a predetermined polar coordinate origin 111 as the center, a θ coordinate 104 that is an angle θ representing an inclination with respect to a reference axis, and an r coordinate 105 that represents a distance r from the polar coordinate origin 111 to each position. Coordinates are expressed in combination.

  The graphic memory 106 holds the corresponding graphic data as a value corresponding to the distance from the polar coordinate origin 111 at each address associated with the θ coordinate 104. Therefore, when the θ coordinate 104 is input as a read address to the input of the graphic memory 106, the distance data in the corresponding direction is read from the graphic memory 106.

  The multiplier 108 multiplies the graphic data representing the distance read from the graphic memory 106 by the coefficient 107 input from the outside, and outputs the result. The comparator 109 compares the value output from the multiplier 108 with the value of the r coordinate 105 output from the polar coordinate conversion unit 103 and outputs the comparison result as a wipe pattern output 110.

  For example, if data representing a triangular figure pattern is stored in the figure memory 106, as shown in FIG. 24, figure data representing the distance from the polar coordinate origin 111 to each point of the outline on the triangle figure pattern. Is read out from the graphic memory 106 in accordance with the value of the input θ coordinate 104. Further, since the graphic data read from the graphic memory 106 is multiplied by the coefficient 107 by the multiplier 108, the graphic pattern can be enlarged or reduced by this multiplication.

  Actually, the display screen is sequentially scanned, and the position information of each scanning position is input to the polar coordinate conversion unit 103 as a combination of the x coordinate 101 and the y coordinate 102. Therefore, the wipe pattern output output from the comparator 109 is output. 110 becomes as shown in FIG. That is, the display screen is divided into two areas as indicated by the diagonal lines and white background in the figure, with the outline on the triangular figure pattern as the boundary.

JP 10-65966 A

  In actuality, when generating a wipe pattern, a more complicated graphic pattern is actually required, or various types of graphic patterns are required. However, in the conventional wipe pattern generation apparatus as described above, a large-capacity graphic memory is indispensable for realizing various graphic wipe patterns. For example, in order to generate various graphic patterns such as triangles, pentagons, hexagons,..., A storage area for storing data for each type of graphic as shown in FIG. It was necessary to secure.

  In recent years, since the resolution of the display screen has been increased, it is necessary to execute the wipe pattern generation process at a high speed. However, if a large-capacity ROM (read-only memory) is used as a large-capacity graphic memory, it is difficult to generate a wipe pattern for a high-resolution display screen because the access speed to the memory is slow.

  On the other hand, recently, semiconductor devices that can dynamically reconfigure a circuit configuration and efficiently mount hardware functions using limited hardware resources have appeared. However, in the design based on the premise of using a large capacity ROM, it is difficult to make use of the advantages because the large capacity ROM cannot be configured on the semiconductor device.

  The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a wipe pattern generation device that can execute wipe pattern generation of various figures at high speed and can be easily downsized.

  In the wipe pattern generation device of the present invention, position information corresponding to each pixel on the display screen is input as polar coordinate data expressed by a combination of angle data θ and distance data r from the center of polar coordinates, and the polar coordinate data A wipe pattern generation apparatus that outputs a result of comparing the predetermined pattern information with a predetermined signal information, a dynamic reconfiguration device having a digital signal processing function, and a sin θ calculation means for calculating sin θ from the input angle data θ First multiplication means for multiplying the calculation result of sin θ and the first coefficient, cos θ calculation means for calculating cos θ from the angle data θ, and second multiplication for multiplying the calculation result of cos θ and the second coefficient. Means, and third multiplication means for multiplying the third coefficient by the result of adding the output of the first multiplication means and the output of the second multiplication means, A first circuit for calculating the reciprocal of the distance from the heart to an arbitrary straight line on the display screen is configured on the dynamic reconfiguration device, and a polar coordinate corresponding to the upper bits of the angle data θ A second circuit having a memory that holds a reciprocal of discrete distance data from a center to an arbitrary curve, and an interpolation unit that interpolates the memory output using the angle data θ; A second circuit configuration unit configured on the device, and an angle range to which the angle data θ belongs, and controls the first circuit configuration unit and the second circuit configuration unit according to the range of the angle data θ, A configuration switching means for dynamically switching between the first circuit and the second circuit, an output of the first circuit or a result of multiplying the output of the second circuit and the distance data r of the polar coordinates, and a fourth coefficient Compare with And a comparison means.

  In the above configuration, a multi-function circuit can be realized by efficiently using limited hardware resources by adopting a dynamic reconfigurable (RCF) device. The first circuit configured on the dynamic reconfigurable device is provided with sin θ calculating means, first multiplying means, cos θ calculating means, second multiplying means, and third multiplying means. Calculate the reciprocal of the distance to the straight line. In addition, in the second circuit configured on the dynamic reconfigurable device, a memory that holds the reciprocal of discrete distance data from the center of the polar coordinate corresponding to the upper bit of the angle data θ to an arbitrary curve, and the angle Interpolating means for interpolating the memory output using the data θ is provided. The configuration switching means identifies the range of angles to which the angle data θ belongs, controls the first circuit configuration means and the second circuit configuration means according to the range of the angle data θ, and the first circuit and the second circuit Switch dynamically.

  Here, the first circuit is a circuit for generating a linear pattern, and the linear pattern can be generated by calculation without using a large-capacity ROM. The second circuit is a circuit for generating a curve pattern, and the curve pattern can be generated by using a combination of a memory and an interpolation means without using a large capacity ROM. Furthermore, by combining the straight lines generated by the first circuit and the curves generated by the second circuit, the types of patterns that can be generated can be greatly increased. By dynamically switching between the first circuit and the second circuit by the configuration switching means, the straight line generated by the first circuit and the curve generated by the second circuit are variously combined according to the range of the angle data θ. Can do. Thereby, wipe pattern generation of various figures can be executed at high speed, and a wipe pattern generation device that can be easily downsized can be realized.

  In the wipe pattern generation device of the present invention, position information corresponding to each pixel on the display screen is input as polar coordinate data expressed by a combination of angle data θ and distance data r from the center of polar coordinates, A wipe pattern generation apparatus that outputs a result of comparing polar coordinate data and predetermined pattern information, from a dynamic reconfiguration device having a digital signal processing function, and a polar coordinate center corresponding to the upper bits of the angle data θ A second circuit having a memory for holding the reciprocal of discrete distance data up to the first curve, and an interpolating means for interpolating the memory output using the angle data θ. Second circuit configuration means configured above, and discrete distance data from the center of polar coordinates corresponding to the upper bits of the angle data θ to the second curve A third circuit comprising a memory for holding a number and an interpolating means for interpolating the memory output using the angle data θ on the dynamic reconfigurable device, and the angle data The range of angles to which θ belongs is identified, the second circuit configuration means and the third circuit configuration means are controlled according to the range of angle data θ, and the second circuit and the third circuit are dynamically switched. The apparatus includes a configuration switching unit, a comparison unit that compares a result obtained by multiplying the output of the second circuit or the output of the third circuit with the polar coordinate distance data r and a fourth coefficient.

  In the above configuration, the second circuit configured on the dynamic reconfigurable device stores a reciprocal of discrete distance data from the center of the polar coordinates corresponding to the upper bits of the angle data θ to the first curve. And interpolation means for interpolating the memory output using the angle data θ. Further, the third circuit has a memory for holding the reciprocal of discrete distance data from the center of the polar coordinate corresponding to the upper bit of the angle data θ to the second curve, and a memory output using the angle data θ. Interpolation means for interpolation is provided. The configuration switching means identifies the range of angles to which the angle data θ belongs, and controls the second circuit configuration means and the third circuit configuration means according to the range of the angle data θ, and the second circuit and the third circuit Switch dynamically.

  Here, the second circuit is a circuit for generating a first curve pattern, and the third circuit is a circuit for generating a second curve pattern. Further, the second circuit and the third circuit can generate a curve pattern by using a combination of a memory and an interpolation unit without using a large capacity ROM. Furthermore, it is possible to greatly increase the types of patterns that can be generated by combining the first curve pattern generated by the second circuit and the second curve pattern generated by the third circuit. By dynamically switching between the second circuit and the third circuit by the configuration switching means, the first curve pattern generated by the second circuit and the second circuit generated by the third circuit according to the range of the angle data θ. Various combinations with curve patterns are possible. Thereby, wipe pattern generation of various figures can be executed at high speed, and a wipe pattern generation device that can be easily downsized can be realized.

  According to the present invention, it is possible to provide a wipe pattern generation device that can execute wipe pattern generation of various figures at high speed and can be easily miniaturized.

  The wipe pattern generation device according to the present embodiment is used in a video processing device or the like, similar to a conventional wipe pattern generation device. For example, when a moving image such as a television broadcast is displayed on a screen, an area on the screen is displayed. It can be used to sort by the generated pattern.

(First embodiment)
FIG. 1 is a block diagram showing a first configuration example of a main part of a wipe pattern generation apparatus according to the first embodiment of the present invention, and FIG. 2 shows a main part of the wipe pattern generation apparatus according to the first embodiment of the present invention. It is a block diagram which shows the 2nd structural example.

  The wipe pattern generation device includes a θ range detection unit 31, a circuit configuration switching unit 32, a dynamic reconfiguration (Reconfigurable Compute Fabric) device RCF, a multiplier 11, and a comparator 109. In the wipe pattern generation apparatus according to the first embodiment, as will be described later, under certain conditions, the function of the first circuit 12 is configured inside the dynamic reconfiguration device RCF as shown in FIG. 2, the function of the second circuit 24 is configured in the dynamic reconfigurable device RCF as shown in FIG.

  As the dynamic reconfigurable device RCF, for example, MRC6011 manufactured by Motorola can be used. FIG. 3 is a block diagram showing a configuration example of the dynamic reconfiguration device, and shows a schematic configuration of the MRC 6011. The dynamic reconfigurable device RCF is constituted by a reconfigurable digital signal processor (DSP), and includes an input buffer 501, a frame buffer 502, a DMA controller 503, an I-cache 504, a D-cache 505, an RC controller 506, An RC array 507 and a context memory 508 are provided. An RC array 507 having a large number of reconfigurable cells RC for performing arithmetic logic operations is provided inside the dynamic reconfigurable device RCF, and each reconfigurable cell RC is connected in an array via a data bus. An RC controller 506 is provided to control a large number of reconfigurable cells RC. Further, a memory buffer including an input buffer 501 and a frame buffer 502 is provided to store wideband data.

  In the dynamic reconfigurable device RCF, the function itself of the RC array 507 can be switched by controlling the contents of the context stored in the context memory 508 that is an instruction executed by the RC array 507. That is, a functional circuit configuration can be reconfigured inside the dynamic reconfiguration device RCF.

  FIG. 4 is a schematic diagram illustrating a specific example of a wipe pattern in the wipe pattern generation device of the first embodiment. In the present embodiment, it is assumed that a wipe pattern as shown in FIG. 4 is applied to the display screen. In FIG. 4, the horizontal pixel position in the display screen is the x coordinate, the vertical pixel position is the y coordinate, the origin of the x coordinate is the upper left of the screen, and the origin of the y coordinate is the center of the screen. Further, the corresponding polar coordinate origin 111 is located at the left center of the screen. The wipe pattern shown in FIG. 4 is formed by a combination of a curve 1 and a straight line (y = − (1/3) x + 2/3).

  Information corresponding to the pixel coordinates (x coordinate, y coordinate) of the scanning position in the display screen is input as polar coordinates to the input of the wipe pattern generation device. This polar coordinate is constituted by a combination of an r coordinate 105 representing a distance from the polar coordinate origin 111 and a θ coordinate 104 representing an angle with respect to the reference axis. In the example shown in FIG. 1, the θ coordinate 104 is input as 20-bit parallel binary data.

  The θ range detector 31 identifies the range of angles to which the input θ coordinate 104 belongs. Specifically, the θ range detection unit 31 identifies whether or not the condition (0 ≦ θ <π / 2) is satisfied and whether or not the condition (−π / 2 ≦ θ <0) is satisfied.

  The circuit configuration switching unit 32 controls the dynamic reconfiguration device RCF according to the identification result of the θ range detection unit 31, and dynamically switches the circuit configured inside the dynamic reconfiguration device RCF. That is, when the input θ coordinate 104 satisfies the condition (0 ≦ θ <π / 2), the circuit configuration switching unit 32 replaces the first circuit 12 configured as shown in FIG. 1 with the dynamic reconfiguration device. When the input θ coordinate 104 satisfies the condition of (−π / 2 ≦ θ <0), the circuit configuration switching unit 32 configures the second circuit 24 configured as shown in FIG. Are configured inside the dynamic reconfiguration device RCF.

  The output of the first circuit 12 or the output of the second circuit 24 is connected to the input of the multiplier 11. The multiplier 11 multiplies the output of the first circuit 12 or the second circuit 24 and the r coordinate 105 and outputs the result. The comparator 109 compares the output value of the multiplier 11 with the coefficient R4, and outputs the result as a wipe pattern output 110.

  As shown in FIG. 1, the first circuit 12 configured inside the dynamic reconfiguration device RCF includes a sin θ calculation unit 1, a cos θ calculation unit 2, a multiplier 4, a multiplier 6, and an adder 8. And a multiplier 10. The sin θ calculation unit 1 performs sin θ calculation processing on the input θ coordinate 104. The cos θ calculation unit 2 performs cos θ calculation processing on the input θ coordinate 104.

  The multiplier 4 multiplies the output of the sin θ calculator 1 and the coefficient R1 and outputs the result. The multiplier 6 multiplies the output of the cos θ calculator 2 and the coefficient R2 and outputs the result. The adder 8 adds the output of the multiplier 4 and the output of the multiplier 6 and outputs the result. The multiplier 10 multiplies the output of the adder 8 by the coefficient R3 and outputs the result.

  By the way, the calculation function of sin θ and cos θ is generally realized by using a large-capacity ROM, but a large-capacity ROM cannot be configured inside the dynamic reconfigurable device RCF. When is used, since the access speed is slow, it is difficult to execute signal processing at high speed. Therefore, in the present embodiment, the sin θ calculation unit 1 shown in FIG. 1 is realized by a circuit having a configuration as shown in FIG. 5, and the cos θ calculation unit 2 is realized by a circuit having a configuration as shown in FIG.

  FIG. 5 is a block diagram showing a specific configuration of the sin θ calculator shown in FIG. 1, and FIG. 6 is a graph showing an example of operating characteristics of the sin θ calculator shown in FIG. FIG. 7 is a block diagram showing a specific configuration of the cos θ calculator shown in FIG. 1, and FIG. 8 is a graph showing an example of operating characteristics of the cos θ calculator shown in FIG.

  As shown in FIG. 5, the sin θ calculation unit 1 includes a sin θ table 301, a sin θ linear interpolation coefficient table 302, a multiplier 303, and an adder 304. The sin θ table 301 includes a memory, and the calculation result of the discrete sin θ assuming that the lower 10 bits are all 0 out of the θ coordinate 104 having 20-bit accuracy is the upper 10 bits of the θ coordinate 104. It is held at the address corresponding to the content. Therefore, by applying the upper 10 bits of the θ coordinate 104 to the sin θ table 301, the corresponding sin θ value can be read from the sin θ table 301 (see FIG. 6).

  The sin θ linear interpolation coefficient table 302 is configured by a memory, and holds an interpolation value corresponding to one step of the lower 10-bit value of the θ coordinate 104. As for this interpolation value, an appropriate value differs depending on the contents of the upper 10 bits of the θ coordinate 104, and therefore, different interpolation values are held at addresses associated with the upper 10 bits of the θ coordinate 104, respectively. Therefore, by providing the upper 10 bits of the θ coordinate 104 to the sin θ linear interpolation coefficient table 302, an appropriate interpolation value can be read from the sin θ linear interpolation coefficient table 302.

  The multiplier 303 multiplies the interpolation value corresponding to one step output from the sin θ linear interpolation coefficient table 302 and the lower 10-bit value of the θ coordinate 104 and outputs the result. The adder 304 adds the value output from the sin θ table 301 and the interpolated value output from the multiplier 303, and outputs the result as the value of sin θ subjected to linear interpolation (see FIG. 6).

  Since the sin θ calculation unit 1 configured as shown in FIG. 5 can handle the 20-bit θ coordinate 104 with only two memories having an address equivalent to 10 bits, a large-capacity memory is not required, and dynamic re-generation is possible. It can be realized in a size that can be configured inside the component device RCF.

  As illustrated in FIG. 7, the cos θ calculation unit 2 includes a cos θ table 401, a cos θ linear interpolation coefficient table 402, a multiplier 403, and an adder 404. The cos θ calculation unit 2 is configured by a memory, and among the θ coordinates 104 having a precision of 20 bits, the calculation result of discrete cos θ assuming that the lower 10 bits are all 0 is the upper 10 bits of the θ coordinate 104. Is held at the address corresponding to the contents of. Therefore, by giving the upper 10 bits of the θ coordinate 104 to the cos θ table 401, the corresponding cos θ value can be read from the cos θ table 401 (see FIG. 8).

  The cos θ linear interpolation coefficient table 402 includes a memory, and holds an interpolation value corresponding to one step of the lower 10-bit value of the θ coordinate 104. As for this interpolation value, an appropriate value differs depending on the contents of the upper 10 bits of the θ coordinate 104, and therefore, different interpolation values are held at addresses associated with the upper 10 bits of the θ coordinate 104, respectively. Accordingly, by providing the upper 10 bits of the θ coordinate 104 to the cos θ linear interpolation coefficient table 402, an appropriate interpolation value can be read from the cos θ linear interpolation coefficient table 402.

  The multiplier 403 multiplies the interpolation value corresponding to one step output from the cos θ linear interpolation coefficient table 402 by the lower 10 bits of the θ coordinate 104 and outputs the result. The adder 404 adds the value output from the cos θ table 401 and the interpolation value output from the multiplier 403, and outputs the result as the value of cos θ that has been linearly interpolated (see FIG. 8).

  The cos θ calculation unit 2 configured as shown in FIG. 7 can handle the 20-bit θ coordinate 104 with only two memories having an address equivalent to 10 bits. It can be realized in a size that can be configured inside the component device RCF.

  On the other hand, as shown in FIG. 2, the second circuit 24 configured inside the dynamic reconfiguration device RCF includes a curve 1 table 21 and a first interpolation circuit 25. For the input of the curve 1 table 21, the upper 10 bits of the θ coordinate 104 are input as a read address.

  The curve 1 table 21 includes a memory, and holds pattern data of a predetermined curve (curve 1) at an address associated with the upper 10 bits of the θ coordinate 104. Therefore, by giving the θ coordinate 104, the pattern data of the curve 1 corresponding to the θ coordinate 104 can be read from the curve 1 table 21. However, the data output from the curve 1 table 21 has only 10-bit accuracy of the θ coordinate 104. Therefore, high accuracy is ensured by using the first interpolation circuit 25.

  FIG. 9 is a block diagram showing a specific configuration of the first interpolation circuit shown in FIG. The first interpolation circuit 25 includes a curve 1 linear interpolation coefficient table 22, a multiplier 23, and an adder 26. The curve 1 linear interpolation coefficient table 22 includes a memory, and holds a coefficient corresponding to one step of θ for interpolation. Further, since the appropriate coefficient differs for each θ coordinate 104, different coefficients are held at addresses associated with the contents of the upper 10 bits of the θ coordinate 104. Therefore, by giving the upper 10 bits of the θ coordinate 104 as a read address of the curve 1 linear interpolation coefficient table 22, an appropriate interpolation coefficient can be read from the curve 1 linear interpolation coefficient table 22.

  The multiplier 23 multiplies the value output from the curve 1 linear interpolation coefficient table 22 by the lower 10 bits of the θ coordinate 104 and outputs the result. The adder 26 adds the value output from the curve 1 table 21 and the value output from the multiplier 23 and outputs the result as a linear interpolation result.

  Next, a configuration and operation for generating a specific wipe pattern in the first embodiment will be described. First, in the wipe pattern shown in FIG. 4, when the inputted θ coordinate 104 is within the range of (0 ≦ θ <π / 2), the first circuit 12 of FIG. 1 is used (y = − (1 / 3) Assume that a straight line pattern represented by a function of x + 2/3) is generated.

The distance from the polar coordinate origin 111 to an arbitrary point on the straight line (y = − (1/3) x + 2/3) is represented by r ₁ , and its reciprocal (1 / r ₁ ) is obtained by the following equation (1). .

The reciprocal of the distance (1 / r ₁ ) expressed by the above equation (1) is as shown in FIG. FIG. 10 is a graph showing the relationship between θ and the reciprocal of the distance r ₁ between the point on the straight line of the wipe pattern and the polar coordinate center in the first embodiment. FIG. 11 is a schematic diagram showing a straight line constituting a part of the wipe pattern in the first embodiment.

Therefore, in order to output the reciprocal (1 / r ₁ ) of the distance for generating the pattern of the straight line (y = − (1/3) x + 2/3) using the first circuit 12, the above (1 ) According to the content of the equation, “3” is assigned to the coefficient R1, “1” is assigned to the coefficient R2, and “1/2” is assigned to the coefficient R3.

Further, when “1” is assigned to the coefficient R4 to be compared by the comparator 109 and various polar coordinate values obtained by sequentially scanning the display screen are input to the circuit shown in FIG. 1 as the θ coordinate 104 and the r coordinate 105. As the wipe pattern output 110, a result as shown in FIG. 11 is obtained. That is, a binary signal representing a region when the screen is divided into two regions with the straight line (y = − (1/3) x + 2/3) as a boundary is obtained as the wipe pattern output 110. That is, a point where the value output from the multiplier 11, that is, (r / r ₁ ) coincides with the coefficient R4 “1” is located on the straight line (y = − (1/3) x + 2/3). .

  Next, in the wipe pattern shown in FIG. 4, when the input θ coordinate 104 is within the range of (−π / 2 ≦ θ <0), the pattern of the curve 1 using the second circuit 24 of FIG. The case of generating will be described.

  FIG. 12 is a schematic diagram showing an example of data held in the curve 1 table shown in FIG. In the curve 1 table 21 on the second circuit 24, as shown in FIG. 12, the polar coordinate origin 111 to the curve 1 on the lower 10 bits of the θ coordinate 104 composed of 20 bits is set to 0. The reciprocal of the discrete distance is held as data. Accordingly, the upper 10 bits of the θ coordinate 104 are given as the read address of the curve 1 table 21, and the reciprocal of the distance is read from the curve 1 table 21. However, since discrete data is output from the curve 1 table 21, linear interpolation is performed using the first interpolation circuit 25.

  The first interpolation circuit 25 is configured as shown in FIG. 9, and the curve 1 linear interpolation coefficient table 22 holds an interpolation value corresponding to one step of the lower 10 bits of the θ coordinate 104. A different value is assigned to this interpolation value for each address corresponding to the upper 10 bits of the θ coordinate 104. By adding the output of the curve 1 table 21 by the adder 26 to the result obtained by multiplying the value of the curve 1 linear interpolation coefficient table 22 and the lower 10 bits of the θ coordinate 104 by the multiplier 23, the linear interpolation result is obtained.

When the distance from the polar coordinate origin 111 to an arbitrary point on the curve 1 is represented by r ₂ , the linear interpolation result output from the first interpolation circuit 25 is (1 / r ₂ ). The output of the curve 1 table 21 and the linear interpolation result (1 / r ₂ ) are shown in a graph as shown in FIG.

FIG. 13 is a graph showing the relationship between θ and the reciprocal of the distance r ₂ between the point on the curve 1 of the wipe pattern and the polar coordinate center in the first embodiment. FIG. 14 is a schematic diagram showing a curve 1 constituting a part of the wipe pattern in the first embodiment.

  The second circuit 24 configured as shown in FIGS. 2 and 9 can handle the 20-bit θ-coordinate 104 with only two memories having an address equivalent to 10 bits, and thus does not require a large-capacity memory. It can be realized in a size that can be configured inside the dynamic reconfigurable device RCF.

Further, when “1” is assigned to the coefficient R4 to be compared by the comparator 109 and various polar coordinate values obtained by sequentially scanning the display screen are input to the circuit shown in FIG. 2 as the θ coordinate 104 and the r coordinate 105. As the wipe pattern output 110, a result as shown in FIG. 14 is obtained. That is, a binary signal representing a region when the screen is divided into two regions with the curve 1 as a boundary is obtained as the wipe pattern output 110. That is, a point where the value output from the multiplier 11, that is, (r / r ₂ ) coincides with the coefficient R4 “1” is located on the curve 1.

  In the actual wipe pattern generation apparatus of this embodiment, the θ range detection unit 31 shown in FIGS. 1 and 2 identifies the range of the θ coordinate 104, and the circuit configuration switching unit 32 dynamically reconfigures according to the result. The circuit configuration on the device RCF is dynamically switched. Therefore, as shown in FIG. 4, when the θ coordinate 104 is in the range of (0 ≦ θ <π / 2), the pattern of the straight line (y = − (1/3) x + 2/3) is the first circuit 12. When the θ coordinate 104 is in the range of (−π / 2 ≦ θ <0), the pattern of the curve 1 is generated by the operation of the second circuit 24, so that the straight line and the curve are continuous. Combined wipe patterns can be generated.

  In the present embodiment, the first circuit 12 and the second circuit 24 are used to generate a wipe pattern. However, since the dynamic reconfiguration device RCF is used as a common circuit resource and the configuration is switched, There is no need to prepare independent circuit resources for each of the first circuit 12 and the second circuit 24, and the apparatus can be downsized. Furthermore, by reducing the capacity by sharing memory resources, it becomes easy to use a memory capable of high-speed operation mounted on a semiconductor device, and high-speed operation of the entire circuit can be facilitated.

  In the above description, the case where a pattern of a straight line (y = − (1/3) x + 2/3) is generated by the first circuit 12 is described as a specific example. However, the coefficients R1, R2, R3, By appropriately changing the value of, a wipe pattern based on other straight lines having various inclinations can be generated.

  The specific configuration of the above-described sin θ calculation unit 1, cos θ calculation unit 2, second circuit 24, and the like may be any other configuration that can be realized with a memory capacity that can be mounted on the dynamic reconfiguration device RCF. The circuit configuration may be adopted. Moreover, various shapes can be realized for the curve 1.

  In the above example, the case where the polar coordinate angle θ on the display screen is set in the range of (−π / 2) to (π / 2) has been described. An angle θ outside the range of (−π / 2) to (π / 2) may be used. Further, as the boundary value of θ at which the circuit configuration switching unit 32 switches the circuit configuration, a value other than 0 may be used, and a plurality of values may be used as the boundary value. For the coefficient R4, the wipe pattern can be enlarged or reduced with the polar coordinate origin 111 as the center by adopting a value other than 1 or making the value variable.

(Second Embodiment)
FIG. 15 is a block diagram showing a configuration example of a main part of a wipe pattern generation device according to the second embodiment of the present invention. FIG. 16 is a schematic diagram illustrating a specific example of a wipe pattern in the wipe pattern generation apparatus according to the second embodiment.

  The second embodiment is a modification of the first embodiment described above. In FIG. 15 and FIG. 17, the same elements corresponding to those of the first embodiment are indicated by the same reference numerals. In the following description, the configuration and operation different from those of the first embodiment will be mainly described.

  In the second embodiment, it is assumed that a wipe pattern as shown in FIG. 16 is applied to the display screen. In FIG. 16, the horizontal pixel position in the display screen is the x coordinate, the vertical pixel position is the y coordinate, the origin of the x coordinate is the upper left of the screen, and the origin of the y coordinate is the center of the screen. Further, the corresponding polar coordinate origin 111 is located at the left center of the screen. Further, the wipe pattern shown in FIG. 16 is formed by a combination of curve 1 and curve 2.

  The wipe pattern generation device includes a θ range detection unit 31, a circuit configuration switching unit 32B, a dynamic reconfiguration device RCF, a multiplier 11, and a comparator 109. That is, only the configuration of the circuit configuration switching unit 32B is different from the first embodiment. Here, in the second embodiment, the second circuit 24 or the third circuit 45 is formed on the dynamic reconfiguration device RCF under the control of the circuit configuration switching unit 32B.

  In the wipe pattern generation device of the second embodiment, as will be described later, the function of the second circuit 24 is configured inside the dynamic reconfiguration device RCF under certain conditions as shown in FIG. Under these conditions, as shown in FIG. 15, the function of the third circuit 45 is configured inside the dynamic reconfigurable device RCF.

  As in the first embodiment, information corresponding to pixel coordinates (x coordinate, y coordinate) of the scanning position in the display screen is input as polar coordinates to the input of the wipe pattern generation device. This polar coordinate is constituted by a combination of an r coordinate 105 representing a distance from the polar coordinate origin 111 and a θ coordinate 104 representing an angle with respect to the reference axis. In the example shown in FIG. 15, the θ-coordinate 104 is input as 20-bit parallel binary data.

  The θ range detector 31 identifies the range of angles to which the input θ coordinate 104 belongs. Specifically, the θ range detection unit 31 identifies whether or not the condition (0 ≦ θ <π / 2) is satisfied and whether or not the condition (−π / 2 ≦ θ <0) is satisfied.

  The circuit configuration switching unit 32B controls the dynamic reconfiguration device RCF according to the identification result of the θ range detection unit 31, and dynamically switches the circuit configured in the dynamic reconfiguration device RCF. That is, when the input θ coordinate 104 satisfies the condition (0 ≦ θ <π / 2), the circuit configuration switching unit 32B replaces the third circuit 45 configured as shown in FIG. 15 with the dynamic reconfiguration device. When the input θ coordinate 104 satisfies the condition of (−π / 2 ≦ θ <0) configured inside the RCF, the circuit configuration switching unit 32B has the second circuit 24 configured as shown in FIG. Are configured inside the dynamic reconfiguration device RCF.

  The configuration and operation of the second circuit 24 shown in FIG. 2 are as described in the first embodiment.

  As shown in FIG. 15, the third circuit 45 configured inside the dynamic reconfiguration device RCF includes a curve 2 table 41 and a second interpolation circuit 46. The upper 12 bits of the θ coordinate 104 are input to the input of the curve 2 table 41, and the output of the curve 2 table 41 and the θ coordinate 104 are input to the two inputs of the second interpolation circuit 46.

  FIG. 17 is a block diagram showing a specific configuration of the second interpolation circuit shown in FIG. The second interpolation circuit 46 includes a curve 2 linear interpolation coefficient table 42, a multiplier 43, and an adder 44. The curve 2 linear interpolation coefficient table 42 inputs the upper 12 bits of the θ coordinate 104 as a read address and outputs the corresponding interpolation coefficient. The multiplier 43 multiplies the output of the curve 2 linear interpolation coefficient table 42 and the lower 8 bits of the θ coordinate 104 and outputs the result. The adder 44 adds the output of the curve 2 table 41 and the output of the multiplier 43 and outputs the result.

  Next, a configuration and operation for generating a specific wipe pattern in the first embodiment will be described.

  When the input θ coordinate 104 is within the range of (−π / 2 ≦ θ <0), the circuit configuration switching unit 32B forms the second circuit 24 on the dynamic reconfiguration device RCF. The pattern of curve 1 shown in FIG. 16 is generated similarly to the first embodiment by the action of the two circuits 24. On the other hand, when the input θ coordinate 104 is in the range of (0 ≦ θ <π / 2), the circuit configuration switching unit 32B forms the third circuit 45 on the dynamic reconfiguration device RCF.

FIG. 18 is a schematic diagram showing an example of data held in the curve 2 table shown in FIG. If the curve 2 table 41 in the third circuit 45, the inverse of the distance r ₃ from the polar coordinate origin 111 to any point on the curve 2, theta lower 8 bits of the coordinates 104 consists of 20 bits is 0 Is stored as discrete data. Therefore, by giving the upper 12 bits of the θ coordinate 104 to the curve 2 table 41 as a read address, data of the reciprocal of the distance r ₃ is read from the curve 2 table 41.

  The second interpolation circuit 46 in the third circuit 45 is provided for linearly interpolating the data output from the curve 2 table 41. The curve 2 linear interpolation coefficient table 42 provided in the second interpolation circuit 46 holds an interpolation coefficient corresponding to one step of the lower 8 bits of the θ coordinate 104. Since an appropriate interpolation coefficient differs depending on the value of the upper 12 bits of the θ coordinate 104, different interpolation coefficients are stored in the addresses associated with the value of the upper 12 bits of the θ coordinate 104 in the curve 2 linear interpolation coefficient table 42. It is. Therefore, an appropriate interpolation coefficient is read from the curve 2 linear interpolation coefficient table 42 by giving the upper 12 bits of the θ coordinate 104 to the read address of the curve 2 linear interpolation coefficient table 42.

FIG. 19 is a graph showing the relationship between θ and the inverse of the distance r ₃ between the point on the curve 2 of the wipe pattern and the polar coordinate center in the second embodiment. FIG. 20 is a schematic diagram showing a curve 2 constituting a part of the wipe pattern in the second embodiment.

The multiplier 43 multiplies the lower 8 bits of the θ coordinate 104 by the interpolation coefficient output from the curve 2 linear interpolation coefficient table 42 and outputs the result. The adder 44 adds the value output from the curve 2 table 41 and the value output from the multiplier 43 and outputs the result as a linear interpolation result. This linear interpolation result is the reciprocal (1 / r ₃ ) of the distance r ₃ described above (see FIG. 19).

  The third circuit 45 configured as shown in FIGS. 15 and 17 can deal with the 20-bit θ coordinate 104 only by using a memory having an address equivalent to 12 bits and a memory having an address equivalent to 8 bits. It can be realized in a size that can be configured inside the dynamic reconfigurable device RCF without requiring a memory of a capacity.

The multiplier 11 multiplies the r coordinate 105 by (1 / r ₂ ) output from the second circuit 24 or (1 / r ₃ ) output from the third circuit 45 and outputs the result. The comparator 109 compares the value ((r / r ₂ ) or (r / r ₃ )) output from the multiplier 11 with the coefficient R 4 and outputs the result as the wipe pattern output 110.

Further, when “1” is assigned to the coefficient R4 to be compared by the comparator 109 and various polar coordinate values obtained by sequentially scanning the display screen are input to the circuit shown in FIG. 15 as the θ coordinate 104 and the r coordinate 105. As the wipe pattern output 110, a result as shown in FIG. 20 is obtained. That is, a binary signal representing a region when the screen is divided into two regions with the curve 2 as a boundary is obtained as the wipe pattern output 110. That is, a point where the value output from the multiplier 11, that is, (r / r ₃ ) coincides with the coefficient R4 “1” is located on the curve 2.

  In the second embodiment, the second circuit 24 and the third circuit 45 are used to generate the wipe pattern. However, since the dynamic reconfiguration device RCF is used as a common circuit resource and the configuration is switched, There is no need to prepare independent circuit resources for the second circuit 24 and the third circuit 45, and the apparatus can be downsized. Furthermore, by reducing the capacity by sharing memory resources, it becomes easy to use a memory capable of high-speed operation mounted on a semiconductor device, and high-speed operation of the entire circuit can be facilitated.

  As for the configuration of the third circuit 45, a circuit configuration other than the configuration shown in FIG. 17 may be adopted as long as the configuration can be realized with a memory capacity that can be mounted on the dynamic reconfiguration device RCF. Moreover, various shapes can be realized for the curve 2.

  In the above example, the case where the polar coordinate angle θ on the display screen is set in the range of (−π / 2) to (π / 2) has been described. An angle θ outside the range of (−π / 2) to (π / 2) may be used. Further, as the boundary value of θ at which the circuit configuration switching unit 32B switches the circuit configuration, a value other than 0 may be used, and a plurality of values may be used as the boundary value. For the coefficient R4, the wipe pattern can be enlarged or reduced with the polar coordinate origin 111 as the center by adopting a value other than 1 or making the value variable.

  According to the wipe pattern generation apparatus of the present embodiment described above, various patterns can be generated without using a large-capacity ROM. Since a large-capacity ROM is not used, it is possible to prevent the pattern generation speed from being slowed down, and it is possible to deal with a high-resolution display screen. Moreover, since the pattern to be generated is switched by using a dynamic reconfigurable device and changing its configuration according to the polar angle range, various types of patterns can be used by effectively utilizing limited hardware resources. Can be generated. Therefore, the wipe pattern generation apparatus of the present embodiment can execute wipe pattern generation of various figures at high speed with a miniaturized and high speed configuration, and can produce and edit video and images. Can be widely used.

  Although various embodiments of the present invention have been described above, the present invention is not limited to the matters described in the above embodiments, and those skilled in the art will understand the configuration and operation based on the description of this specification and well-known techniques. It goes without saying that it is possible to change or apply a part of the above.

  The present invention is capable of generating wipe patterns of various figures at high speed, and has an effect that can be easily reduced in size, and is used for video production and the like, particularly for high resolution images. It is useful for a wipe pattern generation device that can generate many types of wipe patterns.

The block diagram which shows the 1st structural example of the principal part of the wipe pattern generation apparatus which concerns on the 1st Embodiment of this invention. The block diagram which shows the 2nd structural example of the principal part of the wipe pattern generation apparatus in the 1st Embodiment of this invention. Block diagram showing a configuration example of a dynamic reconfiguration device The schematic diagram which shows the specific example of the wipe pattern in the wipe pattern production | generation apparatus of 1st Embodiment. The block diagram which shows the concrete structure of the sin (theta) calculation part shown by FIG. FIG. 5 is a graph showing an example of operating characteristics of the sin θ calculator The block diagram which shows the concrete structure of the cos (theta) calculation part shown by FIG. FIG. 7 is a graph showing an example of operation characteristics of the cos θ calculation unit in FIG. The block diagram which shows the concrete structure of the 1st interpolation circuit shown by FIG. Graph showing the relationship between the reciprocal of the distance r ₁ between point and polar center on a straight line in the wipe pattern θ in the first embodiment The schematic diagram which shows the straight line which comprises a part of wipe pattern in 1st Embodiment. The schematic diagram which shows the example of the data which the curve 1 table shown by FIG. 2 hold | maintains Graph showing the relationship between the reciprocal of the distance r ₂ between the point and the polar coordinates centered on the curve 1 of the wipe pattern θ in the first embodiment The schematic diagram which shows the curve 1 which comprises a part of wipe pattern in 1st Embodiment. The block diagram which shows the structural example of the principal part of the wipe pattern generation apparatus which concerns on the 2nd Embodiment of this invention. The schematic diagram which shows the specific example of the wipe pattern in the wipe pattern generation apparatus of 2nd Embodiment The block diagram which shows the concrete structure of the 2nd interpolation circuit shown by FIG. Schematic diagram showing an example of data held in the curve 2 table shown in FIG. Graph showing the relationship between the reciprocal of the distance r ₃ between the point and the polar coordinates centered on the curve 2 of the wipe pattern θ in the second embodiment The schematic diagram which shows the curve 2 which comprises a part of wipe pattern in 2nd Embodiment. The block diagram which shows the structure of the wipe pattern generation apparatus of a prior art example Front view showing an example of a display screen to which a wipe pattern is applied Schematic diagram showing examples of polar coordinates on the display screen The schematic diagram which shows the example of the data hold | maintained at the memory in the wipe pattern generation apparatus of a prior art example Front view showing a state where the display screen is divided by the generated wipe pattern The schematic diagram which shows the example of the data hold | maintained at the memory in the wipe pattern generation apparatus of a prior art example

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 sin (theta) calculation part 2 cos (theta) calculation part 4,6,10,11 multiplier 8 adder 12 1st circuit 21 curve 1 table 22 curve 1 linear interpolation coefficient table 23 multiplier 24 2nd circuit 25 1st interpolation circuit 26 adder 31 θ range detection unit 32, 32B circuit configuration switching unit 41 curve 2 table 42 curve 2 linear interpolation coefficient table 43 multiplier 44 adder 45 third circuit 46 second interpolation circuit 104 θ coordinate 105 r coordinate 109 comparator 110 wipe pattern Output 111 Polar coordinate origin 301 sin θ table 302 sin θ linear interpolation coefficient table 303 multiplier 304 adder 401 cos θ table 402 cos θ linear interpolation coefficient table 403 multiplier 404 adder R1, R2, R3, R4 coefficient RCF dynamic reconfiguration device

Claims (2)

Position information corresponding to each pixel on the display screen is input as polar coordinate data expressed by a combination of angle data θ and distance data r from the center of polar coordinates, and the polar coordinate data is compared with predetermined pattern information. A wipe pattern generation device that outputs a result,
A dynamic reconfigurable device with digital signal processing capabilities;
Sin θ calculation means for calculating sin θ from the input angle data θ, first multiplication means for multiplying the calculation result of the sin θ and a first coefficient, cos θ calculation means for calculating cos θ from the angle data θ, Second multiplying means for multiplying the calculation result of the cos θ by the second coefficient, and third multiplying means for multiplying the result obtained by adding the output of the first multiplying means and the output of the second multiplying means with the third coefficient; A first circuit configuration means for configuring, on the dynamic reconfiguration device, a first circuit that calculates a reciprocal of a distance from a center of polar coordinates to an arbitrary straight line on the display screen;
A memory that holds the reciprocal of discrete distance data from the center of polar coordinates corresponding to the upper bits of the angle data θ to an arbitrary curve; and an interpolation means that interpolates the memory output using the angle data θ. Second circuit configuration means for configuring a second circuit on the dynamic reconfiguration device;
The range of angles to which the angle data θ belongs is identified, the first circuit configuration means and the second circuit configuration means are controlled according to the range of the angle data θ, and the first circuit and the second circuit are operated. Switching means for switching automatically,
A wipe pattern generation device comprising: a comparison unit that compares a result obtained by multiplying the output of the first circuit or the output of the second circuit by the polar coordinate distance data r and a fourth coefficient. Position information corresponding to each pixel on the display screen is input as polar coordinate data expressed by a combination of angle data θ and distance data r from the center of polar coordinates, and the polar coordinate data is compared with predetermined pattern information. A wipe pattern generation device that outputs a result,
A dynamic reconfigurable device with digital signal processing capabilities;
A memory for holding the reciprocal of discrete distance data from the center of the polar coordinate corresponding to the upper bits of the angle data θ to the first curve, and an interpolation means for interpolating the memory output using the angle data θ A second circuit configuration means configured on the dynamic reconfiguration device,
A memory for holding the reciprocal of discrete distance data from the center of the polar coordinate corresponding to the upper bits of the angle data θ to the second curve, and an interpolation means for interpolating the memory output using the angle data θ A third circuit comprising: a third circuit comprising: a third circuit comprising:
The range of angles to which the angle data θ belongs is identified, the second circuit configuration means and the third circuit configuration means are controlled according to the range of the angle data θ, and the second circuit and the third circuit are operated. Switching means for switching automatically,
A wipe pattern generation device comprising: a comparison unit that compares the output of the second circuit or the output of the third circuit and the polar coordinate distance data r with a fourth coefficient.

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