JP4044738B2 - Semiconductor photo detector - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor light receiving element, and more particularly to a semiconductor light receiving element using optical fiber communication or the like.
[0002]
[Prior art]
In recent years, semiconductor light receiving elements have been widely used in optical fiber communication.
The characteristics of the light receiving element for optical communication have been developed mainly to improve each characteristic of response speed, light receiving sensitivity, and wavelength sensitivity band.
[0003]
A recent increase in the amount of information transmitted in the communication industry is accompanied by a demand for a light receiving element with a higher response speed.
[0004]
FIG. 3 is a cross-sectional view showing a structure of an InGaAs / InP PIN photodiode, which is a typical conventional semiconductor light receiving element.
[0005]
Reference numeral 20 denotes an n-type InP substrate, and an n-type InP buffer layer 21, an n ⁻ -type InGaAs light absorption layer 22, and an n ⁻ -type InP window layer 23 are sequentially grown on the n-type InP substrate 20, Further, an impurity such as Zn is selectively diffused in a partial region of the n ⁻ type InP window layer 23 to provide a p ⁺ type InP region 24. An insulating film 25 and a surface electrode 26 are provided on the light receiving surface of the element, and the other electrode 26 is provided on the back surface of the n-type InP substrate 20.
[0006]
In the semiconductor light receiving device of the above structure, a reverse bias voltage is applied between the opposing electrodes 26, and, in the state of applying the reverse bias, as shown by the energy band diagram of FIG. 6, n ^- -type InGaAs most areas of the light absorbing layer 22 are depleted, the light 27 in this state is incident on the surface of the device, n ^- -type InGaAs light carriers excited by absorbing layer 22 n ^- type field of the InGaAs optical absorption layer 22 As a result, holes move to the p ⁺ -type InP region 24, electrons move to the n-type InP buffer layer 21, and a photocurrent flows.
[0007]
On the other hand, Japanese Patent Application Laid-Open No. 03-109779 proposes a technique for further improving the light receiving sensitivity by providing a multilayer reflective layer.
[0008]
FIG. 4 is a cross-sectional view of this semiconductor light-receiving element. An n-type InP buffer layer 21, a multilayer reflective layer 28 formed of InGaAsP and InP, an n ⁻ -type InGaAs light absorption layer 22, The n ⁻ -type InP window layer 23 is sequentially grown, and other configurations are the same as those of the semiconductor light receiving element shown in FIG.
[0009]
Thus, by providing the multilayer reflection layer 28 formed of InGaAsP and InP between the n-type InP buffer layer 21 and the n ⁻ -type InGaAs light absorption layer 22, incident light 27 is transmitted by the multilayer reflection layer 28. Reflected upward and thereby absorbed by the light absorption layer 22, as a result, the light receiving sensitivity is improved.
[0010]
[Problems to be solved by the invention]
According to the semiconductor light-receiving device as shown in FIG. 3, in order to improve the light receiving sensitivity, almost all the incident light n ^- but it is being absorbed by the type InGaAs light absorbing layer 22, in order that the n ^- -type It is necessary to increase the thickness of the InGaAs light absorption layer 22.
[0011]
However, if the n ⁻ -type InGaAs light absorption layer 22 is made thicker than necessary, the traveling time of carriers traveling through the light absorption layer 22 is delayed, and the response speed is degraded.
[0012]
On the other hand, as shown in FIG. 4, according to Japanese Patent Laid-Open No. 03-1097779, by providing the multilayer film reflection layer 28, the incident light 27 is reflected upward by the multilayer film reflection layer 28, thereby the light absorption layer. However, on the other hand, the number of manufacturing steps is increased by providing a multilayer reflective layer, and the thickness of the reflective layer needs to be controlled by several tens of meters. The manufacturing process becomes complicated.
[0013]
Accordingly, the present invention has been completed in view of the above circumstances, and an object thereof is to provide a high-performance and low-cost semiconductor light-receiving element by improving the light-receiving sensitivity without complicating the manufacturing process. .
[0014]
[Means for Solving the Problems]
The semiconductor light-receiving element of the present invention is formed by sequentially laminating a large-area one-conductivity-type semiconductor layer and a light-absorption layer composed of a small-area semiconductor layer on a semi-insulating semiconductor substrate, and conducting reverse conductivity on the light-absorption layer. A first semiconductor layer and a first electrode, a second electrode formed on the exposed surface of the one-conductive semiconductor layer, and a third electrode formed on the back surface of the semi-insulating semiconductor substrate. between the electrode and the second electrode, between the second electrode and the third electrode, characterized in that the voltage applied at, respectively it reverse bias.
[0015]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, the semiconductor light receiving element of the present invention will be described using an InGaAs / InP PIN photodiode as an example.
[0016]
FIG. 1 is a top view of a semiconductor light-receiving element of the present invention, and FIG. 2 is a schematic cross-sectional view taken along section line AA ′ in FIG.
[0017]
Reference numeral 10 denotes an InP substrate made of a semi-insulating semiconductor. On the InP substrate 10, an n-type InP buffer layer 11 which is the large-area one-conductivity-type semiconductor layer and a small-area n ⁻ -type InGaAs light absorption layer 12 are formed. And the n ⁻ -type InP window layer 13, which is the reverse conductivity type semiconductor layer, is provided on the light absorption layer 12. A p ⁺ -type InP diffusion region 14 is formed inside the InP window layer 13.
[0018]
Furthermore, the electrode 16a as the first electrode is formed on the light receiving surface of the element, the electrode 16b as the second electrode is formed on the exposed surface of the n-type InP buffer layer 11, and the third electrode is formed on the back surface of the InP substrate 10. An electrode 16c is formed, and the element is covered with an insulating film 15.
[0019]
Next, each layer will be described in detail.
[0020]
The InP substrate 10 is a semi-insulating semiconductor substrate having a (100) plane with an off-angle of 2 ° in the <011> direction.
[0021]
The n-type InP buffer layer 11 contains about 1 × 10 ¹⁷ to 10 ¹⁹ atoms / cm ³ of one conductivity type impurity (such as Si) and is formed to a thickness of about 2 to 3 μm.
[0022]
The n ⁻ -type InGaAs light absorption layer 12 is non-doped without impurities, but actually contains about 8 × 10 ¹³ atoms / cm ³ of one conductivity type impurity (Si, etc.) and is about 2 to 3 μm. It is thickness.
[0023]
The n ⁻ -type InP window layer 13 is non-doped without impurities, but actually contains about 8 × 10 ¹³ atoms / cm ³ of one conductivity type impurity (Si or the like) and has a thickness of about 1 μm. .
[0024]
The p ⁺ -type InP diffusion region 14 contains about 1 × 10 ¹⁷ to 10 ¹⁹ atoms / cm ³ of zinc (Zn) reverse conductivity type semiconductor impurities and has a thickness of about 0.1 to 0.2 μm.
[0025]
The insulating film 15 is made of silicon nitride (SiNx) or the like and has a thickness of about 3000 mm.
[0026]
The electrodes 16a and 16c are made of gold / gold / zinc (Au / AuZn), electrode 16b gold / gold / germanium (Au / AuGe), etc., and have a thickness of about 3000 mm.
[0027]
Thus, according to the semiconductor light receiving element having the above-described configuration, when the electrode 16b is provided on the exposed surface of the n-type InP buffer layer 11 having a further step, and a reverse bias voltage is applied between the electrode 16a and the electrode 16b, A figure similar to the energy band shown in FIG. 6 is obtained.
[0028]
However, when a reverse bias voltage is further applied between the electrode 16c and the electrode 16b, an energy band diagram as shown in FIG. 5 is obtained.
[0029]
In contrast to FIG. 6, by applying a reverse bias voltage between the electrode 16c and the electrode 16b, a potential barrier is formed in the vicinity of the interface between the n-type InP buffer layer 11 and the substrate 10, thereby confining carriers. Cause it to occur. Therefore, the carriers generated by the incident light 17 are drifted to both the p ⁺ -type InP diffusion region 14 and the n-type InP buffer layer 11 respectively. As a result, the generated carriers drift to the InP substrate 10 having a large band gap. The light receiving sensitivity is improved.
[0030]
Further, according to the present invention, as shown in FIG. 4, since the multilayer film reflective layer 28 is not provided, the number of manufacturing processes is not increased in that respect, and the manufacturing process is simplified correspondingly.
[0031]
[Example 1]
(Example 1)
Next, the semiconductor light emitting device of the present invention was fabricated with an InGaAs-based semiconductor light receiving device by epitaxial growth by MOCVD, and the evaluation test was performed. For this production, the steps (1) to (8) are sequentially performed.
[0032]
(1) Process:
As the InP substrate 10, a semi-insulating substrate having a (100) plane with an off-angle of 2 ° in the <011> direction is used. Then, the substrate temperature is heated to 550 ° C. in an atmosphere of hydrogen (H ₂ ) and phosphine (PH ₃ ).
[0033]
In this step, in order to prevent thermal deterioration of the InP substrate due to the separation of the P element, it is preferable to increase the partial pressure of phosphine, which is a group V source gas.
[0034]
(2) Process:
An n-type InP buffer layer is supplied at 550 ° C. by supplying trimethylindium (hereinafter referred to as TMI) as a group III source gas and phosphine (PH ₃ ) as a group V source gas and using silane gas (SiH ₄ ) as a dopant gas. 11 is grown epitaxially.
[0035]
The concentration of the semiconductor impurity Si in this layer 11 was 3 × 10 ¹⁸ atoms / cm ³ and the film thickness was 3 μm.
[0036]
(3) Process:
An n ⁻ -type InGaAs light absorption layer 12 is grown at 560 ° C. by supplying TMI and trimethylgallium (hereinafter referred to as TMG) as a group III source gas and arsine gas (AsH ₃ ) as a group V source gas. The film thickness is 2 μm.
[0037]
Although it is non-doped without impurities, it actually contains about 8 × 10 ¹³ atoms / cm ^{3 of} Si remaining on the reaction tube wall or C from organic matter.
[0038]
(4) Process:
Next, TMI as a group III source gas and phosphine (PH ₃ ) as a group V source gas are supplied, and the n ⁻ -type InP window layer 13 is grown at 550 ° C. The film thickness is 1 μm. This n ⁻ -type InP window layer 13 is also non-doped without impurities as in the previous n ⁻ -type InGaAs light absorption layer 12, but in reality, 8 × containing approximately 10 ¹³ atoms / cm ^3.
[0039]
(5) Process:
A mesa structure is formed using a sulfuric acid hydrogen peroxide based etching solution. Subsequently, etching is similarly performed using a sulfuric acid hydrogen peroxide based etching solution so that a part of the n-type InP buffer layer 11 is exposed.
[0040]
(6) Process:
A selective diffusion mask pattern made of silicon nitride (SiNx) having a thickness of 1000 mm is formed on the n ⁻ -type InP window layer 13 using silane gas (SiH ₄ ) and ammonia (NH ₄ ) by plasma CVD. Thereafter, a sample is enclosed in a quartz ampule tube together with an ingot of zinc arsenic (ZnAs), and thermal diffusion is performed in a diffusion furnace to form a p ⁺ -type InP diffusion region. The diffusion temperature is 500 ° C.
[0041]
(7) Process:
After the diffusion in the previous step, the selective diffusion mask pattern is removed with hydrofluoric acid (HF), and the insulating film made of silicon nitride (SiN _x ) is again used with silane gas (SiH ₄ ) and ammonia (NH ₄ ) by the plasma CVD method. A film 15 is formed.
[0042]
(8) Process:
After that, the electrode 16a is formed with gold / gold / zinc (Au / AuZnl) and the electrode 16b with gold / gold / germanium (Au / AuGe) to a thickness of 2500 mm by vapor deposition or sputtering. Then, an electrode 16c is formed on the back surface of the substrate with gold / gold / zinc (Au / AuZn) to a thickness of 2500 mm.
[0043]
When a reverse bias voltage is applied to the electrode 16a and the electrode 16b as shown in the circuit diagram of FIG. 7 using a light source having a wavelength of 1.31 μm for the semiconductor light-receiving element thus obtained, (2) the electrode 16a The light receiving sensitivity was measured separately when the reverse bias voltage was applied to the electrode 16b and the reverse bias voltage was applied to the electrode 16c and the electrode 16b.
[0044]
In this measurement, the light intensity was obtained using an optical power meter, light having the light intensity was incident on the light receiving element of the present invention, the photocurrent was measured with an electrometer, and the ratio was obtained.
[0045]
As a result of such measurement, the light receiving sensitivity was 0.89 A / W in the case of {circle around (1)} as in the prior art, whereas in the case of {circle around (2)}, the light receiving sensitivity was 0.92 A / W. Improved.
[0046]
(Example 2)
In Example 1, an InGaAs / InP PIN photodiode was fabricated, but in this example, a GaAs / GaAs PIN photodiode was fabricated instead and measured and evaluated in the same manner. In this example, the same reference numerals are used because the configuration is as shown in FIGS.
[0047]
For this production, the steps (1) to (8) are sequentially performed.
[0048]
(1) Process:
As the GaAs substrate 10, a semi-insulating substrate having a (100) plane with an off-angle of 2 ° in the <011> direction is used. Then, the substrate temperature is heated to 700 ° C. in an atmosphere of hydrogen (H ₂ ) and arsine (AsH ₃ ).
[0049]
(2) Process:
The n-type GaAs buffer layer 11 is epitaxially grown at 640 ° C. by supplying TMG and arsine (AsH ₃ ) and using silane gas (SiH ₄ ) as a dopant gas. The concentration of the semiconductor impurity Si was 2 × 10 ¹⁸ atoms / cm ³ and the film thickness was 3 μm.
[0050]
(3) Process:
TMG and arsine gas (AsH ₃ ) are supplied, and the n ⁻ -type GaAs light absorption layer 12 is grown at 640 ° C. The film thickness is 1.5 μm. Although it is non-doped without impurities, it contains about 8 × 10 ¹³ atoms / cm ^{3 of} Si remaining on the reaction tube wall or C from organic matter as described above.
[0051]
(4) Process:
Next, TMG, trimethylaluminum (hereinafter referred to as TMA) and arsine gas (AsH ₃ ), which are group III source gases, are supplied, and the n ⁻ -type AlGaAs window layer 13 is grown at 640 ° C. The film thickness is 1 μm. The n ⁻ type AlGaAs window layer 13 is also non-doped without impurities as in the case of the n ⁻ type GaAs light absorption layer 12 described above, but 8 × 10 ¹³ atoms of Si remaining on the reaction tube wall, C from the organic matter, or the like. Contains about / cm ³ .
[0052]
(5) Process:
A mesa structure is formed using a sulfuric acid hydrogen peroxide based etching solution. Subsequently, etching is similarly performed using a sulfuric acid hydrogen peroxide etching solution so that a part of the n-type GaAs buffer layer 11 is exposed.
[0053]
(6) Process:
A selective diffusion mask pattern made of silicon nitride (SiNx) having a thickness of 8000 mm is formed on the n ⁻ -type AlGaAs window layer 13 using silane gas (SiH ₄ ) and ammonia (NH ₄ ) by plasma CVD. Thereafter, a sample is enclosed in a quartz ampule tube together with an ingot of zinc arsenic (ZnAs), and thermal diffusion is performed in a diffusion furnace to form a p ⁺ -type InP diffusion region. The diffusion temperature is 500 ° C.
[0054]
(7) Process:
After the diffusion in the previous step, the selective diffusion mask pattern is removed with hydrofluoric acid (HF), and the insulating film made of silicon nitride (SiN _x ) is again used with silane gas (SiH ₄ ) and ammonia (NH ₄ ) by the plasma CVD method. A film 15 is formed.
[0055]
(8) Process:
After that, the electrode 16a is formed with gold / gold / zinc (Au / AuZnl) and the electrode 16b with gold / gold / germanium (Au / AuGe) to a thickness of 2500 mm by vapor deposition or sputtering. Then, an electrode 16c is formed on the back surface of the substrate with gold / gold / zinc (Au / AuZn) to a thickness of 2500 mm.
[0056]
With respect to the semiconductor light-receiving device thus obtained, when a reverse bias voltage is applied to the electrode 16a and the electrode 16b in the same manner as shown in FIG. 7 using a light source having a wavelength of 850 nm, (2) the electrode 16a and the electrode 16b are applied. When the light receiving sensitivity was measured separately when the reverse bias voltage was applied to the electrodes 16c and 16b, the light receiving sensitivity was 0.58 A / W in the case of (1) of the same specification as the conventional technology. In contrast, in the case of (2), the light receiving sensitivity was improved to 0.60 A / W.
[0057]
【The invention's effect】
As described above, according to the semiconductor light receiving element of the present invention, the light absorption layer, the reverse conductivity type semiconductor layer, and the first conductive layer composed of the large-area one-conductive semiconductor layer, the small-area semiconductor layer on the semi-insulating semiconductor substrate. Are provided in order, and further, a second electrode is formed on the exposed surface of the one-conductivity-type semiconductor layer, a third electrode is formed on the back surface of the semiconductor substrate, and between the first electrode and the second electrode, By applying a voltage with a reverse bias between the second electrode and the third electrode, the light receiving sensitivity could be improved without making the light absorption layer thicker than necessary.
[0058]
In addition, the manufacturing cost is reduced by not complicating the manufacturing process, thereby providing a low-cost semiconductor light-receiving element.
[Brief description of the drawings]
FIG. 1 is a top view of a semiconductor light receiving element of the present invention.
FIG. 2 is a schematic cross-sectional view taken along a cutting plane line AA ′ in FIG.
FIG. 3 is a schematic cross-sectional view of a conventional semiconductor light receiving element.
FIG. 4 is a schematic cross-sectional view of another conventional semiconductor light receiving element.
FIG. 5 is an energy band diagram of the semiconductor light receiving element of the present invention.
FIG. 6 is an energy band diagram of a conventional semiconductor light receiving element.
FIG. 7 is an equivalent circuit diagram corresponding to a conventional element in the case of (1), and an equivalent circuit diagram corresponding to the element of the present invention in the case of (2).
[Explanation of symbols]
10 ... InP substrate 11, ... n-type InP buffer layer 12, ... n ^- -type InGaAs light absorbing layer 13, ... n ^- -type InP window layer 14 ... p ⁺ -type InP diffusion region 15 ... Insulating films 16a, 16b, 16c ... electrodes

Claims (1)

On the semi-insulating semiconductor substrate, a large-area one-conductivity-type semiconductor layer and a light-absorption layer composed of a small-area semiconductor layer are sequentially stacked, and the reverse-conductivity-type semiconductor layer and the first electrode are stacked on the light-absorption layer. Are further formed, and further, a second electrode is formed on the exposed surface of the one-conductivity-type semiconductor layer, a third electrode is formed on the back surface of the semiconductor substrate, and between the first electrode and the second electrode, A semiconductor light receiving element, wherein a voltage is applied between the second electrode and the third electrode with a reverse bias.

Images