JP4042749B2 - Manufacturing method of semiconductor device - Google Patents

Manufacturing method of semiconductor device Download PDF

Info

Publication number
JP4042749B2
JP4042749B2 JP2005043739A JP2005043739A JP4042749B2 JP 4042749 B2 JP4042749 B2 JP 4042749B2 JP 2005043739 A JP2005043739 A JP 2005043739A JP 2005043739 A JP2005043739 A JP 2005043739A JP 4042749 B2 JP4042749 B2 JP 4042749B2
Authority
JP
Japan
Prior art keywords
protective film
semiconductor substrate
film
silicon substrate
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP2005043739A
Other languages
Japanese (ja)
Other versions
JP2006229113A (en
Inventor
猛 若林
一郎 三原
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Casio Computer Co Ltd
Original Assignee
Casio Computer Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Casio Computer Co Ltd filed Critical Casio Computer Co Ltd
Priority to JP2005043739A priority Critical patent/JP4042749B2/en
Priority to US11/349,779 priority patent/US7390688B2/en
Priority to KR1020060016111A priority patent/KR100763079B1/en
Priority to TW095105557A priority patent/TWI322468B/en
Priority to CN2006100087000A priority patent/CN1825590B/en
Publication of JP2006229113A publication Critical patent/JP2006229113A/en
Application granted granted Critical
Publication of JP4042749B2 publication Critical patent/JP4042749B2/en
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Description

この発明は半導体装置の製造方法に関する。 The present invention relates to a method of manufacturing a semiconductor device.

従来の半導体装置の製造方法には、半導体基板の厚さを薄くするため、ウエハ状態の半導体基板の裏面を研削し、ウエハ状態の半導体基板の裏面に樹脂からなる保護膜を形成し、所定の工程を経た後に、ウエハ状態の半導体基板などを切断して複数個の半導体装置を得るようにした方法がある（例えば、特許文献１参照）。   In the conventional method of manufacturing a semiconductor device, in order to reduce the thickness of the semiconductor substrate, the back surface of the semiconductor substrate in the wafer state is ground, and a protective film made of resin is formed on the back surface of the semiconductor substrate in the wafer state. There is a method in which a plurality of semiconductor devices are obtained by cutting a semiconductor substrate in a wafer state after the process (see, for example, Patent Document 1).

特開２００１−２３０２２４号公報Japanese Patent Laid-Open No. 2001-230224

ところで、上記従来の製造方法により得られた半導体装置では、半導体基板の裏面を研削すると、半導体基板の裏面に微細で鋭角な凸凹が形成され、この微細で鋭角な凸凹面に樹脂からなる保護膜を形成しても、微細で鋭角な凹部の奥にまで樹脂を確実に充填することが難しく、微細で鋭角な凹部の奥が保護膜で覆われていないことに起因して、半導体基板の裏面にクラックが発生するおそれがあるという問題がある。また、半導体基板の裏面に保護膜が形成されているが、半導体基板の側面が露出されているので、半導体基板の側面にクラックが発生しやすいという問題がある。   By the way, in the semiconductor device obtained by the above-described conventional manufacturing method, when the back surface of the semiconductor substrate is ground, fine and acute unevenness is formed on the back surface of the semiconductor substrate, and the protective film made of resin is formed on the fine and acute uneven surface. Even if formed, it is difficult to reliably fill the resin into the back of the fine and sharp recess, and the back of the semiconductor substrate is caused by the fact that the back of the fine and sharp recess is not covered with a protective film. There is a problem that cracks may occur. Moreover, although the protective film is formed in the back surface of the semiconductor substrate, since the side surface of the semiconductor substrate is exposed, there is a problem that cracks are likely to occur on the side surface of the semiconductor substrate.

そこで、この発明は、半導体基板の裏面および側面にクラックが発生しにくいようにすることができる半導体装置の製造方法を提供することを目的とする。 In view of the above, an object of the present invention is to provide a method for manufacturing a semiconductor device capable of preventing cracks from being easily generated on the back and side surfaces of a semiconductor substrate.

この発明は上記目的を達成するため、ウエハ状態の半導体基板上に柱状電極を形成する工程と、前記柱状電極の周囲における前記ウエハ状態の半導体基板上に封止膜を形成する工程と、前記ウエハ状態の半導体基板の裏面を研削する工程と、前記ウエハ状態の半導体基板の裏面側から前記封止膜の少なくとも途中までカットして各半導体基板に分離するための溝を形成する工程と、前記各半導体基板の微細で鋭角な凸凹の裏面および側面をウェットエッチングにより粗面化する工程と、前記溝内を含む前記各半導体基板の裏面に保護膜を形成する工程と、前記溝内に形成された前記保護膜を切断して複数個の半導体装置を得る工程とを有することを特徴とするものである。 To achieve the above object, the present invention provides a step of forming a columnar electrode on a semiconductor substrate in a wafer state, a step of forming a sealing film on the semiconductor substrate in the wafer state around the columnar electrode, and the wafer Grinding the back surface of the semiconductor substrate in the state, forming a groove for cutting at least partway of the sealing film from the back surface side of the semiconductor substrate in the wafer state and separating the semiconductor substrate, A step of roughening the back and side surfaces of the fine and acute irregularities of the semiconductor substrate by wet etching, a step of forming a protective film on the back surface of each semiconductor substrate including the inside of the groove, and a step formed in the groove And cutting the protective film to obtain a plurality of semiconductor devices .

この発明によれば、半導体基板の裏面および側面を粗面としているので、この粗面を保護膜で確実に覆うことができ、したがって半導体基板の裏面および側面にクラックが発生しにくいようにすることができる。   According to this invention, since the back surface and side surface of the semiconductor substrate are rough surfaces, the rough surface can be reliably covered with the protective film, and therefore, the back surface and side surfaces of the semiconductor substrate are not easily cracked. Can do.

図１はこの発明の一実施形態としての半導体装置の断面図を示す。この半導体装置は、一般的にはＣＳＰ(chip size package)と呼ばれるものであり、シリコン基板（半導体基板）１を備えている。シリコン基板１の上面には所定の機能の集積回路（図示せず）が設けられ、上面周辺部にはアルミニウム系金属などからなる複数の接続パッド２が集積回路に接続されて設けられている。   FIG. 1 is a sectional view of a semiconductor device as an embodiment of the present invention. This semiconductor device is generally called a CSP (chip size package) and includes a silicon substrate (semiconductor substrate) 1. An integrated circuit (not shown) having a predetermined function is provided on the upper surface of the silicon substrate 1, and a plurality of connection pads 2 made of aluminum-based metal or the like are provided on the periphery of the upper surface so as to be connected to the integrated circuit.

接続パッド２の中央部を除くシリコン基板１の上面には酸化シリコンなどからなる絶縁膜３が設けられ、接続パッド２の中央部は絶縁膜３に設けられた開口部４を介して露出されている。絶縁膜３の上面にはエポキシ系樹脂やポリイミド系樹脂などからなる保護膜５が設けられている。この場合、絶縁膜３の開口部４に対応する部分における保護膜５には開口部６が設けられている。   An insulating film 3 made of silicon oxide or the like is provided on the upper surface of the silicon substrate 1 excluding the central portion of the connection pad 2, and the central portion of the connection pad 2 is exposed through an opening 4 provided in the insulating film 3. Yes. A protective film 5 made of epoxy resin or polyimide resin is provided on the upper surface of the insulating film 3. In this case, an opening 6 is provided in the protective film 5 at a portion corresponding to the opening 4 of the insulating film 3.

保護膜５の上面には銅などからなる下地金属層７が設けられている。下地金属層７の上面全体には銅からなる配線８が設けられている。下地金属層７を含む配線８の一端部は、絶縁膜３および保護膜５の開口部４、６を介して接続パッド２に接続されている。配線８の接続パッド部上面には銅からなる柱状電極（外部接続用電極）９が設けられている。配線８を含む保護膜５の上面にはエポキシ系樹脂やポリイミド系樹脂などからなる封止膜１０がその上面が柱状電極９の上面と面一となるように設けられている。柱状電極９の上面には半田ボール１１が設けられている。   A base metal layer 7 made of copper or the like is provided on the upper surface of the protective film 5. A wiring 8 made of copper is provided on the entire upper surface of the base metal layer 7. One end of the wiring 8 including the base metal layer 7 is connected to the connection pad 2 through the openings 4 and 6 of the insulating film 3 and the protective film 5. A columnar electrode (external connection electrode) 9 made of copper is provided on the upper surface of the connection pad portion of the wiring 8. A sealing film 10 made of an epoxy resin or a polyimide resin is provided on the upper surface of the protective film 5 including the wiring 8 so that the upper surface is flush with the upper surface of the columnar electrode 9. A solder ball 11 is provided on the upper surface of the columnar electrode 9.

シリコン基板１の周側面、絶縁膜３の周側面、保護膜５の周側面および封止膜１０の周側面下部には溝１２が設けられている。溝１２内を含むシリコン基板１の下面（裏面）にはエポキシ系樹脂やポリイミド系樹脂などからなる保護膜１３が設けられている。この場合、保護膜１３の周側面と封止膜１０の周側面上部とは面一となっている。   Grooves 12 are provided on the peripheral side surface of the silicon substrate 1, the peripheral side surface of the insulating film 3, the peripheral side surface of the protective film 5, and the lower part of the peripheral side surface of the sealing film 10. A protective film 13 made of epoxy resin or polyimide resin is provided on the lower surface (back surface) of the silicon substrate 1 including the inside of the groove 12. In this case, the peripheral side surface of the protective film 13 and the upper peripheral side surface of the sealing film 10 are flush with each other.

次に、この半導体装置の製造方法の一例について説明する。まず、図２に示すように、ウエハ状態のシリコン基板（半導体基板）１上にアルミニウム系金属などからなる接続パッド２、酸化シリコンなどからなる絶縁膜３およびエポキシ系樹脂やポリイミド系樹脂などからなる保護膜５が設けられ、接続パッド２の中央部が絶縁膜３および保護膜５に形成された開口部４、６を介して露出されたものを用意する。   Next, an example of a method for manufacturing this semiconductor device will be described. First, as shown in FIG. 2, on a silicon substrate (semiconductor substrate) 1 in a wafer state, a connection pad 2 made of an aluminum metal, an insulating film 3 made of silicon oxide, an epoxy resin, a polyimide resin, or the like. A protective film 5 is provided, and the connection pad 2 is exposed through the openings 4 and 6 formed in the insulating film 3 and the protective film 5.

この場合、ウエハ状態のシリコン基板１には、各半導体装置が形成される領域に所定の機能の集積回路が形成され、接続パッド２は、それぞれ、対応する領域に形成された集積回路に電気的に接続されている。また、ウエハ状態のシリコン基板１の厚さは、図１に示すシリコン基板１の厚さよりもある程度厚くなっている。なお、図２において、符号２１で示す領域は第１のダイシングストリートに対応する領域であり、符号２２で示す領域は第２のダイシングストリートに対応する領域である。この場合、第２のダイシングストリート２２は、第１のダイシングストリート２１の幅方向中央部に対応する領域となっている。   In this case, on the silicon substrate 1 in the wafer state, an integrated circuit having a predetermined function is formed in a region where each semiconductor device is formed, and the connection pad 2 is electrically connected to the integrated circuit formed in the corresponding region. It is connected to the. Further, the thickness of the silicon substrate 1 in the wafer state is somewhat larger than the thickness of the silicon substrate 1 shown in FIG. In FIG. 2, an area indicated by reference numeral 21 is an area corresponding to the first dicing street, and an area indicated by reference numeral 22 is an area corresponding to the second dicing street. In this case, the second dicing street 22 is a region corresponding to the central portion in the width direction of the first dicing street 21.

次に、図３に示すように、絶縁膜３および保護膜５の開口部４、６を介して露出された接続パッド２の上面を含む保護膜５の上面全体に下地金属層７を形成する。この場合、下地金属層７は、無電解メッキにより形成された銅層のみであってもよく、またスパッタにより形成された銅層のみであってもよく、さらにスパッタにより形成されたチタンなどの薄膜層上にスパッタにより銅層を形成したものであってもよい。   Next, as shown in FIG. 3, a base metal layer 7 is formed on the entire upper surface of the protective film 5 including the upper surfaces of the connection pads 2 exposed through the openings 4 and 6 of the insulating film 3 and the protective film 5. . In this case, the base metal layer 7 may be only a copper layer formed by electroless plating, or may be only a copper layer formed by sputtering, and a thin film such as titanium formed by sputtering. A copper layer may be formed on the layer by sputtering.

次に、下地金属層７の上面にメッキレジスト膜２３をパターン形成する。この場合、配線８形成領域に対応する部分におけるメッキレジスト膜２３には開口部２４が形成されている。次に、下地金属層７をメッキ電流路として銅の電解メッキを行なうことにより、メッキレジスト膜２３の開口部２４内の下地金属層７の上面に配線８を形成する。次に、メッキレジスト膜２３を剥離する。   Next, a plating resist film 23 is pattern-formed on the upper surface of the base metal layer 7. In this case, an opening 24 is formed in the plating resist film 23 in a portion corresponding to the wiring 8 formation region. Next, by performing electrolytic plating of copper using the base metal layer 7 as a plating current path, the wiring 8 is formed on the upper surface of the base metal layer 7 in the opening 24 of the plating resist film 23. Next, the plating resist film 23 is peeled off.

次に、図４に示すように、配線８を含む下地金属層７の上面にメッキレジスト膜２５をパターン形成する。この場合、柱状電極９形成領域に対応する部分におけるメッキレジスト膜２５には開口部２６が形成されている。次に、下地金属層７をメッキ電流路として銅の電解メッキを行なうことにより、メッキレジスト膜２５の開口部２６内の配線８の接続パッド部上面に柱状電極９を形成する。次に、メッキレジスト膜２５を剥離し、次いで、配線８をマスクとして下地金属層７の不要な部分をエッチングして除去すると、図５に示すように、配線８下にのみ下地金属層７が残存される。   Next, as shown in FIG. 4, a plating resist film 25 is formed on the upper surface of the base metal layer 7 including the wiring 8. In this case, an opening 26 is formed in the plating resist film 25 in a portion corresponding to the columnar electrode 9 formation region. Next, the columnar electrode 9 is formed on the upper surface of the connection pad portion of the wiring 8 in the opening 26 of the plating resist film 25 by performing electrolytic plating of copper using the base metal layer 7 as a plating current path. Next, when the plating resist film 25 is peeled off, and then unnecessary portions of the base metal layer 7 are removed by etching using the wiring 8 as a mask, the base metal layer 7 is formed only under the wiring 8 as shown in FIG. Remain.

次に、図６に示すように、柱状電極９および配線８を含む保護膜５の上面全体に、スクリーン印刷法やスピンコート法などにより、エポキシ系樹脂やポリイミド系樹脂などからなる封止膜１０をその厚さが柱状電極９の高さよりも厚くなるように形成する。したがって、この状態では、柱状電極９の上面は封止膜１０によって覆われている。   Next, as shown in FIG. 6, a sealing film 10 made of an epoxy resin, a polyimide resin, or the like is formed on the entire upper surface of the protective film 5 including the columnar electrodes 9 and the wirings 8 by a screen printing method, a spin coating method, or the like. Is formed so that the thickness thereof is greater than the height of the columnar electrode 9. Therefore, in this state, the upper surface of the columnar electrode 9 is covered with the sealing film 10.

次に、封止膜１０および柱状電極９の上面側を適宜に研磨し、図７に示すように、柱状電極９の上面を露出させ、且つ、この露出された柱状電極９の上面を含む封止膜１０の上面を平坦化する。ここで、柱状電極９の上面側を適宜に研磨するのは、電解メッキにより形成される柱状電極９の高さにばらつきがあるため、このばらつきを解消して、柱状電極９の高さを均一にするためである。   Next, the upper surface side of the sealing film 10 and the columnar electrode 9 is appropriately polished to expose the upper surface of the columnar electrode 9 and to include the exposed upper surface of the columnar electrode 9 as shown in FIG. The upper surface of the stop film 10 is flattened. Here, the reason for appropriately polishing the upper surface side of the columnar electrode 9 is that the height of the columnar electrode 9 formed by electrolytic plating varies, so that this variation is eliminated and the height of the columnar electrode 9 is made uniform. It is to make it.

次に、図８に示すように、シリコン基板１の厚さを薄くするため、シリコン基板１の下面（裏面）側を適宜に研削する。次に、図９に示すように、第１のダイシングストリート２１に沿って、ダイシング法により、シリコン基板１の下面側から封止膜１０の途中までハーフカットし、すなわち、シリコン基板１、絶縁膜３および保護膜５をフルカットし、且つ、封止膜１０をハーフカットし、溝１２を形成する。この状態では、ウエハ状態のシリコン基板１は個々のシリコン基板１に分離されるが、封止膜１０がハーフカットされているため、各シリコン基板１は実質的には分離されていない。このハーフカット加工は、ダイシングテープ（図示せず）に封止膜１０および柱状電極９の上面を貼着した状態で行ってもよい。   Next, as shown in FIG. 8, in order to reduce the thickness of the silicon substrate 1, the lower surface (back surface) side of the silicon substrate 1 is appropriately ground. Next, as shown in FIG. 9, along the first dicing street 21, half cutting is performed from the lower surface side of the silicon substrate 1 to the middle of the sealing film 10 by the dicing method, that is, the silicon substrate 1 and the insulating film. 3 and the protective film 5 are fully cut, and the sealing film 10 is half-cut to form the grooves 12. In this state, the silicon substrate 1 in the wafer state is separated into individual silicon substrates 1, but since the sealing film 10 is half-cut, the silicon substrates 1 are not substantially separated. This half-cut processing may be performed in a state where the sealing film 10 and the upper surfaces of the columnar electrodes 9 are adhered to a dicing tape (not shown).

ここで、ウエハ状態のシリコン基板１の下面を研削したり、ウエハ状態のシリコン基板１をダイシングしたりすると、図９のＡ部を詳細に示す部分拡大断面図である図１０に示すように、シリコン基板１の下面および周側面に微細で鋭角な凸凹（シリコンの結晶破壊層）２７が形成される。この微細で鋭角な凸凹２７は、シリコン基板１の下面および周側面にクラックが発生する要因となる。   Here, when the lower surface of the silicon substrate 1 in the wafer state is ground or the silicon substrate 1 in the wafer state is diced, as shown in FIG. Fine and acute irregularities (silicon crystal breakdown layer) 27 are formed on the lower surface and peripheral side surface of the silicon substrate 1. The fine and acute irregularities 27 cause cracks on the lower surface and the peripheral side surface of the silicon substrate 1.

そこで、次に、硝酸−フッ酸−酢酸の混合溶液またはこれに水を加えた混合溶液を用いたウェットエッチングを行なう。このウェットエッチングでは、硝酸でシリコン基板１の下面および周側面を酸化させて酸化膜を形成し、フッ酸でこの酸化膜を溶解して除去し、酢酸で反応を制御することになる。この場合、混合溶液の組成比や処理時間などの条件により、シリコン基板１の下面および周側面を鏡面仕上げとすることもできるが、シリコン基板１が光の影響を受けにくいようにするために、図１１に示すように、シリコン基板１の下面および周側面を段差１〜５μｍの粗面仕上げとする方が好ましい。   Therefore, next, wet etching is performed using a mixed solution of nitric acid-hydrofluoric acid-acetic acid or a mixed solution obtained by adding water. In this wet etching, the lower surface and peripheral side surface of the silicon substrate 1 are oxidized with nitric acid to form an oxide film, the oxide film is dissolved and removed with hydrofluoric acid, and the reaction is controlled with acetic acid. In this case, depending on conditions such as the composition ratio of the mixed solution and the processing time, the lower surface and the peripheral side surface of the silicon substrate 1 can be mirror finished, but in order to make the silicon substrate 1 less susceptible to light, As shown in FIG. 11, it is preferable that the bottom surface and the peripheral side surface of the silicon substrate 1 have a rough surface finish with steps of 1 to 5 μm.

次に、図１２に示すように、溝１２内を含むシリコン基板１の下面に、スクリーン印刷法やスピンコート法などにより、エポキシ系樹脂やポリイミド系樹脂などからなる保護膜１３をその下面が平坦となるように形成する。この状態では、溝１２内におけるシリコン基板１、絶縁膜３、保護膜５および封止膜１０の周側面は、溝１２内に形成された保護膜１３によって覆われている。この場合、特に、シリコン基板１の下面および周側面は、図１１に示すように、段差１〜５μｍの粗面となっているので、この粗面は保護膜１３によって確実に覆われる。また、シリコン基板１は個々に分離されているので、エポキシ系樹脂などからなる保護膜１３が硬化収縮しても、シリコン基板１が反りにくいようにすることができる。   Next, as shown in FIG. 12, a protective film 13 made of an epoxy resin or a polyimide resin is flattened on the lower surface of the silicon substrate 1 including the inside of the groove 12 by screen printing or spin coating. It forms so that it becomes. In this state, the peripheral side surfaces of the silicon substrate 1, the insulating film 3, the protective film 5, and the sealing film 10 in the groove 12 are covered with the protective film 13 formed in the groove 12. In this case, in particular, since the lower surface and the peripheral side surface of the silicon substrate 1 are rough surfaces with a step of 1 to 5 μm as shown in FIG. 11, the rough surface is reliably covered with the protective film 13. Further, since the silicon substrates 1 are individually separated, even if the protective film 13 made of an epoxy resin or the like is cured and contracted, the silicon substrate 1 can be prevented from warping.

次に、柱状電極９の上面に半田ボール１１を形成する。次に、保護膜１３を図示しないダイシングテープに貼着した状態で、図１３に示すように、第２のダイシングストリート２２に沿って、すなわち、溝１２内に形成された保護膜１３の幅方向中央部に沿って、ダイシング法により、保護膜１３および封止膜１０をフルカットすると、図１に示す半導体装置が複数個得られる。   Next, a solder ball 11 is formed on the upper surface of the columnar electrode 9. Next, with the protective film 13 attached to a dicing tape (not shown), the width direction of the protective film 13 formed along the second dicing street 22, that is, in the groove 12, as shown in FIG. 13. When the protective film 13 and the sealing film 10 are fully cut along the center by a dicing method, a plurality of semiconductor devices shown in FIG. 1 are obtained.

このようにして得られた半導体装置では、図１１に示すように、シリコン基板１の下面および周側面を段差１〜５μｍの粗面としているので、この粗面を保護膜１３で確実に覆うことができ、したがってシリコン基板１の下面および周側面にクラックが発生しにくいようにすることができる。   In the semiconductor device obtained in this way, as shown in FIG. 11, the lower surface and the peripheral side surface of the silicon substrate 1 are rough surfaces with steps of 1 to 5 μm, so that the rough surface is reliably covered with the protective film 13. Therefore, it is possible to make it difficult for cracks to occur on the lower surface and the peripheral side surface of the silicon substrate 1.

なお、保護膜１３は、樹脂ではなく、金属によって形成するようにしてもよい。金属材料としては、シリコン基板１との密着性が良く、機械的強度が高いものであればよく、一例を挙げればチタンなどである。そして、図１１に示す工程後に、図１２を参照して説明すると、溝１２内を含むシリコン基板１の下面に、スパッタ法などにより、チタンからなる保護膜１３を膜厚１５００Å程度に形成する。この場合、実際には、図１２の点線で示すように、保護膜１３は溝１２の側面および底面からほぼ均一な厚さに形成される。チタンなどの金属膜からなる保護膜１３には樹脂のような硬化収縮が発生しないので、シリコン基板１に反りが発生しないようにすることができる。   In addition, you may make it form the protective film 13 with a metal instead of resin. The metal material may be any metal material that has good adhesion to the silicon substrate 1 and high mechanical strength. For example, titanium is used. 11, the protective film 13 made of titanium is formed to a thickness of about 1500 mm on the lower surface of the silicon substrate 1 including the inside of the trench 12 by sputtering or the like. In this case, actually, as shown by the dotted line in FIG. 12, the protective film 13 is formed with a substantially uniform thickness from the side surface and the bottom surface of the groove 12. Since the protective film 13 made of a metal film such as titanium does not cause curing shrinkage like resin, it is possible to prevent the silicon substrate 1 from warping.

また、上記実施形態では、溝１２をシリコン基板１の下面側から封止膜１０の途中までハーフカットして形成するものであったが、図８において、ダイシングテープ（図示せず）に封止膜１０および柱状電極９の上面を貼着しておけば、シリコン基板１および封止膜１０をフルカットすることもできる。その場合、その後の工程は、上記実施形態と同様に行うことができるが、溝内に対応するダイシングテープ上に形成された保護膜のみを切断することにより、個々の半導体装置とすることもできる。   Moreover, in the said embodiment, although the groove | channel 12 was formed by half-cutting from the lower surface side of the silicon substrate 1 to the middle of the sealing film 10, in FIG. 8, it seals with a dicing tape (not shown). If the upper surfaces of the film 10 and the columnar electrode 9 are attached, the silicon substrate 1 and the sealing film 10 can be fully cut. In that case, the subsequent steps can be performed in the same manner as in the above embodiment, but by cutting only the protective film formed on the dicing tape corresponding to the inside of the groove, individual semiconductor devices can be obtained. .

さらに、この発明は、ＣＳＰと呼ばれる半導体装置に限らず、例えば、絶縁膜３の開口部４を介して露出された接続パッド２上に下地金属層および柱状電極を形成し、柱状電極の周囲における絶縁膜３上に封止膜を形成し、柱状電極上に半田ボールを形成した半導体装置にも適用することができる。   Further, the present invention is not limited to the semiconductor device called CSP, and for example, a base metal layer and a columnar electrode are formed on the connection pad 2 exposed through the opening 4 of the insulating film 3, and the periphery of the columnar electrode is formed. The present invention can also be applied to a semiconductor device in which a sealing film is formed on the insulating film 3 and solder balls are formed on columnar electrodes.

この発明の一実施形態としての半導体装置の断面図。1 is a cross-sectional view of a semiconductor device as an embodiment of the present invention. 図１に示す半導体装置の製造方法の一例において、当初用意したものの断面 図。Sectional drawing of what was prepared initially in an example of the manufacturing method of the semiconductor device shown in FIG. 図２に続く工程の断面図。Sectional drawing of the process following FIG. 図３に続く工程の断面図。Sectional drawing of the process following FIG. 図４に続く工程の断面図。Sectional drawing of the process following FIG. 図５に続く工程の断面図。Sectional drawing of the process following FIG. 図６に続く工程の断面図。Sectional drawing of the process following FIG. 図７に続く工程の断面図。Sectional drawing of the process following FIG. 図８に続く工程の断面図。FIG. 9 is a cross-sectional view of the process following FIG. 8. 図９のＡ部を詳細に示す部分拡大断面図。The partial expanded sectional view which shows the A section of FIG. 9 in detail. 図１０に続く工程の部分拡大断面図。FIG. 11 is a partial enlarged cross-sectional view of the process following FIG. 10. 図１１に続く工程の断面図。Sectional drawing of the process following FIG. 図１２に続く工程の断面図。Sectional drawing of the process following FIG.

符号の説明Explanation of symbols

１ シリコン基板
２ 接続パッド
３ 絶縁膜
５ 保護膜
７ 下地金属層
８ 配線
９ 柱状電極（外部接続用電極）
１０ 封止膜
１１ 半田ボール
１２ 溝
１３ 保護膜
２１、２２ ダイシングストリート DESCRIPTION OF SYMBOLS 1 Silicon substrate 2 Connection pad 3 Insulating film 5 Protective film 7 Base metal layer 8 Wiring 9 Columnar electrode (electrode for external connection)
10 Sealing film 11 Solder ball 12 Groove 13 Protective film 21, 22 Dicing street

Claims (4)

ウエハ状態の半導体基板上に柱状電極を形成する工程と、前記柱状電極の周囲における前記ウエハ状態の半導体基板上に封止膜を形成する工程と、前記ウエハ状態の半導体基板の裏面を研削する工程と、前記ウエハ状態の半導体基板の裏面側から前記封止膜の少なくとも途中までカットして各半導体基板に分離するための溝を形成する工程と、前記各半導体基板の微細で鋭角な凸凹の裏面および側面をウェットエッチングにより粗面化する工程と、前記溝内を含む前記各半導体基板の裏面に保護膜を形成する工程と、前記溝内に形成された前記保護膜を切断して複数個の半導体装置を得る工程とを有することを特徴とする半導体装置の製造方法。   Forming a columnar electrode on the semiconductor substrate in a wafer state, forming a sealing film on the semiconductor substrate in the wafer state around the columnar electrode, and grinding a back surface of the semiconductor substrate in the wafer state And forming a groove for cutting at least part of the sealing film from the back surface side of the semiconductor substrate in the wafer state to separate each semiconductor substrate, and the back surface of each semiconductor substrate having a fine, sharp and uneven surface And a step of roughening the side surface by wet etching, a step of forming a protective film on the back surface of each semiconductor substrate including the inside of the groove, and a plurality of cutting the protective film formed in the groove And a method of manufacturing a semiconductor device. 請求項１に記載の発明において、前記保護膜は樹脂によって形成することを特徴とする半導体装置の製造方法。 2. The method of manufacturing a semiconductor device according to claim 1 , wherein the protective film is formed of a resin. 請求項１に記載の発明において、前記保護膜は金属によって形成することを特徴とする半導体装置の製造方法。 2. The method of manufacturing a semiconductor device according to claim 1 , wherein the protective film is made of metal. 請求項１に記載の発明において、前記粗面は段差１〜５μｍであることを特徴とする半導体装置の製造方法。 2. The method of manufacturing a semiconductor device according to claim 1, wherein the rough surface has a level difference of 1 to 5 [mu] m.
JP2005043739A 2005-02-21 2005-02-21 Manufacturing method of semiconductor device Expired - Fee Related JP4042749B2 (en)

Priority Applications (5)

Application Number Priority Date Filing Date Title
JP2005043739A JP4042749B2 (en) 2005-02-21 2005-02-21 Manufacturing method of semiconductor device
US11/349,779 US7390688B2 (en) 2005-02-21 2006-02-08 Semiconductor device and manufacturing method thereof
KR1020060016111A KR100763079B1 (en) 2005-02-21 2006-02-20 Semiconductor device and manufacturing method thereof
TW095105557A TWI322468B (en) 2005-02-21 2006-02-20 Semiconductor device and manufacturing method thereof
CN2006100087000A CN1825590B (en) 2005-02-21 2006-02-21 Semiconductor device and manufacturing method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2005043739A JP4042749B2 (en) 2005-02-21 2005-02-21 Manufacturing method of semiconductor device

Publications (2)

Publication Number Publication Date
JP2006229113A JP2006229113A (en) 2006-08-31
JP4042749B2 true JP4042749B2 (en) 2008-02-06

Family

ID=36990175

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2005043739A Expired - Fee Related JP4042749B2 (en) 2005-02-21 2005-02-21 Manufacturing method of semiconductor device

Country Status (1)

Country Link
JP (1) JP4042749B2 (en)

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100738730B1 (en) 2005-03-16 2007-07-12 야마하 가부시키가이샤 Semiconductor device production method and semiconductor
JP4497112B2 (en) * 2005-05-18 2010-07-07 ヤマハ株式会社 Manufacturing method of semiconductor device
JP2008084918A (en) * 2006-09-26 2008-04-10 Casio Comput Co Ltd Method of forming mark of semiconductor device
JP4922891B2 (en) 2006-11-08 2012-04-25 株式会社テラミクロス Semiconductor device and manufacturing method thereof
JP5437626B2 (en) * 2007-12-28 2014-03-12 株式会社半導体エネルギー研究所 Semiconductor device and manufacturing method of semiconductor device
EP2075840B1 (en) * 2007-12-28 2014-08-27 Semiconductor Energy Laboratory Co., Ltd. Method for dicing a wafer with semiconductor elements formed thereon and corresponding device
JP5115295B2 (en) * 2008-04-11 2013-01-09 株式会社デンソー Semiconductor device and manufacturing method thereof
JP4538764B2 (en) * 2008-07-24 2010-09-08 カシオ計算機株式会社 Semiconductor device and manufacturing method thereof
JP4725639B2 (en) * 2008-12-09 2011-07-13 カシオ計算機株式会社 Manufacturing method of semiconductor device
JP4725638B2 (en) * 2008-12-09 2011-07-13 カシオ計算機株式会社 Manufacturing method of semiconductor device
JP4742252B2 (en) * 2008-12-10 2011-08-10 カシオ計算機株式会社 Manufacturing method of semiconductor device
CN102709199B (en) * 2011-03-28 2015-04-01 华东科技股份有限公司 Mold array process method for covering side edge of substrate
CN102709198A (en) * 2011-03-28 2012-10-03 华东科技股份有限公司 Mold array process method for preventing periphery of substrate from being exposed

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002083839A (en) * 2000-06-30 2002-03-22 Nippon Avionics Co Ltd Flip chip mounting method and semiconductor chip
JP2002353347A (en) * 2001-05-24 2002-12-06 Oki Electric Ind Co Ltd Semiconductor device and method of manufacturing same
JP2003309228A (en) * 2002-04-18 2003-10-31 Oki Electric Ind Co Ltd Semiconductor device and manufacturing method therefor
JP4346333B2 (en) * 2003-03-26 2009-10-21 新光電気工業株式会社 Method for manufacturing multilayer circuit board incorporating semiconductor element
JP2005175327A (en) * 2003-12-15 2005-06-30 Matsushita Electric Ind Co Ltd Semiconductor device, and manufacturing method thereof
JP2006196701A (en) * 2005-01-13 2006-07-27 Oki Electric Ind Co Ltd Manufacturing method for semiconductor device

Also Published As

Publication number Publication date
JP2006229113A (en) 2006-08-31

Similar Documents

Publication Publication Date Title
JP4042749B2 (en) Manufacturing method of semiconductor device
KR100763079B1 (en) Semiconductor device and manufacturing method thereof
JP2006229112A (en) Semiconductor device and its fabrication process
KR100727519B1 (en) Semiconductor device packaged into chip size and manufacturing method thereof
JP2000068401A (en) Semiconductor device and manufacture thereof
JP4742252B2 (en) Manufacturing method of semiconductor device
JP2002231854A (en) Semiconductor device and its manufacturing method
JP2009302453A (en) Semiconductor device and method of manufacturing semiconductor device
JP2006080284A (en) Semiconductor device and manufacturing method thereof
JP2009088109A (en) Semiconductor device and method of manufacturing the same
JP2008130886A (en) Manufacturing method of semiconductor device
JP2004349610A (en) Semiconductor device and its manufacturing method
JP4492621B2 (en) Semiconductor device and manufacturing method thereof
JP2005064473A (en) Semiconductor device and manufacturing method for the same
JP5603191B2 (en) Manufacturing method of semiconductor device
JP4506168B2 (en) Semiconductor device and its mounting structure
JP2008244132A (en) Semiconductor device, and manufacturing method therefor
JP5095991B2 (en) Manufacturing method of semiconductor device
JP3917121B2 (en) Manufacturing method of semiconductor device
JP2005093652A (en) Semiconductor device
JP2004327724A (en) Semiconductor device and manufacturing method therefor
JP2010147358A (en) Method of manufacturing semiconductor device
JP2010147293A (en) Method of manufacturing semiconductor device
JP2005038979A (en) Manufacturing method of semiconductor device
JP2001077145A (en) Semiconductor device manufacturing method

Legal Events

Date Code Title Description
A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20070720

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20070731

A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20070928

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20071023

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20071105

R150 Certificate of patent or registration of utility model

Free format text: JAPANESE INTERMEDIATE CODE: R150

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20101122

Year of fee payment: 3

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20101122

Year of fee payment: 3

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20111122

Year of fee payment: 4

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20111122

Year of fee payment: 4

S111 Request for change of ownership or part of ownership

Free format text: JAPANESE INTERMEDIATE CODE: R313111

R350 Written notification of registration of transfer

Free format text: JAPANESE INTERMEDIATE CODE: R350

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20121122

Year of fee payment: 5

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20121122

Year of fee payment: 5

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20131122

Year of fee payment: 6

LAPS Cancellation because of no payment of annual fees