JP4039091B2

JP4039091B2 - Multilayer capacitor

Info

Publication number: JP4039091B2
Application number: JP2002074425A
Authority: JP
Inventors: 豊島原
Original assignee: Murata Manufacturing Co Ltd
Current assignee: Murata Manufacturing Co Ltd
Priority date: 2002-03-18
Filing date: 2002-03-18
Publication date: 2008-01-30
Anticipated expiration: 2022-03-18
Also published as: JP2003272946A

Description

【０００１】
【発明の属する技術分野】
この発明は、積層コンデンサに関し、特に、たとえば主に高耐圧が要求される中高圧タイプの積層コンデンサに関する。
【０００２】
【従来の技術】
近年、電子機器の小型化、面実装化によって、積層コンデンサの小型、高容量化が進んでいる。このような流れは中高圧コンデンサ市場にも波及しており、たとえば液晶ディスプレーのバックライト用、スイッチング電源用などの高耐電圧を必要とするコンデンサの分野において、より小型で低コストな積層コンデンサが求められている。
【０００３】
積層コンデンサ１を小型化、高耐圧化するには、内部の高耐圧化、表面リークの防止、圧電歪破壊の防止という３つの問題を解決する必要がある。内部の高耐圧化のために、たとえば図６（Ａ）（Ｂ）（Ｃ）に示すように、誘電体で形成された積層体２の両端の外部電極３間を結ぶ方向に垂直な分割線を境界にして、対向する外部電極３に接続される内部電極４を複数に分割し、その分割部分の両側と重なるようにして隣接する内部電極５を形成した構造とすることが考えられる。ここで、内部電極５は外部電極３には接続されず、内部電極４の分割部分と異なる部分において、内部電極４の分割部分と平行となるように分割される。このような構造とすることにより、図６（Ｂ）に示すように、内部電極４と内部電極５との対向部分に、静電容量が形成される。したがって、対向する外部電極３間において複数の静電容量が形成され、これらの静電容量が直列に接続された構成となる。そのため、個々の静電容量に印加される電圧は低くなり、内部の高耐圧化を図ることができる。
【０００４】
ところで、積層コンデンサを構成する誘電体層として強誘電体材料が使用される場合は、ある程度圧電性も有するものである。そのため、積層コンデンサ１に高電圧を印加すると、誘電体層に圧電歪が発生し、積層コンデンサ１内に機械的応力が働いて破壊される。このような破壊は、電界に起因する電気的な破壊よりも早く起こる場合がある。
【０００５】
そこで、圧電歪破壊対策として、たとえば特開平９−１８０９５６号公報に開示され、図７に示されているように、内部電極により容量を得ている部分を積層方向に分割し、その分割部分に圧電歪による応力を緩和する中間層６を形成する方法が考えられている。この中間層６は、誘電体層と同じ材料で形成され、誘電体層よりも層の厚みを大きくすることにより、機械的応力が緩和され、圧電歪破壊を低減することができるものである。
【０００６】
【発明が解決しようとする課題】
しかしながら、上記中間層を設ける方法では、次のような問題があった。
すなわち、圧電歪による応力は積層数が増えるにしたがって大きくなるが、この応力を緩和するためには、中間層の厚みを大きくする、または、内部電極により容量を得ている部分の分割数を増やし中間層の数を増やすこととなる。
ところが、中間層は容量に寄与しない余分な層であり、中間層の厚みを大きくする場合および中間層の数を増やす場合のいずれの場合においても、積層体における余分な層の割合を増やすこととなるため、圧電歪による応力を十分に低減するとともに必要な容量を得ようとすると、積層体の厚みが大きくなりすぎてしまう。逆に、決められた寸法内で必要な容量を得ようとすると、必然的に中間層の数が少なくなる、または厚みが小さくなるため、それに伴って圧電歪による応力を低減する効果が小さくなる。
また、中間層の厚みを大きくする場合、積層数が少ない場合は、中間層において応力緩和が十分に行うことができるが、積層数が多くなってくると、中間層近傍では応力緩和ができても、中間層から離れるにしたがって応力緩和の効果が薄れるため、圧電歪による応力を低減する効果が小さい。
【０００７】
それゆえに、この発明の主たる目的は、高耐圧性を有し、かつ圧電歪による破壊を抑えることができる積層コンデンサを提供することである。
【０００８】
【課題を解決するための手段】
この発明は、対向する外部電極間を結ぶ方向と交差する分割線を境界として、同一平面上で少なくとも２分割されて、一方の外部電極と接続される第１の接続内部電極、他方の外部電極と接続される第２の接続内部電極とが形成されてなる第１の内部電極群と、第１の内部電極群の少なくとも２つとチタン酸バリウムを主成分とする誘電体層を介して重なるようにして配設され、対向する外部電極間を結ぶ分割線を境界として、同一平面上で少なくとも２分割されて、外部電極に接続されない複数の浮遊内部電極が形成されてなる第２の内部電極群とを有する積層体とを含み、第１の内部電極群を形成するための分割線と第２の内部電極群を形成するための分割線が重なることにより、積層体の積層方向に第１および第２の内部電極群が存在しない無電極領域が形成された、積層コンデンサである。
このような積層コンデンサにおいて、第１の内部電極群は、外部電極を結ぶ分割線を境界として同一平面上で少なくとも２分割されて形成されてもよい。
また、この発明は、対向する外部電極間を結ぶ方向と交差する分割線を境界として、同一平面上で少なくとも３分割されて、一方の外部電極と接続される第１の接続内部電極、他方の外部電極と接続される第２の接続内部電極、および第１の接続内部電極と第２の接続内部電極との間に位置する浮遊内部電極とが形成されてなる第１の内部電極群と、第１の内部電極群の少なくとも２つとチタン酸バリウムを主成分とする誘電体層を介して重なるようにして配設され、対向する外部電極間を結ぶ方向と交差する分割線を境界として、同一平面上で少なくとも２分割されて、外部電極に接続されない複数の浮遊内部電極が形成されてなる第２の内部電極群とを有する積層体を含み、第１の内部電極群または第２の内部電極群の少なくともどちらかが、対向する外部電極間を結ぶ分割線を境界として分割され、第１の内部電極群を形成するための分割線と第２の内部電極群を形成するための分割線が重なることにより、積層体の積層方向に第１および第２の内部電極群が存在しない無電極領域が形成された、積層コンデンサである。
このような積層コンデンサにおいて、第１の内部電極郡および第２の内部電極郡の両方が、対向する外部電極間を結ぶ分割線を境界として分割されて形成されてもよい。
また、第１の内部電極群の外部電極間を結ぶ分割線と外部電極を結ぶ方向と交差する分割線が同一平面上で交差する部分を囲む４つの第１の内部電極が、第２の内部電極群のうち１つの浮遊内部電極と共通に重なるように配置されてもよい。
さらに、第２の内部電極群の外部電極間を結ぶ分割線と外部電極を結ぶ方向と交差する分割線が同一平面上で交差する部分を囲む４つの第２の内部電極が、第１の内部電極群のうち１つの浮遊内部電極と共通に重なるように配置されてもよい。
これらの積層コンデンサにおいて、複数の第１の内部電極群と複数の第２の内部電極群とが、誘電体層を挟んで交互に積層されてもよい。
【０００９】
第１の内部電極群を形成するための分割線と、第２の内部電極群を形成するための分割線が重なることにより、積層体の積層方向にみて内部電極が存在しない無電極領域が形成される。そのため、この無電極領域には電界が印加されず、この部分に圧電歪が発生しない。それにより、内部電極間にある誘電体層に圧電歪が発生しても、内部電極の存在しない部分において機械的応力が緩和される。
また、第１の内部電極群の分割線と第２の内部電極群の分割線とが交差することにより、外部電極間において、複数の静電容量が直列および並列に接続された構造となる。そのため、外部電極間に高電圧が印加されても、個々の静電容量に印加される電圧は低くなり、全体として高い耐電圧性を得ることができる。
さらに、内部電極群の分割数を増やすことにより、複数の場所において、隣接する内部電極群の分割線が交差する。そのため、積層体の積層方向にみて、内部電極の存在しない無電極領域が多数形成される。したがって、積層体に発生する機械的応力を緩和する部分の数が多くなり、圧電歪によって破壊されにくい積層コンデンサを得ることができる。
このような積層コンデンサでは、第１の内部電極群と第２の内部電極群との積層数を調整することにより、全体としての静電容量を調整することができる。
【００１０】
この発明の上述の目的，その他の目的，特徴および利点は、図面を参照して行う以下の発明の実施の形態の詳細な説明から一層明らかとなろう。
【００１１】
【発明の実施の形態】
図１は、この発明の積層コンデンサの一例を示す斜視図である。積層コンデンサ１０は、積層体１２を含む。積層体１２は、図２（Ａ）（Ｂ）（Ｃ）に示すように、誘電体層１４、第１の内部電極群１６および第２の内部電極群１８の積層構造となるように形成される。第１の内部電極群１６は、第１、第２の接続内部電極１６ａ、１６ｂと、同一平面でその間に位置する浮遊内部電極１６ｃとからなる。また、第２の内部電極群１８は、浮遊内部電極１８ｃからなる。ここで、複数の第１の内部電極群１６と複数の第２の内部電極群１８とが、誘電体層１４を挟んで、互いに隣接するように交互に積層される。これらの積層数を調整することにより、積層コンデンサ１０全体の静電容量を調整することができる。積層体１２の対向端面には、それぞれ外部電極２０が形成される。そして、第１の内部電極群１６のうち両端に位置する第１および第２の接続内部電極１６ａ、１６ｂが、対向する外部電極２０に接続される。なお、第２の内部電極群１８は、外部電極２０には接続されない。
【００１２】
同一平面上に形成された第１の内部電極群１６は、図２（Ａ）に示すように、対向する外部電極２０間を結ぶ方向に交差する分割線を境界として４分割され、対向する外部電極２０間を結ぶ分割線を境界として３分割されることにより、同一平面上において、３個の第１の接続内部電極１６ａ、３個の第２の接続内部電極１６ｂ、６個の浮遊内部電極１６ｃに分割される。
【００１３】
また、第１の内部電極１６に重なって形成された第２の内部電極群１８は、対向する外部電極２０間を結ぶ分割線を境界として２分割され、対向する外部電極２０間を結ぶ方向に交差する分割線を境界として、３分割されることにより、同一平面上において、６個の浮遊内部電極１８ｃに分割される。
【００１４】
浮遊内部電極１８ｃのそれぞれは、第１の内部電極群１６において同一平面上で分割線が交差した十字部分を囲む４つの第１の内部電極１６を覆うように配置される。したがって、図２（Ａ）に示すように、積層体１２の積層方向にみて、第１の内部電極群１６の分割線と第２の内部電極群１８の分割線とが重なる場所に、どちらの内部電極も存在しない無電極領域２２が形成される。
【００１５】
また、第１の内部電極群１６が２つの外部電極２０間で縦横に１２分割され、第２の内部電極群１８が２つの外部電極２０間で縦横に６分割されている。そして、第２の内部電極群１８の各浮遊内部電極１８ｃが、第１の内部電極群１６の分割線が同一平面上で交差する部分を囲む第１、第２の接続内部電極１６ａ、１６ｂおよび浮遊内部電極１６ｃに重なるように配置されている。そのため、図２（Ｂ）（Ｃ）に示すように、第１の内部電極群１６と第２の内部電極群１８との対向部分に静電容量が形成され、これらの静電容量が直列および並列に接続される。したがって、図１および図２に示す積層コンデンサ１０では、図３に示すように、複数の静電容量が直並列接続された等価回路を有するものとなる。
【００１６】
この積層コンデンサ１０では、複数の静電容量が直並列接続された構成となっているため、２つの外部電極２０間に電圧が印加されても、個々の静電容量に印加される電圧は低くなる。そのため、積層体１２内部において、高い耐圧性を得ることができる。
【００１７】
また、積層体１２の積層方向にみて、無電極領域２２が複数形成されるため、これらの無電極領域２２には電界が印加されず、この領域においては圧電歪が発生しない。したがって、第１の内部電極群１６および第２の内部電極群１８が重なった部分において誘電体層１４に圧電歪が発生しても、無電極領域２２で機械的応力が緩和される。そのため、圧電歪による機械的応力によって基体１２が破壊されることを防止することができる。図６や図７に示す従来の積層コンデンサでは、内部電極形成部分の全体で圧電歪が発生するが、図１に示す積層コンデンサ１０では、内部電極形成部分に無電極領域２２が散在することにより、機械的応力が効果的に緩和される。
【００１８】
なお、第１の内部電極群１６および第２の内部電極群１８は、対向する外部電極２０間において、それぞれ縦横に少なくとも２分割されていればよい。これらの第１の内部電極群１６および第２の内部電極群１８がそれぞれ２分割された場合、図４に示すように、内部電極形成部分の中央部に１つの無電極領域２２が形成される。さらに、図５に示すように、対向する外部電極２０間を結ぶ方向に交差する分割線を境界として第１の内部電極群１６を３分割して第１、第２の接続内部電極１６ａ、１６ｂおよび浮遊内部電極１６ｃを形成し、第２の内部電極群１８を縦横に４分割して浮遊内部電極１８ｃを４個形成することにより、２つの無電極領域２２を形成することができる。また、図２（Ａ）に示すように、第１の内部電極群１６を１２分割し、第２の内部電極群１８を６分割することにより、７つの無電極領域２２を形成することができる。このように、第１の内部電極群１６および第２の内部電極群１８の分割数を増やすことによって、無電極領域２２の数も増加し、圧電歪が発生しない部分を散在させることができる。
【００１９】
【実施例】
まず、ＢａＴｉＯ₃ を主体とする誘電率３０００のＢ特性のコンデンサ材料粉末に、溶媒、有機バインダ、分散剤、可塑剤を加えてスラリーを作製し、成型機によってセラミックグリーンシートを形成した。得られたセラミックグリーンシートにＡｇ−Ｐｄを主体とした内部電極ペーストを所定のパターンで印刷した。
【００２０】
外層用セラミックグリーンシートを数枚積み重ね、続いて所定のパターンで内部電極ペーストを印刷した内層用セラミックグリーンシートを多層に積み重ね、最後に外層用セラミックグリーンシートを数枚積み重ねた。この積層体を加圧プレスしてプレス成型体を形成し、約４００℃で脱脂したのち、１２００〜１３００℃で焼成した。このようにして得られた焼結体の端面に電極を焼き付け、さらにその上にめっき製膜を行って、外部電極を形成した。
【００２１】
このような工程で、図２に示す構造を有する積層コンデンサと、図６に示す従来の構造を有する積層コンデンサとを作製した。これらの積層コンデンサは、隣接して積層される内部電極間の素子厚３０μｍであり、対向する外部電極間において、複数の静電容量を接続した等価回路を有するものである。
【００２２】
これらの積層コンデンサについて、外部電極間に直流電圧を印加して、内部欠陥の発生の有無を確認した。なお、圧電歪破壊は、内部破壊が外部まで至らなかったり、絶縁抵抗が低下しないことがあるため、外観や絶縁抵抗測定から判断できない場合がある。そのため、超音波探傷装置により内部欠陥を観察する方法で評価を行った。このとき、直流電圧を０．５ｋＶずつ昇圧して積層コンデンサに印加し、超音波探傷による欠陥検査を行って、どれ位の電圧で圧電歪破壊が生じるかを評価した。そして、その結果を表１に示した。
【００２３】
【表１】

【００２４】
表１から、本発明の積層コンデンサは、従来の構造の積層コンデンサに比べて、圧電歪による内部破壊電圧が高いことが確認された。これは、圧電歪の発生しない部分、つまり内部電極のない無電極領域が、従来の積層コンデンサでは、基体の両側部のみに存在するのに対して、本発明の積層コンデンサでは、それ以外に、内部電極形成部に無電極領域が散在し、この部分で圧電歪による機械的応力を緩和しているものであると考えられる。
【００２５】
【発明の効果】
この発明によれば、内部電極形成部に圧電歪の発生しない無電極領域が散在することにより、内部電極で挟まれた部分に圧電歪が発生しても、無電極領域が強度を保持する役目を果たし、歪に対する耐性が増加する。それによって、圧電歪破壊電圧が増加し、高耐圧の積層コンデンサを得ることができる。
【図面の簡単な説明】
【図１】この発明の積層コンデンサの一例を示す斜視図である。
【図２】（Ａ）は図１に示す積層コンデンサの内部電極が重なる状態を示す平面図であり、（Ｂ）は線ＩＩＢ−ＩＩＢにおける断面図解図であり、（Ｃ）は線ＩＩＣ−ＩＩＣにおける断面図解図である。
【図３】図１および図２に示す積層コンデンサの等価回路図である。
【図４】この発明の積層コンデンサの他の例において、内部電極が重なる状態を示す図解図である。
【図５】この発明の積層コンデンサのさらに他の例において、内部電極が重なる状態を示す図解図である。
【図６】（Ａ）は従来の積層コンデンサの一例において、内部電極が重なる状態を示す平面図であり、（Ｂ）は線ＶＩＢ−ＶＩＢにおける断面図解図であり、（Ｃ）は線ＶＩＣ−ＶＩＣにおける断面図解図である。
【図７】従来の積層コンデンサの他の例を示す断面図解図である。
【符号の説明】
１０積層コンデンサ
１２積層体
１４誘電体層
１６第１の内部電極群
１６ａ第１の接続内部電極
１６ｂ第２の接続内部電極
１６ｃ浮遊内部電極
１８第２の内部電極群
１８ｃ浮遊内部電極
２０外部電極
２２無電極領域[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a multilayer capacitor, and more particularly to a medium-high voltage type multilayer capacitor that mainly requires a high breakdown voltage.
[0002]
[Prior art]
2. Description of the Related Art In recent years, the downsizing and high capacity of multilayer capacitors have been promoted by downsizing electronic devices and surface mounting. This trend has spread to the medium- and high-voltage capacitors market. For example, in the field of capacitors that require high voltage resistance such as for backlights of liquid crystal displays and for switching power supplies, smaller and lower-cost multilayer capacitors are available. It has been demanded.
[0003]
In order to reduce the size and increase the breakdown voltage of the multilayer capacitor 1, it is necessary to solve the three problems of increasing the internal breakdown voltage, preventing surface leakage, and preventing piezoelectric strain breakdown. In order to increase the internal breakdown voltage, for example, as shown in FIGS. 6A, 6B and 6C, the dividing line perpendicular to the direction connecting the external electrodes 3 at both ends of the laminate 2 formed of a dielectric is used. It is conceivable that the internal electrode 4 connected to the opposing external electrode 3 is divided into a plurality of parts with the boundary as a boundary, and adjacent internal electrodes 5 are formed so as to overlap both sides of the divided part. Here, the internal electrode 5 is not connected to the external electrode 3, and is divided so as to be parallel to the divided portion of the internal electrode 4 at a portion different from the divided portion of the internal electrode 4. With such a structure, as shown in FIG. 6B, a capacitance is formed at a portion where the internal electrode 4 and the internal electrode 5 face each other. Therefore, a plurality of capacitances are formed between the opposing external electrodes 3 and these capacitances are connected in series. For this reason, the voltage applied to each capacitance is reduced, and the internal breakdown voltage can be increased.
[0004]
By the way, when a ferroelectric material is used as a dielectric layer constituting the multilayer capacitor, it has a certain degree of piezoelectricity. Therefore, when a high voltage is applied to the multilayer capacitor 1, piezoelectric strain is generated in the dielectric layer, and mechanical stress is applied to the multilayer capacitor 1 to be destroyed. Such breakdown may occur faster than electrical breakdown due to the electric field.
[0005]
Therefore, as a countermeasure against piezoelectric strain destruction, for example, as disclosed in Japanese Patent Application Laid-Open No. 9-180956, as shown in FIG. A method of forming the intermediate layer 6 that relieves stress due to piezoelectric strain is considered. The intermediate layer 6 is formed of the same material as that of the dielectric layer. By making the layer thickness larger than that of the dielectric layer, mechanical stress is relieved and piezoelectric strain breakdown can be reduced.
[0006]
[Problems to be solved by the invention]
However, the method for providing the intermediate layer has the following problems.
That is, the stress due to piezoelectric strain increases as the number of layers increases, but in order to alleviate this stress, the thickness of the intermediate layer is increased or the number of divisions where the capacitance is obtained by the internal electrode is increased. The number of intermediate layers will be increased.
However, the intermediate layer is an extra layer that does not contribute to the capacity.In either case of increasing the thickness of the intermediate layer or increasing the number of intermediate layers, the ratio of the extra layer in the laminate is increased. Therefore, when the stress due to the piezoelectric strain is sufficiently reduced and a necessary capacity is obtained, the thickness of the laminated body becomes too large. On the other hand, if the required capacity is obtained within the determined dimensions, the number of intermediate layers is inevitably reduced or the thickness is reduced, and accordingly, the effect of reducing stress due to piezoelectric strain is reduced. .
In addition, when the thickness of the intermediate layer is increased, if the number of stacked layers is small, stress relaxation can be sufficiently performed in the intermediate layer. However, as the number of stacked layers increases, stress relaxation can be performed in the vicinity of the intermediate layer. However, since the effect of stress relaxation diminishes as the distance from the intermediate layer increases, the effect of reducing the stress due to piezoelectric strain is small.
[0007]
Therefore, a main object of the present invention is to provide a multilayer capacitor that has high pressure resistance and can suppress breakage due to piezoelectric strain.
[0008]
[Means for Solving the Problems]
According to the present invention, a first connection internal electrode that is divided into at least two on the same plane and is connected to one external electrode, with the dividing line intersecting the direction connecting the opposing external electrodes as a boundary, the other external electrode A first internal electrode group formed with a second connection internal electrode connected to each other, and at least two of the first internal electrode group overlap with each other through a dielectric layer mainly composed of barium titanate. The second internal electrode group is formed by forming a plurality of floating internal electrodes which are arranged at least in two on the same plane with a dividing line connecting the opposing external electrodes as a boundary and are not connected to the external electrodes The dividing line for forming the first internal electrode group and the dividing line for forming the second internal electrode group overlap with each other, so that the first and Second internal electrode group exists No electrodeless region is formed, a multilayer capacitor.
In such a multilayer capacitor, the first internal electrode group may be formed by being divided into at least two on the same plane with a dividing line connecting the external electrodes as a boundary.
The present invention also provides a first connection internal electrode that is divided into at least three on the same plane and connected to one external electrode, with the dividing line intersecting the direction connecting the opposing external electrodes as a boundary, A first internal electrode group formed by forming a second connection internal electrode connected to the external electrode, and a floating internal electrode positioned between the first connection internal electrode and the second connection internal electrode; Identical with a dividing line that is arranged to overlap at least two of the first internal electrode groups via a dielectric layer mainly composed of barium titanate and intersects the direction connecting the opposing external electrodes. A first internal electrode group or a second internal electrode, comprising: a laminated body having a second internal electrode group formed of a plurality of floating internal electrodes that are divided into at least two parts on a plane and are not connected to external electrodes. At least either of the group But is divided dividing line connecting the opposing external electrodes as a boundary, since the first division line for forming the internal electrode group of a dividing line for forming the second inner electrode groups overlap, stacked This is a multilayer capacitor in which an electrodeless region in which the first and second internal electrode groups do not exist is formed in the stacking direction of the body.
In such a multilayer capacitor, both the first internal electrode group and the second internal electrode group may be divided and formed with a dividing line connecting the opposing external electrodes as a boundary.
Further, the four first internal electrodes surrounding the portion where the dividing line connecting the external electrodes of the first internal electrode group and the dividing line crossing the direction connecting the external electrodes intersect on the same plane are the second internal electrodes. You may arrange | position so that it may overlap with one floating internal electrode among electrode groups.
Further, the four second internal electrodes surrounding the portion where the dividing line connecting the external electrodes of the second internal electrode group and the dividing line crossing the direction connecting the external electrodes intersect on the same plane are the first internal electrodes. You may arrange | position so that it may overlap with one floating internal electrode among electrode groups.
In these multilayer capacitors, a plurality of first internal electrode groups and a plurality of second internal electrode groups may be alternately stacked with a dielectric layer interposed therebetween.
[0009]
The dividing line for forming the first internal electrode group and the dividing line for forming the second internal electrode group overlap to form an electrodeless region in which no internal electrode exists in the stacking direction of the stacked body. Is done. Therefore, no electric field is applied to the electrodeless region, and no piezoelectric strain is generated in this portion. As a result, even if piezoelectric strain occurs in the dielectric layer between the internal electrodes, the mechanical stress is relieved in the portion where the internal electrodes do not exist.
In addition, since the dividing line of the first internal electrode group and the dividing line of the second internal electrode group cross each other, a plurality of capacitances are connected in series and in parallel between the external electrodes. For this reason, even when a high voltage is applied between the external electrodes, the voltage applied to each capacitance is low, and high voltage resistance can be obtained as a whole.
Further, by increasing the number of divisions of the internal electrode groups, the division lines of adjacent internal electrode groups intersect at a plurality of locations. Therefore, many electrodeless regions where no internal electrode exists are formed in the stacking direction of the stack. Therefore, the number of portions that relieve the mechanical stress generated in the multilayer body is increased, and a multilayer capacitor that is not easily broken by piezoelectric strain can be obtained.
In such a multilayer capacitor, the overall capacitance can be adjusted by adjusting the number of stacked layers of the first internal electrode group and the second internal electrode group.
[0010]
The above object, other objects, features, and advantages of the present invention will become more apparent from the following detailed description of embodiments of the present invention with reference to the drawings.
[0011]
DETAILED DESCRIPTION OF THE INVENTION
FIG. 1 is a perspective view showing an example of the multilayer capacitor of the present invention. The multilayer capacitor 10 includes a multilayer body 12. As shown in FIGS. 2A, 2B, and 2C, the laminated body 12 is formed to have a laminated structure of a dielectric layer 14, a first internal electrode group 16, and a second internal electrode group 18. The The first internal electrode group 16 includes first and second connection

internal electrodes

16a and 16b and a floating internal electrode 16c located between them on the same plane. The second internal electrode group 18 includes floating internal electrodes 18c. Here, the plurality of first internal electrode groups 16 and the plurality of second internal electrode groups 18 are alternately stacked so as to be adjacent to each other with the dielectric layer 14 interposed therebetween. By adjusting the number of layers, the capacitance of the entire multilayer capacitor 10 can be adjusted. External electrodes 20 are formed on opposite end surfaces of the stacked body 12, respectively. Then, the first and second connection

internal electrodes

16 a and 16 b located at both ends of the first internal electrode group 16 are connected to the opposed external electrodes 20. Note that the second internal electrode group 18 is not connected to the external electrode 20.
[0012]
As shown in FIG. 2A, the first internal electrode group 16 formed on the same plane is divided into four with a dividing line intersecting in a direction connecting the opposing external electrodes 20 as a boundary. The three first connection internal electrodes 16a, the three second connection internal electrodes 16b, and the six floating internal electrodes are formed on the same plane by being divided into three with the dividing line connecting the electrodes 20 as a boundary. It is divided into 16c.
[0013]
The second internal electrode group 18 formed to overlap the first internal electrode 16 is divided into two with a dividing line connecting the opposing external electrodes 20 as a boundary, and in a direction connecting the opposing external electrodes 20. By dividing into three with the intersecting dividing line as a boundary, it is divided into six floating internal electrodes 18c on the same plane.
[0014]
Each of the floating internal electrodes 18 c is arranged so as to cover the four first internal electrodes 16 surrounding the cross portion where the dividing lines intersect on the same plane in the first internal electrode group 16. Therefore, as shown in FIG. 2A, in the stacking direction of the stacked body 12, whichever part of the overlapping line of the dividing line of the first internal electrode group 16 and the dividing line of the second internal electrode group 18 An electrodeless region 22 in which no internal electrode exists is formed.
[0015]
Further, the first internal electrode group 16 is divided into 12 parts vertically and horizontally between the two external electrodes 20, and the second internal electrode group 18 is divided into 6 parts vertically and horizontally between the two external electrodes 20. Then, each floating internal electrode 18c of the second internal electrode group 18 includes first and second connection

internal electrodes

16a, 16b surrounding a portion where the dividing lines of the first internal electrode group 16 intersect on the same plane, and It arrange | positions so that it may overlap with the floating internal electrode 16c. Therefore, as shown in FIGS. 2B and 2C, a capacitance is formed in the facing portion between the first internal electrode group 16 and the second internal electrode group 18, and these capacitances are connected in series and Connected in parallel. Therefore, the multilayer capacitor 10 shown in FIGS. 1 and 2 has an equivalent circuit in which a plurality of capacitances are connected in series and parallel as shown in FIG.
[0016]
Since the multilayer capacitor 10 has a configuration in which a plurality of capacitances are connected in series and parallel, even when a voltage is applied between the two external electrodes 20, the voltage applied to each capacitance is low. Become. Therefore, high pressure resistance can be obtained in the laminate 12.
[0017]
In addition, since a plurality of electrodeless regions 22 are formed in the stacking direction of the stacked body 12, an electric field is not applied to these electrodeless regions 22, and no piezoelectric strain is generated in these regions. Therefore, even if piezoelectric strain occurs in the dielectric layer 14 in the portion where the first internal electrode group 16 and the second internal electrode group 18 overlap, the mechanical stress is relaxed in the electrodeless region 22. Therefore, it is possible to prevent the base 12 from being broken by mechanical stress due to piezoelectric strain. In the conventional multilayer capacitor shown in FIGS. 6 and 7, piezoelectric distortion occurs in the entire internal electrode formation portion. However, in the multilayer capacitor 10 shown in FIG. 1, the non-electrode region 22 is scattered in the internal electrode formation portion. , Mechanical stress is effectively relieved.
[0018]
The first internal electrode group 16 and the second internal electrode group 18 may be divided into at least two portions in the vertical and horizontal directions between the opposing external electrodes 20. When each of the first internal electrode group 16 and the second internal electrode group 18 is divided into two, as shown in FIG. 4, one non-electrode region 22 is formed in the central portion of the internal electrode formation portion. . Further, as shown in FIG. 5, the first internal electrode group 16 is divided into three parts with the dividing line intersecting in the direction connecting the opposing external electrodes 20 as a boundary, and the first and second connection

internal electrodes

16a, 16b. Then, the floating internal electrode 16c is formed, the second internal electrode group 18 is divided into four in the vertical and horizontal directions, and the four floating internal electrodes 18c are formed, whereby two electrodeless regions 22 can be formed. As shown in FIG. 2A, seven electrodeless regions 22 can be formed by dividing the first internal electrode group 16 into 12 parts and dividing the second internal electrode group 18 into 6 parts. . As described above, by increasing the number of divisions of the first internal electrode group 16 and the second internal electrode group 18, the number of electrodeless regions 22 is also increased, and portions where no piezoelectric strain is generated can be scattered.
[0019]
【Example】
First, a slurry was prepared by adding a solvent, an organic binder, a dispersant, and a plasticizer to a capacitor material powder having a dielectric constant of 3000 and having a dielectric constant of 3000, mainly BaTiO ₃ , and a ceramic green sheet was formed by a molding machine. An internal electrode paste mainly composed of Ag—Pd was printed in a predetermined pattern on the obtained ceramic green sheet.
[0020]
Several ceramic green sheets for outer layers were stacked, then ceramic green sheets for inner layers on which internal electrode paste was printed in a predetermined pattern were stacked in multiple layers, and finally several ceramic green sheets for outer layers were stacked. The laminate was pressed to form a press-molded body, degreased at about 400 ° C., and fired at 1200 to 1300 ° C. An electrode was baked on the end face of the sintered body thus obtained, and a plating film was formed thereon to form an external electrode.
[0021]
Through these steps, the multilayer capacitor having the structure shown in FIG. 2 and the multilayer capacitor having the conventional structure shown in FIG. 6 were produced. These multilayer capacitors have an element thickness of 30 μm between adjacent internal electrodes, and have an equivalent circuit in which a plurality of capacitances are connected between opposing external electrodes.
[0022]
With respect to these multilayer capacitors, a DC voltage was applied between the external electrodes to confirm the presence or absence of internal defects. Note that piezoelectric strain breakdown may not be judged from appearance or insulation resistance measurement because internal breakdown may not reach the outside or the insulation resistance may not decrease. Therefore, evaluation was performed by a method of observing internal defects with an ultrasonic flaw detector. At this time, the DC voltage was boosted by 0.5 kV and applied to the multilayer capacitor, and defect inspection by ultrasonic flaw detection was performed to evaluate the voltage at which piezoelectric strain breakdown occurred. The results are shown in Table 1.
[0023]
[Table 1]

[0024]
From Table 1, it was confirmed that the multilayer capacitor of the present invention had a higher internal breakdown voltage due to piezoelectric strain than the multilayer capacitor having the conventional structure. This is because, in the conventional multilayer capacitor, a portion where no piezoelectric strain occurs, that is, an electrodeless region without an internal electrode, exists only on both sides of the base, whereas in the multilayer capacitor of the present invention, It is considered that non-electrode regions are scattered in the internal electrode forming portion, and mechanical stress due to piezoelectric strain is relieved in this portion.
[0025]
【The invention's effect】
According to the present invention, since the non-electrode regions where no piezoelectric strain is generated are scattered in the internal electrode forming portion, the non-electrode region has a function of maintaining the strength even if the piezoelectric strain is generated in the portion sandwiched between the internal electrodes. And resistance to distortion increases. As a result, the piezoelectric strain breakdown voltage increases and a high withstand voltage multilayer capacitor can be obtained.
[Brief description of the drawings]
FIG. 1 is a perspective view showing an example of a multilayer capacitor according to the present invention.
2A is a plan view showing a state in which internal electrodes of the multilayer capacitor shown in FIG. 1 overlap, FIG. 2B is a cross-sectional view taken along line IIB-IIB, and FIG. 2C is a line IIC-IIC; FIG.
3 is an equivalent circuit diagram of the multilayer capacitor shown in FIGS. 1 and 2. FIG.
FIG. 4 is an illustrative view showing a state in which internal electrodes overlap in another example of the multilayer capacitor of the present invention;
FIG. 5 is an illustrative view showing a state in which internal electrodes overlap in still another example of the multilayer capacitor of the present invention;
6A is a plan view showing a state in which internal electrodes overlap in an example of a conventional multilayer capacitor, FIG. 6B is a sectional view taken along line VIB-VIB, and FIG. 6C is a line VIC- It is a cross-sectional solution figure in VIC.
FIG. 7 is a cross-sectional view illustrating another example of a conventional multilayer capacitor.
[Explanation of symbols]
10 multilayer capacitor 12 multilayer 14 dielectric layer 16 first internal electrode group 16a first connection internal electrode 16b second connection internal electrode 16c floating internal electrode 18 second internal electrode group 18c floating internal electrode 20 external electrode 22 No electrode area

Claims

The first connecting internal electrode connected to one external electrode and the other external electrode are divided into at least two parts on the same plane with a dividing line intersecting the direction connecting the opposing external electrodes as a boundary. A first internal electrode group formed with a second connection internal electrode;
It is arranged on the same plane with a dividing line connecting between the opposing external electrodes as a boundary, which is disposed so as to overlap with at least two of the first internal electrode groups via a dielectric layer mainly composed of barium titanate. And a second internal electrode group in which a plurality of floating internal electrodes that are not connected to the external electrodes are formed,
The dividing line for forming the first internal electrode group and the dividing line for forming the second internal electrode group overlap, whereby the first and second internal electrodes are arranged in the stacking direction of the stacked body. A multilayer capacitor in which an electrodeless region in which no group exists is formed.

2. The multilayer capacitor according to claim 1, wherein the first internal electrode group is formed by being divided into at least two on the same plane with a dividing line connecting the external electrodes as a boundary.

The first connecting internal electrode connected to one external electrode and the other external electrode are divided into at least three parts on the same plane with a dividing line intersecting the direction connecting the opposing external electrodes as a boundary. A first internal electrode group in which a second connection internal electrode and a floating internal electrode positioned between the first connection internal electrode and the second connection internal electrode are formed;
At least two of the first internal electrode groups are arranged so as to overlap with each other through a dielectric layer mainly composed of barium titanate, and a dividing line intersecting with a direction connecting the opposed external electrodes is used as a boundary Including a laminate having a second internal electrode group formed of a plurality of floating internal electrodes that are divided into at least two on the same plane and are not connected to the external electrodes,
At least one of the first internal electrode group or the second internal electrode group is divided using a dividing line connecting the opposed external electrodes as a boundary,
The dividing line for forming the first internal electrode group and the dividing line for forming the second internal electrode group overlap, whereby the first and second internal electrodes are arranged in the stacking direction of the stacked body. A multilayer capacitor in which an electrodeless region in which no group exists is formed.

4. The multilayer capacitor according to claim 3, wherein both of the first internal electrode group and the second internal electrode group are divided and formed with a dividing line connecting the opposed external electrodes as a boundary. 5.

Four first internal electrodes surrounding a portion where a dividing line connecting the external electrodes of the first internal electrode group and a dividing line crossing a direction connecting the external electrodes intersect on the same plane are the second internal electrodes. 5. The multilayer capacitor according to claim 3, wherein the multilayer capacitor is disposed so as to overlap with one floating internal electrode in the internal electrode group.

Four second internal electrodes surrounding a portion where a dividing line connecting the external electrodes of the second internal electrode group and a dividing line crossing the direction connecting the external electrodes intersect on the same plane are the first internal electrode. The multilayer capacitor according to claim 3, wherein the multilayer capacitor is disposed so as to overlap with one floating internal electrode in the internal electrode group.

The multilayer capacitor according to claim 1, wherein a plurality of the first internal electrode groups and a plurality of the second internal electrode groups are alternately stacked with the dielectric layer interposed therebetween. .