JP4035573B2 - Semiconductor memory device and control method thereof - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
  The present invention relates to selection of an activation region partitioned for each predetermined block region in a semiconductor storage device, and more particularly to a semiconductor storage device having a protection function for an access operation to an activation region and a control method thereof. It is.
[0002]
[Prior art]
  Conventionally, in a semiconductor memory device, a memory cell array is generally divided into a plurality of blocks, and access control is performed for each block. As access control, there is a so-called protection function that prohibits these access operations in addition to reading, writing, and erasing data, and is set for each block.
[0003]
  Patent Document 1 discloses a protection control circuit for setting a protection function for each block as shown in FIG. The protection state for each block is set by the lock control signals LS0 to LSN. The lock control signals LS0 to LSN are output from the block protect control unit 100. The block protect control unit 100 includes a lock register 110 that stores permission / prohibition of an access state to the block, and a lockdown register 120 that prohibits writing to the lock register 110.
[0004]
  A lock set signal LS or a lock reset signal LR is input to the lock register 110 together with the block selection signal S # (S0 to SN). The lock selection signal LS or the lock reset signal LR can be input by the block selection signal S #, the protection function setting state or the release state is stored according to the lock set signal LS or the lock reset signal LR, and the lock information DQ00 to DQ0N Is output. The lockdown register 120 is supplied with the lockdown set signal LDS together with the block selection signal S # (S0 to SN). The lock down set signal LDS can be input by the block selection signal S #, the rewriting of the lock register 110 is prohibited in accordance with the lock down set signal LDS, and the lock down information DQ10 to DQ1N is output. The lock information DQ00 to DQ0N and the lockdown information DQ10 to DQ1N are input to the logic synthesis unit 130, and lock control signals LS0 to LSN are output.
[0005]
  The lockdown set signal LDS is output from the lockdown register rewriting circuit 300 in response to a command. The block selection signal S # is output from the block selection circuit 400 in response to a command. Further, the lock set signal LS and the lock reset signal LR are output from the lock register rewriting circuit 200 in response to commands. Here, block select signal S # (S0 to SN) and lockdown information DQ10 to DQ1N from each block protect control unit 100 are input to lock register rewriting circuit 200. This is because for the block in which the lock-down state is set, the lock set signal LS and the lock reset signal LR are prohibited from being output and the lock register 110 is not rewritten.
[0006]
[Patent Document 1]
    US Pat. No. 6,154,819 (FIG. 5)
[0007]
[Problems to be solved by the invention]
  However, in the above prior art, when determining whether or not the lock register 110 can be rewritten, lockdown information DQ10 to DQ1N for confirming the lockdown state is selected for each block selection signal S # (S0 to SN) selected. Is required. Since the lock register rewriting circuit 200 determines whether or not the rewrite of the lock register 110 is permitted, (N + 1) signal wirings that propagate the block selection signal S # (S0 to SN) from the block selection circuit 400 and each block It is necessary to wire (N + 1) signal lines that propagate lockdown information DQ10 to DQ1N from the protection control unit 100.
[0008]
  In order to route a total of (2N + 2) signal wires, it is necessary to secure a large wiring area, which may be difficult to realize a compact die size. When the number of blocks increases as the capacity increases, the number of necessary signal wirings further increases, and the ratio of the signal wiring area in the die size further increases.
[0009]
  The present invention has been made to solve the problems of the prior art, and when the activation control is performed by dividing the memory cell array into a plurality of blocks, access to a lock register associated with a protection function set for each block. An object of the present invention is to provide a semiconductor memory device and a method for controlling the semiconductor memory device which can realize the control of whether or not the operation is permitted with a compact circuit configuration.
[0010]
[Means for Solving the Problems]
  In order to achieve the above object, a semiconductor memory device according to a first aspect of the present invention is a semiconductor memory device including a plurality of blocks, in which permission / prohibition of access operation is controlled for each block, and the access operation permission / denial state for the block is controlled. The lock information indicating the setting is stored in a rewritable manner, and the lock information that is activated in response to the block selection signal is rewritten.PermissionStatusIt is inA lockdown register that stores rewrite permission / inhibition information indicating whether or not rewritable,Rewrite permission informationRewrite permission statusWhat is inIndicateIn case,Outputs a selection signal according to the block selection signal and lock registerWhen the update of lock information to the device is permitted and the rewrite permission / inhibition information indicates that rewrite is not permitted, the selection signal is not output and the lock register is not permitted to be updated.A first logic synthesis unit is provided for each block.
[0011]
  According to another aspect of the semiconductor memory device of the present invention, rewrite permission / inhibition information is stored in a lockdown register activated in response to a block selection signal. In the first logic synthesis unit, the rewrite permission / inhibition information is in a rewrite permitted state.To indicate thatA lock register that outputs a selection signal according to the block selection signalAllow update of lock information to. BThe lock register contains lock information indicating the setting of permission / inhibition status of access operation for the block.UpdatedStored.When the rewrite permission / inhibition information indicates that the rewrite is not permitted, the selection register is not output and the lock register is not permitted to be updated.These are provided for each block.
[0012]
  A method for controlling a semiconductor memory device according to claim 8 is a method for controlling a semiconductor memory device, wherein the semiconductor memory device is divided into a plurality of blocks, and permission / inhibition of an access operation is controlled for each block,Each In the block,The lock information indicating the setting of permission / inhibition status of access operation to the block is rewritten according to the block selection instruction.PermissionStatusIt is inWhether or notCalligraphyPass / fail information,RewritableStore inRewrite permission information storage step and,bookPass / fail informationIs in a rewrite-enabled stateDepending on the block selection instruction, the lock informationAllow update and writePass / fail informationIs in a rewrite disallowed state, Mask the block selection instructions and lock informationDisallow updatesLock information rewrite determination step and lock information rewrite determination stepAllowedLock information ifThe stored information in response toRewriteGetLock information storing step,HaveIt is characterized by that.
[0013]
  9. The method of controlling a semiconductor memory device according to claim 8, wherein in the rewrite permission / rejection information storage step, the lock information indicating the setting of the permission state of the access operation for the block is rewritten according to the block selection instruction.PermissionStatusInIndicates whether there isCalligraphyPass / fail informationTheRewritableStore in. In the lock information rewrite determination step, rewrite permission / rewrite based on rewrite permission / inhibition informationDisapprovalDepending on the status, the lock informationAllow updatesOr by masking the block selection instructionsDisallow updates. In the lock information storage step, the lock information is rewritten.AllowedLock information whenThe stored information in response toRewriteGet. Each of these control steps is block by blockIn lineBe made.
[0014]
  As a result, whether or not the lock information can be rewritten is determined by activating the first logic synthesis unit based on the rewrite permission / rejection information stored for each block, or by the lock information rewrite determination step.Done every. Therefore, it is not necessary to output the rewrite permission / rejection information to the outside for the rewrite control of the lock information. In a semiconductor memory device having a plurality of blocks, the wiring area for wiring the signal path of the rewritability information for each block becomes unnecessary, and the increase in the chip area for realizing the lock information rewrite control is suppressed to the minimum necessary. Can do.
[0015]
  A semiconductor memory device according to claim 2 is characterized in that, in the semiconductor memory device according to claim 1, a lock control signal for controlling permission / inhibition of an access operation to a block is output based on lock information. According to a ninth aspect of the present invention, there is provided a method for controlling a semiconductor memory device according to the eighth aspect, wherein permission / inhibition of an access operation for a block is controlled by lock information. As a result, the lock state of the block is controlled in accordance with the permission information of the access operation to the block set by the lock information, and the stored lock information matches the block lock state.
[0016]
  According to a third aspect of the present invention, there is provided the semiconductor memory device according to the first aspect, wherein the second logic synthesis supplies information based on the rewrite permission / inhibition information to the first logic synthesis unit in response to the forced rewrite permission signal. A rewrite permission information indicating a rewritable state regardless of the rewrite permission / rejection information stored in the lockdown register, when the forced rewrite permission signal is active as information based on the rewrite permission / rejection information, When the forcible rewrite permission signal is inactive, information according to rewrite permission / denial information is supplied.
[0017]
  According to a tenth aspect of the present invention, there is provided a semiconductor memory device control method according to the eighth aspect, wherein, in the lock information rewrite determining step, a lock information forcible rewrite command is issued. Instructing the rewritable state of the lock information regardless of the rewritability information, and if the lock information forced rewrite command is not issued, the lock information rewritable state instruction is determined according to the rewrite permission information. It is characterized by that.
[0018]
  As a result, when the forced rewrite permission signal is active, or when a forced rewrite command for lock information is issued, the first logic synthesis unit is activated regardless of the rewrite permission / rejection information stored for each block. As a result, or by the lock information rewrite determination step, the lock information can be rewritten by performing distributed control for each block. Therefore, even when the lock information is forcibly rewritten regardless of the rewrite permission / rejection information, it is not necessary to output the rewrite permission / rejection information to the outside for the rewrite control of the lock information.
[0019]
  According to a fourth aspect of the present invention, in the semiconductor memory device according to the third aspect, the lock information and the information based on the rewrite permission / prohibition information supplied from the second logic synthesis unit are input, and access to the block is performed. An output logic synthesis unit for outputting a lock control signal for controlling whether or not the operation is permitted is provided. Thereby, the lock control signal can be output in accordance with the logical synthesis of the lock information and the information based on the rewrite permission / inhibition information.
[0020]
  According to a fifth aspect of the present invention, in the semiconductor memory device according to the third aspect, the forced rewrite permission signal is preferably a signal input from the outside.
[0021]
  A semiconductor memory device according to a sixth aspect is the semiconductor memory device according to the first aspect, wherein the lock register and the lock-down register are provided with an initialization terminal for initializing the register contents.
[0022]
  According to a seventh aspect of the present invention, in the semiconductor memory device according to the first aspect, the first logic synthesizer is controlled in conduction by the information based on the rewritability information and the block selection signal, and the selection signal is output. It is characterized by comprising first and second transistors connected in series between a terminal and a predetermined power supply terminal. Thus, the first logic synthesis unit can be configured with a simple configuration.
[0023]
DETAILED DESCRIPTION OF THE INVENTION
  DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of a semiconductor memory device and a control method thereof according to the present invention will be described below in detail with reference to FIGS.
[0024]
  FIG. 1 shows a block protect control unit 10 of the first embodiment. The lock register 11 storing the lock information DQ0 # indicating the setting of the permission / inhibition state of the access operation for the block sets / resets the selection signal S1 # output from the logic synthesis unit 1 (14) and the lock information DQ0 #. A lock set / reset signal LS / LR to be controlled is input. With the lock register 11 activated by the selection signal S1 #, the lock information DQ0 # is set / reset by the lock set / reset signal LS / LR.
[0025]
  The lockdown register 12 storing lockdown information DQ1 # indicating whether or not the lock information DQ0 # stored in the lock register 11 is in a rewrite enabled state receives the block selection signal S # and the lockdown set signal LDS. Is done. In a state where the lockdown register 12 is activated by the block selection signal S #, the lockdown information DQ1 # is stored by the lockdown set signal LDS. Note that no reset signal is input to the lockdown register 12, and the lockdown information DQ1 # that has been set once is supplied when power is turned on again by a control circuit (not shown) or when a forced reset signal is applied to the semiconductor memory device. Only the configuration is reset.
[0026]
  The logic synthesizer 2 (15) is controlled by the forced rewrite permission signal WP # in response to the input of the lockdown information DQ1 #, and outputs the lockdown control information DQ2 #. The lockdown control information DQ2 # is input to the logic synthesis unit 1 (14) and the output logic synthesis unit 130. The lockdown control information DQ2 # is output according to the lockdown information DQ1 # when the forced rewrite permission signal WP # is in an inactive state and does not instruct a forced rewritable state of the lock information DQ0 #. That is, when the lockdown information DQ1 # indicates the rewrite permission state of the lock information DQ0 #, the lockdown control information DQ2 # indicates the rewrite permission state and indicates the rewrite disapproval state of the lock information DQ0 # The lockdown control information DQ2 # indicates a rewrite non-permission state. On the other hand, when the forced rewrite permission signal WP # is in an active state and indicates a compulsory rewritable state of the lock information DQ0 #, the lockdown control information is irrespective of the rewrite permission / denial state of the lockdown information DQ1 #. DQ2 # indicates a rewrite permission state.
[0027]
  The logic synthesis unit 1 (14) is controlled by the lockdown control information DQ2 #, and outputs a selection signal S1 # according to the input block control signal S #. That is, when the lockdown control information DQ2 # indicates the rewrite permission state of the lock information DQ0 #, the selection signal S1 # corresponding to the block selection signal S # is input to the lock register 11. In response to the block selection signal S # indicating that the block is selected, the lock register 11 is activated by the selection signal S1 #, and the lock information DQ0 # becomes rewritable. When the lockdown control information DQ2 # indicates a rewrite disapproval state of the lock information DQ0 #, the selection signal S1 # is not activated regardless of the block selection signal S #, and the lock register 11 is deactivated and locked. Information DQ0 # is not rewritten.
[0028]
  The output logic synthesis unit 130 performs a logical OR operation on the lock information DQ0 # and the lockdown control information DQ2 #, and outputs the operation result as the lock control signal LS #. Therefore, the access operation to the block is performed when the lock information DQ0 # is set to the access operation disallowed state, or when the lockdown control information DQ2 # indicates the lock information DQ0 # rewrite disapproval state. Prohibited. In this configuration, the access operation is prohibited when the lock information DQ2 # is not rewritten in addition to the lock operation DQ0 #.
[0029]
  FIG. 2 shows a specific example of the block protect control unit 10 of the first embodiment. In the lock register 11A, the lock information DQ0 # is held by the latch circuit L1. Each terminal of the latch circuit L1 is connected to NMOS transistors M1 and M2 controlled by the lock set / reset signal LS / LR of the lock information DQ0 #, and is connected to the ground voltage via the logic synthesis unit 1 (14A). The
[0030]
  The logic synthesis unit 1 (14A) has a configuration in which an NMOS transistor M7 connected to the lock register 11A and an NMOS transistor M8 connected to the ground voltage are connected in series. The NMOS transistor M7 is controlled by a block selection signal S #, and the NMOS transistor M8 is a low active signal / DQ2 among lockdown control information DQ2 # and / DQ2 # output from a logic synthesis unit 2 (15A) described later. Controlled by #. The low active lockdown control information / DQ2 # becomes a low level signal when instructing a non-permission state of rewriting of the lock information DQ0 #, and becomes a high level signal when instructing a permission state. Accordingly, the NMOS transistor M8 is turned on in the rewrite enabled state, and the latch circuit L1 is activated in response to the NMOS transistor M7 being turned on in response to the block selection by the block selection signal S #, and lock information DQ0 # described later. Rewriting is performed. In the rewrite non-permission state, the NMOS transistor M8 maintains a non-conduction state. Regardless of the block selection signal S #, the latch circuit L1 maintains an inactive state, and rewriting of the lock information DQ0 # is prohibited.
[0031]
  In a state where the latch circuit L1 is activated, when the NMOS transistor M1 is turned on by the lock set signal LS, the latch circuit L1 is set and a high level signal is stored as the lock information DQ0 #. When the NMOS transistor M2 is turned on by the lock reset signal LR, the latch circuit L1 is reset and a low level signal is stored as the lock information DQ0 #. As a result, the lock information DQ0 # is rewritten.
[0032]
  Further, an NMOS transistor M3 is connected in parallel with the NMOS transistor M1, and is controlled by a reset signal RST. When the NMOS transistor M3 is turned on in response to the high level reset signal RST, the latch circuit L1 is set and a high level signal is stored as the lock information DQ0 #. Here, the reset signal RST is a signal that is activated at the time of power-on or a forced reset and sets the internal circuit to an initialized state. In the initialized state, the lock information DQ0 # is set (DQ0 # = “H”), and the access operation to the block is set to the non-permitted state, thereby preventing unexpected erroneous access.
[0033]
  The lockdown register 12A has a circuit configuration similar to that of the lock register 11A. Lockdown information DQ1 # is held in latch circuit L2. NMOS transistors M4 and M5 connected in series and an NMOS transistor M6 are connected to each terminal of the latch circuit L2. The NMOS transistors M4 and M5 are controlled by a lockdown set signal LDS and a block selection signal S #, respectively. In a state where the block selection signal S # becomes a high level signal and the block is selected, the high level lockdown information DQ1 # is stored by inputting the high level lockdown set signal LDS. The lockdown information DQ1 # stored in the latch circuit L2 is reset according to the high level signal of the reset signal RST that controls the NMOS transistor M6. As described above, the reset signal RST is a signal that is activated when the power is turned on or when a forced reset is performed. Therefore, the lockdown information DQ1 # once set is not erroneously reset in the normal use state.
[0034]
  The logic synthesis unit 2 (15A) performs output control of the lockdown control information DQ2 # according to the forced rewrite permission signal WP # by a logical operation by the NAND gate A1. The lockdown information DQ1 # and the inverted signal of the forced rewrite permission signal WP # via the inverter gate I2 are input to the input terminal of the NAND gate A1. In the case of the high-level lockdown information DQ1 # and the low-level forced rewrite permission signal WP # from the NAND gate A1, that is, in a state where the rewrite disapproval state is instructed by the lockdown information DQ1 # and forcible rewrite permission Only when the signal WP # is inactive and the lock information DQ0 # is not forcibly rewritten, the lockdown control information DQ2 # is activated (DQ2 # = "H", / DQ2 # = "L"). . The rewrite of the lock information DQ0 # is prohibited, and the lock logic signal LS # is activated and the block access operation is prohibited by the output logic synthesizer 13A that performs a logical sum operation by the NOR gate O1 and the inverter gate I1. . On the other hand, when the rewrite non-permission state is not set by the lockdown information DQ1 # (DQ1 # = "L"), or the forced rewrite permission signal WP # is active and the forced rewrite is permitted. When the state (WP # = "H") is maintained, the lockdown control information DQ2 # becomes inactive (DQ2 # = "L", / DQ2 # = “H”).
[0035]
  FIG. 3 shows operation waveforms for the block protect control unit 10 (FIG. 1) of the first embodiment, specifically, the specific example shown in FIG. FIG. 3 shows a case where lock information DQ0 # and lockdown information DQ1 # are stored according to the command.
[0036]
  First, in response to a lock set command, the block selection signal S # becomes a high level to select a block, and a lock set signal LS of a high level pulse is input. At this time, since the lockdown set signal LDS is not input, the lockdown registers 12 and 12A do not store the rewrite non-permission state, and the lockdown information DQ1 # is maintained at the low level. Therefore, the logic synthesis unit 2 (15, 15A) outputs the low-level lockdown control information DQ2 # indicating the rewrite permission state. The inverted signal / DQ2 # becomes high level, the logic synthesis unit 1 (14, 14A) is activated, and the lock registers 11, 11A are activated. The activated lock registers 11 and 11A store high-level lock information DQ0 # by a high-level pulse lock set signal LS, and a block access prohibition state is set. The high level lock information DQ0 # is output as the high level lock control signal LS # via the output logic synthesis units 13 and 13A, and access to the block is prohibited. Transition to protected state.
[0037]
  Next, in response to the lockdown set command, the lockdown set signal LDS is input to the lockdown registers 12 and 12A, and high-level lockdown information DQ1 # is stored. At this time, the forced rewrite permission signal WP # is maintained at a low level, and forced rewriting is not permitted. Accordingly, the lockdown control information DQ2 # from the logic synthesis unit 2 (15, 15A) transitions to a high level, and the inverted signal / DQ2 # transitions to a low level. Rewriting the lock information DQ0 # to the lock registers 11 and 11A is prohibited in accordance with the deactivation of the logic synthesis unit 1 (14, 14A). In addition to the lock information DQ0 #, the lockdown control information DQ2 # is also set to the high level, the lock control signal LS # output via the output logic synthesis units 13 and 13A is maintained at the high level, and the block access operation is prohibited. Maintained.
[0038]
  Assume that a lock reset command is input after the lockdown information DQ1 # is set, and a lock reset signal LR having a high level pulse is input. In this case, high-level lockdown information DQ1 # is held in the lockdown registers 12 and 12A, and high-level lockdown control information DQ2 # is output from the logic synthesis unit 2 (15 and 15A). (Inverted signal / DQ2 # is low level). Therefore, the logic synthesis unit 1 (14, 14A) is maintained in an inactive state, and rewriting of the lock registers 11, 11A is prohibited. Accordingly, even if the high level pulse lock reset signal LR is input, the contents of the lock registers 11 and 11A are not rewritten, and the high level lock information DQ0 # continues to be held. The lock reset command is invalid.
[0039]
  After the rewrite disapproval state is stored in the lockdown registers 12 and 12A, when the forced rewrite permission signal WP # becomes high level and a forced rewrite permission command is input, the output of the logic synthesis unit 2 (15, 15A) Regardless of the high level lockdown information DQ1 # indicating the rewrite disapproval state, the lockdown control information DQ2 # transitions to the low level indicating the rewrite permission state (the inverted signal / DQ2 # transitions to the high level). As a result, the logic synthesis unit 1 (14, 14A) transitions to the active state, and the lock registers 11, 11A are activated. When the lock reset command is input again in this state, the lock information DQ0 # stored in the lock registers 11 and 11A is changed to the low level by the high level pulse lock reset signal LR, and the access operation to the block is permitted. The state is set. The low-level lock information DQ0 # is output as the low-level lock control signal LS # via the output logic synthesis units 13 and 13A, and access to the block is permitted. Transition to unprotected state.
[0040]
  FIG. 4 shows a protection control circuit in which the block protection control unit 10 described with reference to FIGS. In the control circuit of FIG. 4, in each block protect control unit 10, the activation state of the lock register 11 is controlled in accordance with the selection signal S # (S10 to S1N) output from the logic synthesis unit 1 (14). Thus, rewrite control of the lock information DQ0 # (DQ00 to DQ0N) is performed. Therefore, the lock information DQ0 # (DQ00 to DQ0N) to the lock register 110 is controlled by the output control of the lock set / reset signal LS / LR output from the lock register rewriting circuit 200 in the conventional protection control circuit (FIG. 6). The following points are different from the case where the storage is performed.
[0041]
  That is, in the protection control circuit of the prior art (FIG. 6), (N + 1) number for inputting the lockdown information DQ1 # (DQ10 to DQ1N) stored in each block protection control unit 100 to the lock register rewriting circuit 200. However, in the protection control circuit (FIG. 4) of the first embodiment, (N + 1) signal wirings of the lockdown information DQ1 # (DQ10 to DQ1N) to the lock register rewriting circuit 16 are unnecessary. It becomes. Further, in the lock register rewriting circuit 200, since it is necessary to control the output of the lock set / reset signal LS / LR in accordance with the selected block, it is necessary to input the block selection signal S # (S0 to SN). In the protection control circuit (FIG. 4) of the embodiment, (N + 1) signal wirings of the block selection signal S # (S0 to SN) to the lock register rewriting circuit 16 are not required.
[0042]
  As described above in detail, according to the block protect control unit 10 of the first embodiment, whether or not the lock information DQ0 # is to be rewritten is determined based on the lockdown information DQ1 # that is the rewrite permission / rejection information stored for each block. Based on this, the logic synthesizer 1 (14), which is the first logic synthesizer, is activated, and distributed control is performed for each block in the block protect controller 10. Therefore, it is not necessary to output the lockdown information DQ1 # to the outside for rewriting control of the lock information DQ0 #. In a semiconductor memory device having a plurality of blocks, a wiring region for wiring the signal path of the lockdown information DQ1 # for each block becomes unnecessary, and the increase in the chip area for realizing the rewrite control of the lock information DQ0 # is minimized. Can be suppressed.
[0043]
  When the forced rewrite permission signal WP # is active, the logic synthesizer 1 (14) is activated regardless of the lockdown information DQ1 # stored for each block, so that the block protect controller 10, the lock information DQ0 # is in a rewritable state by being distributedly controlled for each block. Therefore, even when the lock information DQ0 # is forcibly rewritten regardless of the lockdown information DQ1 #, it is not necessary to output the lockdown information DQ1 # to the outside for the rewrite control of the lock information DQ0 #.
[0044]
  In addition, (N + 1) signal lines for lockdown information DQ1 # (DQ10 to DQ1N) and (N + 1) signal lines for block selection signals S # (S0 to SN) to the lock register rewriting circuit 16 are not required. Thus, an increase in the chip area for realizing rewrite control of the lock information DQ0 # (DQ00 to DQ0N) can be suppressed to the minimum necessary.
[0045]
  Here, the logic synthesis unit 14A has a simple configuration in which NMOS transistors M7 and M8 are connected in series. The first logic synthesis unit can be configured with a simple configuration.
[0046]
  The block protect control unit 20 of the second embodiment shown in FIG. 5 deletes the output logic synthesis unit 130 in the block protect control unit 10 (FIG. 1) of the first embodiment, and lock information DQ0 # and lockdown control information DQ2 The lock information DQ0 # is output as the lock control signal LS # in place of the lock control signal LS # output as the result of the logical OR with #.
[0047]
  According to the block protect control unit 20 of the second embodiment, the lock control signal LS # is output according to the permission information of the access operation to the block set by the lock information DQ0 #, and the lock state of the block is controlled. . The lock information DQ0 # stored in the lock register 11 matches the block lock state. The output logic synthesis unit 130 becomes unnecessary.
[0048]
  The present invention is not limited to the above-described embodiment, and it goes without saying that various improvements and modifications can be made without departing from the spirit of the present invention.
  It goes without saying that the semiconductor memory device according to the present invention is applicable as long as access permission / denial is controlled for each block regardless of whether it is volatile or nonvolatile.
  Although the present invention has been described by taking as an example application to a semiconductor memory device, the present invention is not limited to this, and the semiconductor memory device is configured on a chip as a function of the semiconductor integrated circuit device. It is also applicable when
  Furthermore, it goes without saying that the present invention can also be applied to a semiconductor integrated circuit device in which permission / inhibition of access operation is performed for each block even for a semiconductor integrated circuit device other than a semiconductor memory device.
[0049]
【The invention's effect】
  According to the present invention, when activation control is performed by dividing a memory cell array into a plurality of blocks, it is possible to control permission / inhibition of an access operation to a lock register accompanying a protection function set for each block with a compact circuit configuration. It is possible to provide a semiconductor memory device and a control method thereof.
[Brief description of the drawings]
FIG. 1 is a circuit block diagram illustrating a block protect control unit according to a first embodiment.
FIG. 2 is a circuit diagram showing a specific example of the first embodiment.
FIG. 3 is an operation waveform diagram of a specific example of the first embodiment.
FIG. 4 is a circuit block diagram showing a protection control circuit of the first embodiment.
FIG. 5 is a circuit block diagram showing a block protect control unit of a second embodiment.
FIG. 6 is a circuit diagram showing a protection control circuit according to the prior art.
[Explanation of symbols]
10 Block protect controller
11, 11A Lock register
12, 12A Lockdown register
14, 14A Logic synthesis unit 1
15, 15A Logic synthesis unit 2
16,200 Lock register rewrite circuit
130 Output logic synthesis unit
DQ0 # Lock information
DQ1 # Lockdown information
DQ2 #, / DQ2 # Lockdown control information
LDS lockdown set signal
LR lock reset signal
LS Lock set signal
LS # Lock control signal
S # Block selection signal
S1 # selection signal
WP # Forced rewrite permission signal

Claims (10)

A semiconductor memory device comprising a plurality of blocks, wherein access permission / non-permission of each block is controlled,
A lock register for storing rewritable lock information indicating setting of permission / inhibition state of access operation to the block;
Is activated in response to the block select signal, and a lockdown register the rewrite permission information indicating whether or not the lock information stored in the lock register is rewritten in the authorized state, rewritable store,
To indicate that it is in the grant state the rewriting permission information rewriting, and outputs a selection signal corresponding to said block selection signal, to allow updating of the lock information into the lock register, the rewrite permission information rewriting A semiconductor memory device comprising: a first logic synthesis unit that does not output the selection signal and does not permit updating of the lock register for each block when indicating that the block is in a non-permitted state .   2. The semiconductor memory device according to claim 1, wherein a lock control signal for controlling permission / inhibition of an access operation for the block is output based on the lock information. A second logic synthesis unit that supplies information based on the rewrite permission / inhibition information to the first logic synthesis unit in response to a forced rewrite permission signal;
Wherein as the information based on the rewrite permission information, if the forced rewrite permission signal is active, rewriting permission information indicating the rewriting permitted state regardless of the rewriting permission information stored in the lockdown register is supplied, 2. The semiconductor memory device according to claim 1, wherein when the forcible rewrite permission signal is inactive, information corresponding to the rewrite permission / inhibition information is supplied.   An output logic synthesis unit is provided to which the lock information and information based on the rewrite permission / prohibition information supplied from the second logic synthesis unit are input and a lock control signal for controlling permission / inhibition of an access operation to the block is output. The semiconductor memory device according to claim 3.   4. The semiconductor memory device according to claim 3, wherein the forcible rewrite permission signal is a signal input from the outside.   2. The semiconductor memory device according to claim 1, wherein each of the lock register and the lock down register includes an initialization terminal that initializes register contents.   The first logic synthesizer is controlled in conduction by information based on the rewrite permission information and the block selection signal, and is connected in series between an output terminal of the selection signal and a predetermined power supply terminal. The semiconductor memory device according to claim 1, further comprising a transistor. A method for controlling a semiconductor memory device, wherein the method is divided into a plurality of blocks, and permission / inhibition of an access operation is controlled for each block,
In each block
Depending on the selection instruction of the block, the block permission whether the shown to manual換許unnecessary information lock information indicating a setting state rewritten in the authorized state of the access operation to the rewritable rewritable permission information storage for storing Steps,
When in the enabled state before Symbol rewriting permission information is rewritten in accordance with the selection instruction of the block, the allow updates of lock information, if the previous SL is disallowed state rewriting permission information is rewritten, the selection instruction of the block A lock information rewrite determination step that masks the update and disallows the update of the lock information;
If rewriting the lock information in the lock information rewriting determination step is permitted, a semiconductor, characterized in that in response to said update lock information, and the stored information write changeover obtain lock information storing step is, having Storage device control method.   9. The method of controlling a semiconductor memory device according to claim 8, wherein whether or not an access operation to the block is permitted is controlled by the lock information. In the lock information rewrite determination step, when a forced rewrite command for the lock information has been issued, the lock information rewrite permission state is instructed regardless of the rewrite permission / inhibition information, and the lock information rewrite command is issued. 9. The method of controlling a semiconductor memory device according to claim 8, wherein if it is not issued, an instruction of a rewrite permission state of the lock information is determined according to the rewrite permission / inhibition information.

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