JP4033086B2 - Dry etching method - Google Patents

Description

  The present invention relates to a dry etching method suitable for use in manufacturing a microstructure such as a MEMS (Micro-Electro-Mechanical System), and more particularly to an anisotropic etching method for a thick polysilicon layer or an amorphous silicon layer.

  Conventionally, as a method of selectively dry-etching a thick silicon material, a Bosch method in which isotropic etching and film deposition are alternately repeated is known (for example, see Non-Patent Document 1).

As a method for selectively dry-etching a polysilicon layer, a method using Cl ₂ gas or a mixed gas of HBr gas and O ₂ gas as an etching gas is also known.
Masayoshi Esashi: “Micromachine”, Industrial Technology Information Service Center, P.A. 55-56

  According to the above-described Bosch method, since isotropic etching is used, the etching shape is not perpendicular to the depth direction and is stepped (not an anisotropic shape). Moreover, it is necessary to introduce new equipment, resulting in an increase in cost.

On the other hand, according to the dry etching method using Cl ₂ gas or a mixed gas of HBr gas and O ₂ gas as an etching gas, the etching rate is slow, so that a reduction in productivity is inevitable when etching a thick silicon material. Further, the etching shape does not become perpendicular to the depth direction, but becomes a forward taper shape, and it is difficult to obtain a good anisotropic shape.

  An object of the present invention is to provide a novel dry etching method capable of processing a thick silicon layer made of polysilicon or amorphous silicon into an anisotropic shape with high dimensional accuracy.

The dry etching method according to the present invention includes:
Forming a silicon layer made of polysilicon or amorphous silicon having a thickness of 1 to 15 μm on one main surface of the substrate having at least one main surface having an insulating property;
Forming a resist layer having a thickness of 1 to 1.5 times the thickness of the silicon layer on the silicon layer according to a predetermined pattern by a photolithography process;
The silicon layer is formed on one main surface of the substrate while forming a side wall protective film on the side wall of the etched portion of the silicon layer by plasma etching using an etching gas containing chlorine, oxygen, and fluorine and using the resist layer as a mask. A step of patterning the silicon layer by anisotropic etching until reaching the surface, wherein the sidewall protective film includes carbon polymer reattached by etching of the resist layer and fluorine in the etching gas Forming a film mainly composed of
Overetching the patterned silicon layer by a plasma etching process using an etching gas containing chlorine and oxygen but not fluorine and using the resist layer as a mask to correct the anisotropic shape of the silicon layer; ,
And removing the remaining portion of the resist layer and the remaining portion of the sidewall protective film after the overetching.

  In the dry etching method of the present invention, a thick silicon layer made of polysilicon or amorphous silicon having a thickness of 1 to 15 μm is used as an etching target. In this case, germanium or carbon may be contained in the polysilicon or amorphous silicon constituting the thick silicon layer. In the step of forming the resist layer, the thickness of the resist layer is set within a range of 1 to 1.5 times the thickness of the silicon layer to be etched. If the thickness of the resist layer is smaller than the thickness of the silicon layer, the resist layer disappears during anisotropic etching (main etching), and the supply of carbon for forming the sidewall protective film becomes insufficient. When the thickness of the resist layer is greater than 1.5 times the thickness of the silicon layer, the aspect ratio becomes large, and silicon etching residue occurs in the narrow space portion. The cross-sectional shape of the resist layer is preferably a shape perpendicular to the thickness direction or a slightly tapered shape.

In the process of patterning the silicon layer, a gas containing chlorine, oxygen, and fluorine is used as an etching gas. When a fluorine-containing gas such as SF ₆ is added to an etching gas containing chlorine and oxygen, the etching rate is increased, the processing time per substrate (wafer) is shortened, and the productivity is improved. However, when the fluorine-containing gas is simply added, the side wall protection is insufficient, so that etching proceeds isotropically, the dimensional accuracy is lowered, and it is impossible to process into a shape perpendicular to the depth direction. As the sidewall protective film, a film capable of preventing the entry of F radicals is necessary. For example, a film mainly composed of an oxide containing oxygen in an etching gas and silicon in an etching material has insufficient F radical resistance. It is. In this invention, the resist layer is positively etched to form a sidewall protective film mainly composed of a dense and thick CF polymer containing carbon supplied from the resist layer and fluorine in the etching gas. Since isotropic etching is performed, the bulk portion of the silicon layer can be processed into an anisotropic shape with high dimensional accuracy.

  In the step of correcting the anisotropic shape of the patterned silicon layer, a gas containing chlorine and oxygen but not fluorine is used as an etching gas. The reason for not adding the fluorine-containing gas is to slow down the etching rate and enable fine correction. When over-etching is performed by plasma etching using such an etching gas, it is possible to eliminate the etching residue of the silicon and the bottom shape of the lower part of the silicon layer without generating a notch on the side wall of the silicon layer. The side wall can have a vertical shape.

  In the dry etching method of the present invention, in the step of forming the resist layer, the silicon layer is covered on one main surface of the substrate so that the area occupied by the resist on one main surface of the substrate is 10 to 40%. Forming an additional resist layer different from the resist layer by the photolithography process, and in the step of patterning the silicon layer and the step of correcting the anisotropic shape of the patterned silicon layer, the silicon layer is added Plasma etching may be performed in a state covered with the resist layer, and the remaining portion of the additional resist layer may be removed in the removing step. In this way, even when the patterning resist layer alone is insufficient to supply carbon for forming the sidewall protective film, sufficient carbon can be supplied. When the area occupied by the resist on one main surface of the substrate is smaller than 10%, a sufficient side wall protection effect cannot be obtained due to insufficient carbon supply, and the controllability of dimensions and shapes deteriorates. If the area occupied by the resist on one main surface of the substrate exceeds 40%, the number of chips per substrate (wafer) decreases, leading to an increase in cost.

  According to the present invention, a silicon layer made of polysilicon or amorphous silicon having a thickness of 1 to 15 μm is anisotropically etched by plasma etching using an etching gas containing chlorine, oxygen and fluorine and using a resist layer as a mask. At this time, etching is performed while forming a side wall protective film containing CF polymer as a main component on the side wall of the etched portion of the silicon layer, and then over-etched by a plasma etching process using an etching gas containing chlorine and oxygen but not fluorine. Since etching is performed, an effect that the silicon layer can be processed into an anisotropic shape with high dimensional accuracy can be obtained. In addition, since there is no need to introduce new equipment, there is an advantage that the cost is not increased.

  1 to 4 show an example of a manufacturing method of a microstructure employing the dry etching method of the present invention, and steps (1) to (4) corresponding to the respective drawings will be described sequentially.

  (1) An insulating film 12 is formed on one main surface (upper surface) of the semiconductor substrate 10 made of, for example, single crystal silicon. 6 shows a cross section of the substrate orthogonal to the cross section of the substrate of FIG. 1. In FIG. 6, the cross section along the line XX ′ on the left side of the connected portion 10a of the substrate 10 is a portion 14A of the polysilicon layer 14 of FIG. Corresponds to the cross section. As the insulating film 12, a three-layer structure including the first to third insulating films 12a to 12c can be formed as shown in FIG. The insulating film 12a is used as a pad film, and is made of, for example, a silicon oxide film having a thickness of 50 to 400 nm. This silicon oxide film is formed by a thermal oxidation method or a CVD (Chemical Vapor Deposition) method.

  The insulating film 12b is used as an etching stopper film, and is made of, for example, a silicon nitride film having a thickness of 100 to 200 nm. This silicon nitride film is formed by a CVD method or the like. The insulating film 12c is used as a sacrificial film and is made of, for example, a silicon oxide film having a thickness of 1 to 4 μm. This silicon oxide film is formed by a CVD method or the like. As the insulating film 12c, a PSG (phosphorus silicate glass) film or a BPSG (boron phosphorus silicate glass) film may be used.

  Next, as shown in FIG. 6, a connection hole 15a corresponding to the connected portion 10a is formed in the insulating film 12c by a selective isotropic etching process. Then, in the stack of the insulating films 12a to 12c, a connection hole 15b that is continuous with the connection hole 15a and exposes the connected portion 10a is formed by a selective anisotropic etching process. Thereafter, as shown in FIGS. 1 and 6, polysilicon is deposited so as to cover the connection holes 15a and 15b and the insulating film 12, and conductive polysilicon having a thickness of 1 to 15 μm (preferably 2 to 5 μm) is doped. Polysilicon) layer 14 is formed. As shown in FIG. 6, the polysilicon layer 14 is formed so as to reach the connected portion 10a via the connection holes 15a and 15b. When the polysilicon layer 14 is formed, a resistance-reducing impurity such as phosphorus or boron is doped in-situ within the range of the impurity / silicon molar ratio of 0.05 to 0.20. This is for reducing the resistivity of the polysilicon layer 14 and facilitating the relaxation of the residual stress in the polysilicon layer 14. The sheet resistance of the polysilicon layer 14 after film formation is about 5 to 15Ω / □ when the thickness of the polysilicon layer 14 is 3 μm.

  Instead of the polysilicon layer 14, an amorphous silicon layer may be formed. The polysilicon layer 14 or the amorphous silicon layer may contain germanium or carbon. In this case, in order to perform etching under substantially the same conditions as polysilicon, the germanium content is set to 30 mol% or less and the carbon content is set to 10 mol% or less.

  Next, the polysilicon layer 14 is subjected to annealing treatment for stress relaxation. As the annealing treatment, RTA (Rapid Thermal Annealing) treatment is performed using a lamp annealing apparatus or the like. The RTA treatment has advantages such as improved throughput because the processing time is shorter than that of the furnace annealing treatment, and avoids fluctuations in characteristics even when an element such as a transistor is formed on the substrate 10.

  Next, resist layers 16a to 16c are formed on the polysilicon layer 14 according to predetermined electrodes or wiring patterns by photolithography. The resist layers 16a to 16c are a part of the resist layers for patterning formed in one sensor region 20a on the upper surface of the substrate (wafer) 10 shown in FIG. The sensor region 20a is a region where, for example, an acceleration sensor or the like is formed, and a sensor region juxtaposed portion 20 in which many such sensor regions are juxtaposed exists on the upper surface of the substrate 10. A resist layer for patterning is formed in the same manner as the resist layers 16a to 16c for each sensor region.

  When 10 to 40% (preferably 20 to 35%) of the resist occupying area cannot be secured by the patterning resist layer alone in the sensor region juxtaposing portion 20 on the upper surface of the substrate 10 shown in FIG. By providing the additional resist layer 16 around 20, the area occupied by the resist on the upper surface of the substrate 10 is set within a range of 10 to 40% (preferably 20 to 35%). The additional resist layer 16 is formed by diverting a photolithography process for forming a patterning resist layer such as the resist layers 16a to 16c.

  (2) Next, anisotropic etching (main etching) is performed on the bulk portion of the polysilicon layer 14 by plasma etching using the resist layers 16 and 16a to 16c as a mask. That is, in a region having a relatively large opening space (region having an aspect ratio of 1.0 or more [when the thickness of the polysilicon layer 14 is 3.0 μm, the region having an opening space of 3.0 μm or more]) By performing anisotropic etching until the insulating film (silicon oxide film) 12c is exposed, the polysilicon layer 14 is patterned to obtain a plurality of polysilicon layers 14a to 14c. As the etching conditions, the resist layers 16, 16a to 16c are positively etched, and the sidewall protective films 18a to 18c mainly composed of a CF polymer containing a resist reattachment (carbon) and fluorine in an etching gas are used. The controllability of size and shape is ensured by selecting the conditions such that the polysilicon layers 14a to 14c are formed on the side walls. Since the resist layers 16 and 16a to 16c are etched, they become thin as shown in FIG.

  Specifically, parameters such as pressure in the etching chamber, RF power, and microwave power are adjusted so that the resist / polysilicon etching rate ratio is 0.8 to 1.0. The wafer holding lower electrode is not particularly required to be at a low temperature, but a region where the pressure is increased as low-pressure high-density plasma, the RF power is increased, and the microwave power is slightly increased (not increased too much) is suitable.

As an example, when using a high-density plasma dry etching apparatus equipped with an ECR (Electron Cyclotron Resonance) plasma source, the etching conditions are:
Gas type: Cl ₂ / O ₂ / SF ₆
Gas flow ratio: Cl ₂ : O ₂ : SF ₆ = 10: 1 to 2: 0.1 to 2.0
(Preferably 0.8 to 1.2)
RF power: 60-80W (high ion energy side)
Microwave power: 1000-1400W (medium plasma density side)
Pressure: 3-8 mTorr (High-pressure side as a high-density plasma source)
Main coil 1 current: 35A
Main coil 2 current: 35A
Magnetic field adjustment coil current: 10A
Wafer holding lower electrode temperature: 10 to 20 ° C.
With automatic end point detection. As the high-density plasma dry etching apparatus, an ICP (inductive coupling) type apparatus or an apparatus using helicon waves may be used.

According to the anisotropic etching process described above, the side walls of the polysilicon layers 14a and 14c are processed into a substantially vertical shape in the wide space portion as shown in FIG. Further, in the narrow space portion, the lower portions of the polysilicon layers 14a to 14c have a skirt shape, or there are silicon etching residues at the bottom portion. These skirt shapes and etching residues are shown in FIG. Can be removed in the process. In the plasma etching process of FIG. 2, the etching rate of the polysilicon layer is increased by adding SF ₆ gas to the Cl ₂ / O ₂ mixed gas system, the processing time per wafer is shortened, and the productivity is improved. To do.

(3) Next, overetching is performed in situ on the polysilicon layers 14a to 14c by plasma etching using the resist layers 16 and 16a to 16c as a mask. That is, in the plasma etching process described above, the flow rate of SF ₆ gas is set to zero, the gas system is changed to a Cl ₂ / O ₂ mixed gas system, and the RF power is lowered slightly to slow the etching rate. By performing over-etching under such etching conditions, a region having a relatively narrow opening space (a region having an aspect ratio of 1.0 or less [when the thickness of the polysilicon layer 14 is 3.0 μm, the opening space is 3.0 μm) In the following region]), the etching residue of silicon and the bottom shape at the bottom of the polysilicon layer are removed, and the anisotropic shape of the polysilicon layers 14a to 14c is corrected as shown in FIG.

As an example, when performing over-etching using the high-density plasma etching apparatus used for the main etching in FIG.
Gas type: Cl ₂ / O ₂
Gas flow ratio: Cl ₂ : O ₂ = 10: 0.1 to 2.0 (preferably 0.8 to
1.2)
RF power: 30-60W (low ion energy side from main etching)
Microwave power: 1000-1400W (medium plasma density side)
Pressure: 3-8 mTorr (High-pressure side as a high-density plasma source)
Main coil 1 current: 35A
Main coil 2 current: 35A
Magnetic field adjustment coil current: 10A
Wafer holding lower electrode temperature: 10 to 20 ° C.
It can be. The O ₂ flow rate should be reduced as compared with the main etching. This is because O ₂ is supplied also from the insulating film (silicon oxide film) 12c as a base film, so that the etching shape is prevented from deteriorating due to excessive supply of O ₂ .

  According to the over-etching process described above, the sidewalls of the polysilicon layers 14a to 14c can have a vertical shape as shown in FIG. Further, a notch is not generated on the side walls of the polysilicon layers 14a to 14c, and a margin can be secured for the remaining amounts of the resist layers 16a to 16c.

  (4) Next, the remaining portions of the resist layers 16 and 16a to 16c and the remaining portions of the sidewall protective films 18a to 18c were removed and patterned by 130 buffered hydrofluoric acid treatment and sulfuric acid / hydrogen peroxide washing treatment. The polysilicon layers 14a to 14c are left. FIG. 7 shows a state after the removal process of FIG. 4 of the polysilicon layer 14a in the substrate portion shown in FIG. The polysilicon layer 14a includes a connection portion 14P connected to the connected portion 10a of the substrate 10 through the connection holes 15a and 15b, and an extension portion 14Q extending continuously above the connection portion onto the insulating film 12. And have. The annealing process described above with reference to FIG. 1 may be performed after the removal process of FIG.

  In the step of FIG. 8, the insulating film (sacrificial film) 12c is removed by wet etching. At this time, the insulating film 12b functions as an etching stopper film. The polysilicon layer 14a is connected to the connected portion 10a of the substrate 10 via the connection hole 15b, and is connected to the upper portion of the connecting portion and is spaced from the insulating film 12b and above the insulating film 12b. The extended portion 14Q is extended.

  In the microstructure shown in FIG. 7, the polysilicon layer 14a as a conductive member can be used as a fixed electrode or a wiring. In the microstructure shown in FIG. 8, the polysilicon layer 14a can be used as a cantilevered movable electrode in an acceleration sensor or the like, and if a connection portion similar to the connection portion 14P is added, the double-supported beam is used. It can also be used as a movable electrode of the type.

  According to the manufacturing method of the microstructure described above, in the anisotropic etching step of FIG. 2, the thick silicon layer 14 made of polysilicon or amorphous silicon having a thickness of 1 to 15 μm is processed into an anisotropic shape with high dimensional accuracy. can do. Further, since the etching rate is high, productivity is improved. In addition, in the overetching process of FIG. 3, the anisotropic shape of the polysilicon layers 14a to 14c can be further improved, and in the removing process of FIG. 4, the resist layers 16a to 16c and the sidewall protective films 18a to 18c. Can be easily removed. Therefore, a microstructure can be manufactured at low cost without adding new equipment.

  The present invention is not limited to the above-described embodiment, and can be implemented in various modifications. For example, the following changes are possible.

  (A) Although a silicon layer made of polysilicon or amorphous silicon doped with resistance-reducing impurities is targeted for etching, a silicon layer made of polysilicon or amorphous silicon that is not doped with resistance-reducing impurities may be etched. it can.

  (B) When germanium (Ge) or carbon (C) is included in polysilicon or amorphous silicon constituting the silicon layer to be etched, the Ge content is 1 to 30 mol% (preferably 5 to 15 mol%). , C content can be 0.5 to 10 mol% (preferably 1 to 5 mol%). Ge forms a solid solution with an arbitrary composition with Si. By including Ge, the temperature of the RTA can be lowered, for example, so that the polysilicon or the amorphous silicon layer is not distorted and warpage can be prevented. In addition, since C forms a Si—C bond in the polysilicon or amorphous silicon layer, the microstructure becomes hard and warpage can be prevented.

(C) The fluorine-containing gas is not limited to SF ₆ , and CHF ₃ , CF ₄ , C ₂ F _8, etc. may be used.

  (D) The polysilicon layer 14a as a conductive member may be connected to a conductive layer such as polysilicon provided on an insulating film covering the substrate 10 instead of being connected to the connected portion 10a of the substrate 10. Good. In this case, the insulating film 12 is formed so as to cover the conductive layer, and the polysilicon layer 14a is connected to the connected portion of the conductive layer via the connection holes 15a and 15b (or only 15b) provided in the insulating film 12. The Note that an insulating substrate may be used in place of the substrate 10 having an insulating film (an insulating film under the conductive layer) formed on one main surface.

It is sectional drawing which shows the insulating film formation process in the example of the manufacturing method of the microstructure which employ | adopted the dry etching method of this invention, a polysilicon deposition process, and a resist layer formation process. It is sectional drawing which shows the main etching process following the process of FIG. FIG. 3 is a cross-sectional view showing an overetching process following the process of FIG. 2. It is sectional drawing which shows the removal process of the resist layer and side wall protective film following the process of FIG. It is a top view which shows the resist layer formation condition of the board | substrate upper surface. FIG. 2 is a cross-sectional view showing an insulating film forming step, a connection hole forming step, and a polysilicon deposition step corresponding to FIG. 1 in a substrate cross section orthogonal to the substrate cross section of FIG. 1. FIG. 7 is a cross-sectional view showing a step of removing the resist layer and the sidewall protective film corresponding to FIG. 4 with respect to the cross section of the substrate in FIG. 6. FIG. 8 is a cross-sectional view showing a sacrificial film removing step that follows the step of FIG. 7.

Explanation of symbols

  10: substrate, 10a: connected portion, 12: insulating film, 14, 14a to 14c: polysilicon layer, 14P: connecting portion, 14Q: extended portion, 15a, 15b: connecting hole, 16, 16a to 16c: resist layer , 18a to 18c: side wall protective film, 20a: sensor region, 20: sensor region juxtaposed portion.

Claims (2)

Forming a silicon layer made of polysilicon or amorphous silicon having a thickness of 1 to 15 μm on one main surface of the substrate having at least one main surface having an insulating property;
Forming a resist layer having a thickness of 1 to 1.5 times the thickness of the silicon layer on the silicon layer according to a predetermined pattern by a photolithography process;
The silicon layer is formed on one main surface of the substrate while forming a side wall protective film on the side wall of the etched portion of the silicon layer by plasma etching using an etching gas containing chlorine, oxygen, and fluorine and using the resist layer as a mask. A step of patterning the silicon layer by anisotropic etching until reaching the surface, wherein the sidewall protective film includes carbon polymer reattached by etching of the resist layer and fluorine in the etching gas Forming a film mainly composed of
Overetching the patterned silicon layer by a plasma etching process using an etching gas containing chlorine and oxygen but not fluorine and using the resist layer as a mask to correct the anisotropic shape of the silicon layer; ,
A step of removing the remaining portion of the resist layer and the remaining portion of the sidewall protective film after the over-etching.   In the step of forming the resist layer, the silicon layer is covered on one main surface of the substrate so that the occupied area of the resist on one main surface of the substrate is 10 to 40%, and is different from the resist layer. In the step of forming an additional resist layer by the photolithography process and patterning the silicon layer and correcting the anisotropic shape of the patterned silicon layer, the silicon layer is covered with the additional resist layer. The dry etching method according to claim 1, wherein plasma etching is performed, and the remaining portion of the additional resist layer is removed in the removing step.

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