JP4028480B2 - FPGA configuration control method and control apparatus - Google Patents

Description

  The present invention relates to an FPGA configuration control method and an FPGA configuration control apparatus for controlling the configuration of an FPGA (Flexible Programmable Gate Array).

  The FPGA is a circuit whose hardware function can be changed by rewriting configuration data. Rewriting the configuration data of the conventional FPGA has been performed as follows.

  Configuration data is written to the flash memory from the remotely located host device through the active FPGA. An instruction is given to rewrite the configuration data written in the flash memory from the host device to the operating FPGA. The FPGA reads and updates the configuration data from the flash memory based on an instruction from the host device.

  On the other hand, when the FPGA is configured from the data written to the flash memory, the data written to the flash memory is incomplete, or the FPGA configuration is started after writing incorrect data to the flash memory Cannot successfully complete the FPGA configuration.

  Conventionally, when the FPGA configuration data has not been completed due to the already written data, the configuration data is transmitted to the FPGA not operating from the host device, and the configuration is performed again. I can't.

  Therefore, in order to recover, the FPGA configuration is completed by rewriting data by connecting a dedicated FPGA write-only terminal directly to the FPGA.

  Further, there are the following documents 1 and 2 as prior art documents.

  Document 1 stores two or more sets of configuration data in a configuration memory, selects one of the two or more sets of configuration data with a switch, outputs it to a routing matrix, and performs configuration. , An implementation of a plurality of logic functions in an FPGA is disclosed.

Document 2 discloses that the configuration data is read from the nonvolatile memory in which the program and configuration data are stored by the control device, the FPGA is configured, and part or all of the data in the nonvolatile memory is rewritten. is doing.
JP-A-8-51356 JP 2003-44303 A

  However, in the conventional FPGA configuration method, as described above, if the FPGA configuration is not completed with already written data, the FPGA configuration cannot be automatically restarted.

  In addition, if the FPGA configuration fails, the FPGA itself does not function normally, so that the FPGA data cannot be rewritten from the host device. To restore the device, a manual FPGA write-only terminal is connected and the data is restored. Since there was only a means other than rewriting, the maintainability was bad.

  Reference 1 can implement a plurality of logical functions in one FPGA, but does not disclose any case where the configuration fails due to an error in the configuration data, so the above-mentioned problems cannot be solved. .

  According to Document 2, the configuration data stored in the non-volatile memory has an error or the like, and in order to restore the device when the configuration fails, the CPU rewrites the data in the non-volatile memory and performs configuration again. Although it is necessary, since it does not automatically perform reconfiguration, there is a problem that the function of the FPGA remains stopped until the reconfiguration is completed, and the apparatus does not operate.

  The present invention has been made in view of the above, and provides an FPGA configuration control method and a control apparatus capable of completing the configuration of the FPGA normally even if the written FPGA data is incomplete or incorrect. That is.

  FIG. 1 shows the principle of the present invention. As shown in FIG. 1, the FPGA configuration control device includes a memory 2, a data rewrite unit 4, a first configuration unit 6, a surface switching unit 8, and a second configuration unit 10.

  The memory 2 has an area for the data storage surface display flag 12 and first and second surfaces for storing data. The data rewrite unit 4 stores the rewrite data on any one of the first and second surfaces 14 # 1 and 14 # 2 corresponding to the work surface indicated by the data storage surface display flag 12.

  The first configuration unit 6 configures the FPGA based on the rewrite data stored on the working surface indicated by the data storage surface display flag 12. When the configuration is completed, the surface switching unit 8 updates the data storage surface display flag 12 so that the current working surface becomes the protection surface and the current protection surface becomes the working surface.

  If the configuration fails, the second configuration unit 10 selects one of the first and second surfaces 14 # 1 and 14 # 2 corresponding to a protection surface different from the working surface indicated by the data storage surface display flag 12. The FPGA is configured based on the data stored in the plane.

  Even if the configuration fails in this way, the configuration is automatically performed based on the previously completed configuration data stored in the protected surface, eliminating the need to configure by connecting a dedicated terminal. .

  According to the present invention, the FPGA data storage surface is composed of two surfaces, a working surface and a protection surface, and even if the FPGA configuration by the rewrite data stored in the working surface fails, the data before the FPGA data rewrite is automatically performed. System failure can be avoided by starting the FPGA configuration from the protected surface storing the.

  Further, since the data storage surface display flag is stored and controlled in the memory, it is possible to start up the apparatus with data for which FPGA data rewriting has been normally completed normally, so that reliability can be improved.

  In addition, even if the FPGA configuration by remote FPGA data rewriting fails, since the restoration means other than the manual rewriting by the dedicated terminal is implemented, the maintainability in the field is remarkably improved.

  FIG. 2 is a block diagram of an FPGA configuration control apparatus according to an embodiment of the present invention. As shown in FIG. 2, the FPGA configuration control device includes an upper device 50, a lower device 52, and an FPGA data writing dedicated terminal (hereinafter abbreviated as a dedicated terminal) 54.

  The host device 50 is a device that performs processing related to configuration rewriting, such as transmission of rewrite data and a configuration start instruction, and other processing to the lower device 52, and is, for example, a server device. The host device 50 includes a storage unit 100, a CPU 102, and an I / O unit 104.

  The storage unit 100 is a memory that stores rewrite data and the like, a program related to configuration rewrite processing, other programs, and the like. The CPU 102 executes a program related to configuration rewriting stored in the storage unit 100.

  In the configuration rewriting, transmission of rewrite data and a configuration start instruction are performed to the lower device 52 through the I / O unit 104. The I / O unit 104 communicates with the lower device 52 according to a predetermined interface.

  The subordinate device 52 is a device including the FPGA 158, and is, for example, a router. The lower level device 52 includes an SDRAM 150, a BOOT 152, a CPU 154, I / O 156 # 0 and 156 # 1, an FPGA 158, a configuration control unit 160, a connector 162, and a flash memory 164.

  The SDRAM 150 is a memory that stores a program related to configuration rewriting executed by the CPU 154. In configuration rewriting, (i) receiving rewrite data from the I / O 156 # 0 and instructing the FPGA 158 to output the configuration data to the configuration control unit 160. (ii) configuration from the I / O 156 # 0 A program for receiving the start instruction and instructing the FPGA 158 to output the configuration start to the configuration control unit 160 is stored.

  The BOOT 152 is a memory that stores a boot program. The CPU 154 executes a program stored in the SDRAM 150 or the BOOT 152. The I / O 156 # 0 controls the interface between the external port connected to the host device 50 and the bus 155.

  That is, data addressed to the CPU 154 is received from the host device 50 and output to the bus 155, and data addressed to the host device 50 is received from the bus 155 and transmitted to the host device 50. I / O # 1 provides an interface between the external port and the bus 155. The bus 155 is a bus that communicates between the CPU 154 and the FPGA 158, I / O 156 # 0, 156 # 1.

  The FPGA 158 includes an interface unit that transmits / receives data between the buses 155 and an interface unit that outputs data reception and configuration completion notification from the signal line 159 to the signal line 159 and has the following functions.

  (I) When data is received from the bus 155 through a predetermined interface, when the data is addressed to the configuration control unit 160, the data is output to the signal line 159. The relevant data is data related to the configuration, and includes rewrite data and a configuration start instruction.

  (Ii) When data is received from the bus 155 and the data is not addressed to the configuration control unit 160, it operates as hardware based on the data.

  (Iii) Data is received from the signal line 159 and stored in a register having an address corresponding to the data. When it is confirmed that all data is stored in the register and operates as hardware, a configuration completion notification is output to the signal line 159.

  (I) and (ii) function when the configuration is completed and the FPGA 160 is operating normally.

  The signal line 159 connects between the FPGA 158 and the configuration control unit 160. The configuration control unit 160 is connected to the signal line 159 to which the FPGA 158 is connected, the connector 162 to which the dedicated terminal 54 is connected, and the signal line 163 to which the flash memory 164 is connected, and performs the control described below related to the FPGA configuration. Do.

  FIG. 3 is an example of a configuration diagram of the flash memory 164 in FIG. As shown in FIG. 3, the flash memory 164 includes a plane management information area 250, an A-plane area 252 # A, and a B-plane area 252 # B. The surface management information area 250 includes a data storage surface display flag 260, a working surface write flag 262, and a data storage surface copy completion flag 264.

  The data storage plane display flag 260 is a flag for displaying whether the A plane area 252 # A is the working plane or the protect plane among the data storage areas 252 # A and 252 # B mounted on the two planes. is there. For example, “1” is set if the A plane 252 # A is a working plane, and “0” is set if the B plane 252 # B is a working plane.

  The working surface writing flag 262 displays whether data has been written to the working surface from the host device 50 or the dedicated terminal 54. For example, “1” is written when data is written, and “0” is written otherwise.

  When this flag 262 is set (“1”), there is a difference between the data stored on the working surface and the protection surface, so after storing the data on the working surface, the FPGA configuration is performed and the data is normal. It shows that it is necessary to switch data from the working surface to the protected surface and to copy data from the working surface to the protected surface.

  The data storage surface copy completion flag 264 displays whether or not the data storage surface copy has been performed. When initial data or rewrite data is written to the working surface, for example, “0” is written in the flag 264 to cancel the flag, and when the data is copied, the flag 264 is set (“1”). )

  When the configuration disclosure instruction / power-on / switch-on from the host device 50 completes the FPGA configuration based on the data on the working surface and the data is copied to the protected surface, or the FPGA configuration based on the data on the protected surface is completed. When the data is copied to the working surface, the flag 264 is set (“1”).

  The A plane 252 # A and the B plane 252 # B are data storage areas in which the flash memory 164 is divided into two planes. For example, the data area is divided into two by the address of the flash memory 164. Surface 252 # A and the one with the larger address are referred to as surface B 252 # B.

  The dedicated terminal 54 designates one of the writing surfaces A and B through the connector 162 and transmits initial data to the configuration control unit 160.

  FIG. 4 is a functional block diagram of the configuration control unit 160 in FIG. As illustrated in FIG. 4, the configuration control unit 160 includes an initial data writing unit 200, a data rewrite processing unit 202, a configuration unit 204, and a data copy unit 206.

  The initial data writing unit 200 writes the data received from the dedicated terminal 54 to the flash memory 164 as follows.

  FIG. 5 is an operation flowchart of the initial data writing unit 200. In step S <b> 2, it is determined whether an A-side and B-side write instruction is received from the dedicated terminal 54. If a write instruction is received, the process proceeds to step S4. When a write instruction has not been received, the process waits in step S2.

  In step S3, it is determined whether or not writing to the flash memory 164 is in progress. If not writing, the process proceeds to step S4. If writing is in progress, the process is terminated.

  In step S4, it is determined whether or not the write instruction is the A side. If the writing instruction surface is the A surface, the process proceeds to step S6. If the writing instruction surface is the B surface, the process proceeds to step S8.

  In step S6, the data received from the dedicated terminal 54 is written to the A side 252 # A of the flash memory 164. That is, the data is sequentially written in the address area of the A surface 252 # A of the flash memory 164 corresponding to the data.

  In step S8, the data received from the dedicated terminal 54 is written to the B surface 252 # B of the flash memory 164. While the data received from the dedicated terminal 54 is being written to the flash memory 164, writing from the host device 50 is prohibited.

  In step S10, the data storage surface display flag 260 of the flash memory 164 indicating whether the working surface is the A or B surface is set so as to indicate the writing instruction surface. For example, “1” is set in the data storage surface display flag 260 if the write instruction surface is the A surface, and “0” is set in the data storage surface display flag 260 if the write instruction surface is the B surface.

  In step S12, “1” is set to the working surface write flag 262 to indicate that the data is stored in the working surface in the flash memory 164 and does not match the data stored in the protect surface.

  In step S14, the data storage surface copy completion flag 264 indicating that copying of the data written in steps S6 and S8 to the protected surface is not completed is canceled (“0”).

  The data rewrite processing unit 202 writes the configuration rewrite data received from the FPGA 158 to the flash memory 164 as follows.

  FIG. 6 is an operation flowchart of the data rewrite processing unit 202. In step S50, it is determined whether a write instruction is received from the FPGA 158. If a write instruction is received, the process proceeds to step S52. When the write instruction has not been received, the process waits in step S50.

  In step S52, it is determined whether writing to the flash memory 164 is in progress. If not writing, the process proceeds to step S54. If writing is in progress, the process is terminated.

  In step S54, the data storage surface display flag 260 is acquired from the flash memory 164. In step S56, it is determined by the data storage surface display flag 260 whether or not the working surface is the A surface. If the working surface is the A surface, the process proceeds to step S58. If the working surface is the B surface, the process proceeds to step S60.

  In step S58, the rewrite data received from the FPGA 158 is written to the A side. In step S60, the rewrite data received from the FPGA 158 is written on the B side. While the rewrite data is being written to the flash memory 164, writing from the dedicated terminal 54 is prohibited.

  In step S60, a working surface write flag 262 is set (“1”) indicating that the rewrite data has been written to the working surface of the flash memory 164. In step S62, the data storage surface copy completion flag 264 indicating that the copy of the rewrite data stored in steps S58 and S60 on the protected surface is not completed is canceled (“0”).

  The configuration unit 204 configures the FPGA 158 with data stored on the working surface of the flash memory 164 as follows.

  FIG. 7 is an operation flowchart of the configuration unit 204. In step S100, it is determined whether or not the FPGA 158 receives the FPGA start instruction / power is turned on / switched on. If the FPGA start instruction is received / power is turned on / switched on, the process proceeds to step S102. If the FPGA start instruction is received, the power is on, and the switch is not turned on, the process waits in step S100.

  The FPGA start instruction is issued from the higher-level device 50 to the lower-level device 52 in order to perform FPGA configuration based on the rewrite data. Power on / switch on is a trigger for performing FPGA configuration with initial data.

  In step S102, the FPGA configuration is started with the data stored in the working plane indicated by the data storage plane display flag 260 in the flash memory 164. In other words, the data is read from the working surface and the data is written to the register at the corresponding address of the FPGA 158.

  In step S104, a configuration monitoring timer is started. In step S <b> 106, it is determined whether all the data stored in the working surface is written in the FPGA 158 and a configuration completion notification indicating that the FPGA 158 has started operating normally has been received from the FPGA 158.

  If a configuration completion notification is received, the process proceeds to step S107. If the configuration completion notification has not been received, the process proceeds to step S108. In step S107, a configuration completion notification is sent to the host device 50 through the FPGA 158 and the CPU 154.

  In step S108, it is determined whether or not the configuration completion monitoring timer has overflowed (timed out). If timed out, the process proceeds to step S110. If not timed out, the process returns to step S106.

  In step S110, the retry counter is incremented by one. The retry counter is initialized when the configuration starts. In step S112, it is determined whether the number of retries on the working side has expired.

  If the number of retries has expired, the data stored in the working surface is incomplete, or the FPGA has not been completed because incorrect data has been written, so the process proceeds to step S114. If the number of retries has not expired, the process returns to step S102.

  In step S114, FPGA configuration is started using data stored on the protected surface indicated by the data storage surface display flag 260 in the flash memory 164.

  In step S116, a configuration monitoring timer is started. In step S118, it is determined whether a configuration completion notification is received from the FPGA 158 or not. If a configuration completion notification is received, the process proceeds to step S107. If the configuration completion notification has not been received, the process proceeds to step S120.

  In step S120, it is determined whether or not the configuration completion monitoring timer has overflowed (timed out). If timed out, the process proceeds to step S122. If not timed out, the process returns to step S118.

  In step S122, the retry counter is incremented by one. The retry counter is initialized when the configuration starts. In step S124, it is determined whether or not the number of retries on the protected surface has expired. If the number of retries has expired, the process proceeds to step S126. If the number of retries has not expired, the process returns to step S114.

  In step S126, the CPU 154 notifies the host device 50 that a device failure has occurred by not sending a normal configuration end notification within a predetermined time.

  The reason why it is determined that a device failure has occurred is that the data stored in the protected surface is data that has been successfully completed in FPGA configuration before, and it is considered that there is no error in the data.

  As described above, when the configuration using the data stored in the working plane fails, the configuration is automatically resumed with the data stored in the protect plane, so the dedicated terminal 54 is connected to perform the configuration. There is no need.

  FIG. 8 is an operation flowchart of the data copy unit 206. In step S150, it is determined whether the working surface configuration is completed. If the working surface configuration is completed, the process proceeds to step S152. If the working surface configuration is not completed, the process proceeds to step S170.

  In step S152, it is determined whether the working surface writing flag 262 is set (“1”). If the working surface writing flag 262 is set, the process proceeds to step S154. If the working plane write flag 262 is not set, it is identified that the same data is stored in the working plane and the protect plane, and the data copy is terminated without executing.

  In step S154, data copying is started from the working surface indicated by the data storage surface display flag 260 of the flash memory 164 to the protected surface. In step S156, it is determined whether or not copying has been completed. If the copying is completed, the process proceeds to step S158. If the copying has not been completed, data loop is continued in a loop in step S156.

  In step S158, the working surface write flag 262 of the flash memory 164 is canceled (“0”). In step S160, the data storage surface copy completion flag 264 is canceled (“0”).

  In step S162, the data storage surface display flag 260 is updated so that the current working surface becomes the protection surface and the current protection surface becomes the working surface, and the working surface and the protection surface are switched.

  As a result, the data on the working surface and the protect surface coincide with each other, and the data whose configuration is completed is stored in the protect surface.

  In step S170, it is determined whether protection surface configuration is completed. If the protection surface configuration is completed, the process proceeds to step S172. If the protection surface configuration has not been completed, the process ends.

  In step S172, data copy is started from the protected surface indicated by the data storage surface display flag 260 of the flash memory 164 to the working surface. In step S174, it is determined whether or not copying has been completed. If the copying is completed, the process proceeds to step S176. If the copying has not been completed, the loop is continued in step S174.

  In step S176, the working surface writing flag 262 is canceled (“0”). In step S178, the data storage surface copy completion flag 264 is set (“1”).

  At this time, since the working surface and the protection surface are not switched, the next rewrite data is stored in the working surface, and an environment for completing the FPGA configuration on the working surface is constructed.

  FIGS. 9A to 9E are diagrams showing the FPGA configuration method. Hereinafter, the FPGA configuration method of the present invention will be described.

(A) Writing Initial Data The dedicated terminal 54 designates one of the writing surfaces A and B, and transmits initial data to the configuration control unit 160 through the connector 162.

  As described above, the configuration control unit 160 receives the initial data from the dedicated terminal 54 and, as shown in FIG. 9A, the designated writing surface in the flash memory 164, for example, the A surface 252 #. The data storage surface display flag 260 is set (“1”), the working surface writing flag 262 is set (“1”), and the data storage surface copy completion flag is set so that the written surface 252 # A becomes the working surface. H.264 is released (“0”).

(B) FPGA Configuration of Initial Data When the power supply is turned on / switched on, the configuration control unit 160 starts configuration of the FPGA 158 with the data stored in the working surface as described above.

  When the configuration is completed, the working plane write flag 262 is set (“1”). Therefore, as shown in FIG. 9B, the data stored in the working plane is copied to the protect plane and the working plane is copied. The surface write flag 262 is canceled (“0”), and the data storage surface copy completion flag 264 is set (“1”).

  The data storage surface display flag 260 is updated (“0”) so that the current protection surface 262 # B is the working surface and the current working surface 262 # A is the protection surface, and the working surface is switched.

  As a result, initial data is configured in the FPGA 158, and the FPGA 158 starts operation. In addition, data for which configuration has been completed is stored in the protected surface. If configuration fails, the above steps (a) and (b) are re-executed.

(C) Rewriting Data The upper device 50 transmits the rewritten data to the configuration control unit 160 through the CPU 154 and the FPGA 158 of the lower device 52. As shown in FIG. 9C, the configuration control unit 160 stores the rewrite data on the working surface indicated by the data storage surface display flag 260, for example, the B surface 162 # B, and sets the working surface write flag 262. ("1") and the data storage surface copy completion flag 264 is canceled ("0").

(D) FPGA Configuration of Rewrite Data The host device 50 issues a configuration start instruction to the configuration control unit 160 through the CPU 154 and the FPGA 158 of the lower device 52. When the configuration control unit 160 receives the configuration start instruction, the configuration control unit 160 configures the FPGA 158 with the rewrite data stored in the working surface indicated by the data storage surface display flag 260.

  When the configuration is completed, since the working surface write flag 262 is set (“1”), as shown in FIG. 9D, the data stored in the working surface, for example, the B surface 162 # B is stored. Copy to the protected surface, release the working surface write flag 262 (“0”), and set the data storage surface copy completion flag 264 (“1”).

  The data storage surface display flag 260 is updated (“1”) so that the current protected surface is the working surface and the current working surface is the protected surface, and the working surface is switched.

  If the configuration fails, the data stored in the protected surface is configured in the FPGA 158. When the configuration is completed, since the working surface write flag 262 is set (“1”), the data stored in the protected surface, for example, the A surface 262 # A, as shown in FIG. The data is copied to the working surface, the working surface write flag 262 is canceled (“0”), and the data storage surface copy completion flag 264 is set (“1”).

  As described above, as long as no device failure has occurred, it is possible to start up the device on the protected surface even if the FPGA configuration based on the data stored in the working surface is not completed. At this time, the apparatus becomes the FPGA data at the time before the FPGA data is rewritten from the host apparatus.

The present invention includes the following supplementary notes.
(Supplementary Note 1) In the FPGA configuration control method for configuring the FPGA,
Data to be rewritten in one of the first and second planes corresponding to the working plane indicated by the data storage plane display flag of the memory having the first and second planes for storing data and the area for setting the data storage plane display flag A first step of storing
A second step of configuring the FPGA based on rewrite data stored in the working surface indicated by the data storage surface display flag;
When the configuration is completed, a third step of updating the data storage surface display flag so that the current working surface is a protection surface and the current protection surface is a working surface;
If the configuration fails, the FPGA is configured based on the data stored in one of the first and second surfaces corresponding to the protected surface different from the working surface indicated by the data storage surface display flag. A fourth step to perform;
An FPGA configuration control method comprising:
(Supplementary Note 2) The third step includes a step of copying data stored in one of the first and second surfaces corresponding to the working surface indicated by the data storage surface display flag to the other surface. The FPGA configuration control method according to appendix 1, characterized by:
(Supplementary Note 3) In the fourth step, data stored in one of the first and second surfaces corresponding to the protected surface different from the working surface indicated by the data storage surface display flag is copied to the other surface. The FPGA configuration control method according to claim 1, further comprising steps.
(Supplementary Note 4) A step of storing initial data in any one of the first and second surfaces, and setting the data storage surface display flag so that the surface storing the initial data becomes a working surface; The FPGA configuration control method according to appendix 1, further comprising a step of configuring the FPGA based on initial data stored in a working plane indicated by a data storage plane display flag.
(Supplementary Note 5) In the FPGA configuration control device that configures the FPGA,
A memory having a data storage surface display flag area and first and second surfaces for storing data;
A data rewrite unit for storing rewrite data on any one of the first and second surfaces corresponding to the work king indicated by the data storage surface display flag;
A first configuration unit configured to configure the FPGA based on rewrite data stored in a working surface indicated by the data storage surface display flag;
When the configuration is completed, a surface switching control unit that updates the data storage surface display flag so that the current working surface is a protected surface and the current protected surface is a working surface;
If the configuration fails, the FPGA is configured based on the data stored in one of the first and second surfaces corresponding to the protected surface different from the working surface indicated by the data storage surface display flag. A second configuration section to perform;
An FPGA configuration control apparatus comprising:
(Additional remark 6) When the configuration by the 1st configuration part was completed, it further provided the 1st data copy part which copies the data stored in the working surface which the said data storage surface display flag shows to a protection surface The FPGA configuration control device according to appendix 5, characterized by:
(Supplementary Note 7) When the configuration by the second configuration unit is completed, a second data copy unit that copies the data stored in the protection surface different from the working surface indicated by the data storage surface display flag to the working surface The FPGA configuration control device according to appendix 6, further comprising:
(Supplementary Note 8) An initial data writing unit that receives initial data from a dedicated terminal and stores it in a working surface indicated by the data storage surface display flag; and a working surface indicated by the data storage surface display flag when the power is turned on. A third configuration unit configured to configure the FPGA based on the initial data stored in the memory, and when the configuration by the third configuration unit is completed, the configuration data is stored in the working surface indicated by the data storage surface display flag. The FPGA configuration control device according to appendix 5, further comprising a third data copy unit that copies the initial data to the protected surface.
(Supplementary note 9) The FPGA configuration control device according to supplementary note 5, wherein the rewrite data is transmitted by a host device and received through the FPGA.

It is a principle diagram of the present invention. It is a block diagram of the configuration control apparatus by embodiment of this invention. FIG. 3 is a configuration diagram of a flash memory in FIG. 2. FIG. 3 is a functional block diagram of a configuration control unit in FIG. 2. It is an initial data write operation flowchart. It is a rewrite data writing operation flowchart. It is a FPGA configuration operation | movement flowchart. It is an operation | movement flowchart of a data copy. It is a figure which shows the FPGA configuration control method.

Explanation of symbols

2 memory 4 data rewrite unit 6 first configuration unit 8 screen switching unit 10 second configuration unit 12 data storage surface display flag 14 # 1 first surface 14 # 2 second surface 16 FPGA

Claims (2)

An upper device, a dedicated terminal, an FPGA connected to the upper device that notifies the completion of configuration when the configuration is normally completed and starts operation as hardware based on data from the upper device, and the FPGA and the In an FPGA configuration control method using an FPGA configuration control device having a lower-level device including a configuration control unit connected to a dedicated terminal ,
The configuration control unit
Receiving the initial data transmitted from the dedicated terminal, and storing the initial data in the working surface of the memory having first and second surfaces, one of which is a working surface and the other is a protection surface;
Configuring the FPGA based on the initial data stored in the working surface of the memory based on a predetermined trigger;
Storing the initial data stored in the working plane in the protection plane upon notification of completion of the configuration based on the initial data from the FPGA ;
Receiving rewrite data from the host device through the FPGA and copying it to the working surface of the memory;
Configuring the FPGA based on the rewrite data stored in the working surface of the memory based on a predetermined trigger;
Copying the rewrite data stored in the working surface to a protection surface when the configuration completion notification based on the rewrite data is received from the FPGA;
When the configuration completion notification is not sent from the FPGA within a predetermined time from the start of configuration based on the rewrite data, the FPGA is configured based on data stored in the protection plane; and
The FPGA configuration control method characterized by performing this . A host device, a dedicated terminal, and a lower device including an FPGA and a configuration control unit that notifies the completion of configuration when the configuration is normally completed and starts operation as hardware based on data from the host device. The FPGA and the FPGA are connected, the FPGA and the configuration control unit are connected, and the dedicated terminal and the configuration control unit are connected,
The configuration control unit
An initial data writing unit that receives initial data transmitted from the dedicated terminal and stores the initial data in the working surface of the memory having first and second surfaces, one of which is a working surface and the other is a protection surface When,
A first configuration unit configured to configure the FPGA based on the initial data stored in the working surface of the memory based on a predetermined trigger;
A first data copy unit configured to copy the initial data stored in the working surface to the protection surface when the configuration completion notification based on the initial data is received from the FPGA;
A data rewrite unit that receives rewrite data from the host device through the FPGA and stores the rewrite data in the working surface of the memory;
A second configuration unit configured to configure the FPGA based on the rewrite data stored in the working surface of the memory based on a predetermined trigger;
A second data copy unit configured to copy the rewrite data stored in the working surface to the protection surface when the configuration completion notification based on the rewrite data is received from the FPGA;
A third configuration unit configured to configure the FPGA based on data stored in the protection plane when the configuration completion notification from the FPGA is not performed within a predetermined time from the start of configuration based on the rewrite data;
An FPGA configuration control device comprising:

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