JP4025165B2 - 半導体装置 - Google Patents

半導体装置 Download PDF

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Publication number
JP4025165B2
JP4025165B2 JP2002289642A JP2002289642A JP4025165B2 JP 4025165 B2 JP4025165 B2 JP 4025165B2 JP 2002289642 A JP2002289642 A JP 2002289642A JP 2002289642 A JP2002289642 A JP 2002289642A JP 4025165 B2 JP4025165 B2 JP 4025165B2
Authority
JP
Japan
Prior art keywords
electrode
bump electrode
wiring
bump
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP2002289642A
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English (en)
Japanese (ja)
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JP2004128183A (ja
JP2004128183A5 (https=
Inventor
和弘 伴
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Renesas Technology Corp
Original Assignee
Renesas Technology Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Renesas Technology Corp filed Critical Renesas Technology Corp
Priority to JP2002289642A priority Critical patent/JP4025165B2/ja
Publication of JP2004128183A publication Critical patent/JP2004128183A/ja
Publication of JP2004128183A5 publication Critical patent/JP2004128183A5/ja
Application granted granted Critical
Publication of JP4025165B2 publication Critical patent/JP4025165B2/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/012—Manufacture or treatment of bump connectors, dummy bumps or thermal bumps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/15—Encapsulations, e.g. protective coatings characterised by their shape or disposition on active surfaces of flip-chip devices, e.g. underfills
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/724—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked insulating package substrate, interposer or RDL
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/734—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked insulating package substrate, interposer or RDL

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  • Wire Bonding (AREA)
JP2002289642A 2002-10-02 2002-10-02 半導体装置 Expired - Fee Related JP4025165B2 (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2002289642A JP4025165B2 (ja) 2002-10-02 2002-10-02 半導体装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2002289642A JP4025165B2 (ja) 2002-10-02 2002-10-02 半導体装置

Related Child Applications (2)

Application Number Title Priority Date Filing Date
JP2007210647A Division JP4585557B2 (ja) 2007-08-13 2007-08-13 半導体装置の製造方法
JP2007210644A Division JP4585556B2 (ja) 2007-08-13 2007-08-13 半導体装置

Publications (3)

Publication Number Publication Date
JP2004128183A JP2004128183A (ja) 2004-04-22
JP2004128183A5 JP2004128183A5 (https=) 2005-11-04
JP4025165B2 true JP4025165B2 (ja) 2007-12-19

Family

ID=32281747

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2002289642A Expired - Fee Related JP4025165B2 (ja) 2002-10-02 2002-10-02 半導体装置

Country Status (1)

Country Link
JP (1) JP4025165B2 (https=)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4990711B2 (ja) * 2007-07-27 2012-08-01 ソニーケミカル＆インフォメーションデバイス株式会社 Ｉｃチップの製造方法及びｉｃチップの実装方法

Also Published As

Publication number Publication date
JP2004128183A (ja) 2004-04-22

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