JP4021807B2 - Abnormal current monitoring circuit - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention is provided as a W-CDMA (wideband-code division multiple access) mobile phone system base station as a monitoring target circuit that is applied to a tower top receiving amplifier or the like attached to an antenna tower or the like. The present invention relates to a monitoring circuit that monitors devices using a circuit that compares and determines monitoring load currents of a large number of monitoring target circuits.
[0002]
[Prior art]
Some conventional monitoring circuits have a comparison circuit to determine whether the received electric field level is equal to or lower than a predetermined value and to obtain the determination output. (For example, refer to Patent Document 1).
[0003]
[Patent Document 1]
Japanese Examined Patent Publication No. 6-103870 (page 3, column 5, lines 25-31, FIG. 2 (B))
[0004]
3 to 4 are explanatory diagrams of examples of an abnormal current monitoring circuit conventionally used.
First, FIG. 3 is an explanatory diagram of an example in which the present invention is applied to a tower-top receiving amplifier system. The tower-top receiving amplifier is installed in the vicinity of an antenna arranged on the top of a tower, etc., and amplifies a radio frequency emitted from a mobile device or the like induced by the antenna with a predetermined amplification, As an output, it is supplied to the radio equipment in the station via a power feeding cable. The tower-top receiving amplifier outputs an input radio frequency signal as a radio frequency signal obtained through a parallel connection and a series connection of a low noise amplifier (LNA) to obtain a predetermined amplification degree.
Between each LNA (1 to 4) and the power source Vcc, for example, a drain current of a FET (field effect transistor) amplifier circuit is used as a load, and a resistor for detecting a potential difference is inserted into the drain load circuit. The potential difference (V _{1 to} V ₄ ) is detected by the potential difference detection unit 1 by the current passed through each resistor. Each detected potential difference (V _{1 to} V ₄ ) is input to the DC amplification unit 2 where it is DC amplified. Each DC output of the DC amplification unit 2 is input to the comparison unit 3, where the highest value, the lowest value and a predetermined value are compared and determined, and output as an alarm signal. The alarm signal is output to the outside and used in a system such as alarm display and alarm control for monitoring each power supply current abnormal value of each LNA of the tower-top receiving amplifier.
[0005]
Next, FIG. 4 is a circuit explanatory diagram detailing a conventional example. Potential difference detection having a plurality of circuits for detecting currents flowing through a plurality of loads (M ₁ , M ₂ ,... M _n ) of the monitored circuit as potential differences (V ₁ , V ₂ ,... V _n ), respectively. Unit 1, and a DC amplification unit 2 having a plurality of DC amplification circuits (A ₁ , A ₂ ,... A _n ) for amplifying the potential differences (V ₁ , V ₂ ,... V _n ), respectively, A plurality of comparison judgment circuits (C ₁ (C _1u , C _1l ), C ₂ (C _2u , C _2l ) for judging whether the output voltage of the amplifying unit 2 is a voltage not less than a predetermined upper limit value and not more than a lower limit value. ),... C _n (C _nu , C _nl )) and any one of all the circuits based on the determination result, if the voltage is not less than the predetermined upper limit value and not more than the lower limit value. One alarm signal is output as an abnormal state of the circuit, or all circuits are below the specified upper limit value and lower limit value. If the voltage not a conventional abnormal current monitor circuit that includes a comparator 3 which determines that any of the monitored circuit is also normal one normal signal performs processing as output.
[0006]
The comparison unit 3 receives each output voltage of the DC amplification circuit (A ₁ , A ₂ ,... A _n ) of the DC amplification unit 2 as an input, and a voltage that is greater than or equal to a predetermined upper limit value and less than the lower limit value for that voltage. Are compared (C ₁ (C _1u , C _1l ), C ₂ (C _2u , C _2l ),... C _n (C _nu , C _nl )). The circuit includes a variable resistor for setting a voltage for determining a predetermined upper limit value for each circuit of determination circuits (C _1u , C _2u ,... C _nu ) having a predetermined upper limit value or more. Each of the determination circuits (C _1l , C _2l ,... C _nl ) below the predetermined lower limit value has a variable resistor for setting a voltage for determining the predetermined lower limit value. Therefore, the comparison unit 3 has 2n variable resistors for adjustment, and at least 2n adjustment man-hours are required for the adjustment.
[0007]
[Problems to be solved by the invention]
In FIG. 3, an abnormal voltage such as lightning that is an abnormal voltage induced to the antenna, an excessive input due to an abnormal radio wave, or the occurrence of static electricity due to some cause in a system device or apparatus, is generated inside the LNA formed of a semiconductor circuit such as an FET. The circuit may be destroyed or damaged, and some LNAs may not be able to perform the specified amplification function. At that time, an abnormal alarm (alarm) is promptly issued to minimize system down and system recovery. It is necessary to plan.
Conventionally, this type of circuit has a detection circuit 1 circuit (V ₁ ), a DC amplification circuit 1 circuit (A ₁ ), and a comparison determination circuit 1 pair circuit (C ₁ (C _1u). , C _1l )). For this reason, in the case of a monitoring target circuit having a large number of load circuits (1, 2,... N) as targets to be detected, the detection circuit, the direct current amplifier circuit, and the comparison / determination circuit also have a large number of systems (1, 2,. ..N) Since the circuit portion of n) is required, there is a problem that the number of parts, mounting space, etc. must be provided n times.
Furthermore, even if the same component constant is used due to variations in characteristics of individual components, the output voltage in each monitoring circuit varies, resulting in variation errors in the accuracy of a predetermined value. For this reason, a variable resistor is required so that the voltage of each of the comparison judgment circuits (C ₁ , C ₂ ,... C _n ) of the comparison unit 3 can be set.
In this variable resistor, variation in a predetermined value is adjusted by a pair of circuits of a variable resistor for setting an upper limit value and a variable resistor for setting a lower limit value. Thus, the comparison unit 3 requires two variable resistors for a pair of comparison / determination circuits, and there is a problem that the number of adjustment steps is extremely increased when the number of circuits to be monitored increases.
As shown in FIG. 3, since the example of the tower-top receiving amplifier actually used is four monitored circuits, the number of variable resistors provided in the comparison unit 3 is eight. In this case, the number of parts is large, and the number of adjustment steps per receiving amplifier increases, which is not suitable for the production of mass-produced products.
[0008]
The object of the present invention is to solve the problem of the prior art “increase in the number of components, mounting space, and adjustment man-hours when there are a large number of targets to be monitored in a circuit to be monitored” and reduce the number of components (reducing material costs) ), To provide an abnormal current monitoring circuit capable of achieving the goal of mounting space saving (miniaturization) and adjustment man-hour reduction (processing cost reduction).
[0009]
[Means for Solving the Invention]
An abnormal current monitoring circuit according to the present invention includes a potential difference detection unit that detects a current flowing through a plurality of n loads of a monitoring target circuit as a plurality of n potential difference outputs, and a DC amplification that amplifies each of the plurality of n potential difference outputs. , A highest value detection circuit for detecting the highest value among the plurality of n amplified output voltage values of the DC amplification unit, and a lowest value detection circuit for detecting the lowest value of the plurality of n A peak detection unit having the maximum value voltage obtained from the maximum value detection circuit, an upper limit value determination circuit for determining whether the voltage of the maximum value is equal to or higher than a predetermined upper limit value, and the lowest value obtained from the lowest value detection circuit A lower limit determination circuit that determines whether the voltage of the value is equal to or lower than a predetermined lower limit, and whether the determination result in the upper limit determination circuit is greater than or equal to the upper limit or determination in the lower limit determination circuit If the result is determined to be less than or equal to the lower limit, It monitored circuit and a comparator for outputting an alarm signal as an abnormal state.
[0010]
DETAILED DESCRIPTION OF THE INVENTION
In the embodiment of the present invention, as shown in FIG. 1, n potential difference outputs corresponding to currents flowing in _n loads (M ₁ , M ₂ ,... M _n ) of the monitoring target circuit are respectively provided. (V ₁ , V ₂ ,... V _n ) and a potential difference detection unit 11 that detects the potential difference, and an amplified output voltage obtained by amplifying the _n potential differences (V ₁ , V ₂ ,... V _n ). DC amplification unit 21 having DC amplification circuits (A ₁ , A ₂ ,... A _n ) and the order of n circuits for detecting the maximum value from the n amplification output voltages of DC amplification unit 21 There is a directional diode gate circuit, and there is a maximum value detection circuit whose output side is wired OR, and a reverse diode gate circuit for n circuits for detecting the minimum value from the n amplified output voltages of the DC amplification unit 21, Two detection circuits of the lowest value detection circuit whose output side is wired OR A peak detector 31 having a maximum value detecting circuit output maximum value detected appears in (A point) determination circuit whether a predetermined upper limit value or more of the voltage (C _u) and a minimum value detection circuit output A comparison unit 41 having a pair of determination circuits (C _u , C _l ) of a determination circuit (C _l ) for determining whether the lowest value detected and detected at (B point) is equal to or lower than the lower limit value; I have. It is determined that each determination result of the pair of determination circuits (C _u , C _l ) in the comparison unit 41 is a voltage not less than a predetermined upper limit value in the determination circuit (C _u ) or not more than a lower limit value in the determination circuit (C _l ). If it is, an alarm signal output indicating an abnormal state of the monitored circuit is obtained. When the determination circuit (C _u ) determines that the voltage is not less than the predetermined upper limit value and the determination circuit (C _l ) is other than the lower limit value (upper limit value, lower limit value), the normal state of the monitored circuit is determined. Normal signal output is obtained. These upper limit and lower limit determination outputs are combined by an OR circuit and output as one output. Even if the value of n of the n loads (M ₁ , M ₂ ,... M _n ) of the monitored circuit increases to a large number, the comparison unit 41 can be completed with a pair of determination circuits (C _u , C _l ). It is.
[0011]
The comparison unit 3 of the conventional circuit (FIG. 4) requires 2n variable resistors. In the comparison unit 41 of FIG. 1 of the present invention, a variable resistor is used instead of a fixed resistor. However, each DC amplifier circuit (A ₁ , A ₂ ,... _An ) of the DC amplifier unit 21 is avoided in order to avoid the influence of the determination error of the upper limit value and the lower limit value in the determination circuit due to the dispersion of the component constants as described above. In addition, n variable resistors for adjustment are provided so that the amplification factor is variable and the voltage can be adjusted to a predetermined value corresponding to a voltage error caused by variations in component constants.
[0012]
The following detailed explanation examples show and explain voltage value examples corresponding to each order of circuit operation in FIG.
There is a potential difference detection unit 11 having a fixed resistor in which a potential difference (V ₁ , V ₂ ,... V _n ) is generated between a load side of the circuit and a power supply Vcc side by a predetermined current flowing in the monitored circuit. If the monitored circuit is normal, V _1, V _2, each potential difference · · · V _n is generally a fixed constant resistor such that the same value.
The potential differences (V ₁ , V ₂ ,... V _n ) are each DC amplified, and at this time, in order to make the dispersion of the amplification degree uniform, each DC amplifier circuit (A ₁ , A ₂ ,... A _n ) Connected to the + input side of each DC amplifier circuit (A ₁ , A ₂ ,... A _n ) so that the voltage values at TP1 to TPn (test points) at the output terminal have the same predetermined voltage value. This is a DC amplifying unit 21 that adjusts the variable resistor so that the TP of each circuit has the same predetermined voltage value. That is, if the monitoring target circuit during normal operation of the system is normal, each TP that is the output of each DC amplification unit 21 circuit has the same predetermined voltage value (for example, 5 V).
In the peak detection unit 31, n forward diodes are wired-ORed on the output side to become the maximum value detection circuit output (point A), and this wired-OR circuit is pulled down to GND through a resistor. On the other hand, n reverse diodes are wired-ORed on the output side to become the lowest value detection circuit output (point B), and this wired-ORed circuit is pulled up to Vcc through a resistor. Therefore, the peak detection unit 31 output voltage at each of the peak detection units 31 (A point) and (B point) is 4.5 V at (A point) and 5.5 V at (B point) in the case of normal values. is there. (See Figure 2)
Next, each of the pair of determination circuits (C _u , C _l ) in the comparison unit 41 is connected to the upper limit value determination circuit (C _u ) with (A point) as an input, and the input voltage is a predetermined upper limit value. The upper limit value determination circuit (C _u ) and (B point) that recognizes an alarm if it is equal to or greater than (for example, 6 V) are connected to the lower limit value determination circuit (C _l ) as inputs, and the input voltage is a predetermined lower limit value (for example, 4V) There is a lower limit judgment circuit (C _l ) that recognizes an alarm if it is less than or equal to 4V).
Therefore, in the normal example of the previous monitoring target circuit, the upper limit determination circuit (C _u ) of the comparison unit 41 determines that (A point) voltage 4.5V <predetermined upper limit 6V. Consider it normal. Similarly, in the lower limit determination circuit (C _l ), it is determined that (B point) voltage 5.5V> predetermined lower limit 4V, and this is considered normal. Accordingly, the output of the comparison unit 41 is determined to be a normal state of the monitoring target circuit, and a normal signal output is obtained. The determination outputs of the upper limit value determination circuit and the lower limit value determination circuit are combined by the OR circuit, and the logic level “H” is set. Is output.
[0013]
Next, when an abnormality occurs in any of the loads (M ₁ , M ₂ ,... M _n ) of the monitored circuit, the current flowing through the load of the circuit changes (over and under). As a result, the predetermined potential difference (V ₁ , V ₂ ,... V _n ) and the voltage at each TP exhibit a change voltage value (abnormal value) in a part of the circuit 1 to n with respect to the predetermined value. .
Where a portion (insufficient current to excessive current or load M ₂ to the load M ₁₎ of the monitored circuit is to have been caused as an abnormal operation. As the output voltage example of the direct-current amplifying section 31 this time, it changes the voltage value at TP2 change voltage value at TP1 corresponding to the load M ₁ (abnormal values) corresponding to 7V and load M ₂ (outliers) is at 3V It is assumed that other TP3 to TPn have a predetermined value (normal value) of approximately 5V. In the following, the main voltage relationships that make up the invention will be described. (See FIG. 2).
7V of the change voltage value (abnormal value) at TP1 is one input of the peak detector 31. In the output of the peak detector 31, 6.5V appears at the maximum value detection circuit output (point A). This is input to the upper limit determination circuit (C _u ) of the comparison unit 41. In the upper limit determination circuit (C _u ), the determination situation of (Voltage A) voltage 6.5V ≧ predetermined upper limit 6V is made, so the predetermined upper limit It is determined that the above condition is satisfied and the monitored circuit is abnormal. At this time, 7.5V appears on the lowest value detection circuit output (point B) side, but in the lower limit determination circuit (C _l ), the voltage (V) is 7.5V ≧ predetermined lower limit value 4V, so the lower limit value. The following conditions are not satisfied and do not contribute to alarm determination.
Therefore, the output of the determination result on the upper limit determination circuit side is output as an alarm signal of logic level “L”.
On the other hand, in the example in which the change voltage value (abnormal value) at TP2 is 3V, 3.5V appears at the lowest value detection circuit output (point B) of the peak detection unit 31, and the lower limit determination circuit (C _l ) has (B Point) Since the voltage is 3.5 V ≦ the predetermined lower limit value 4 V, the condition that is equal to or lower than the predetermined lower limit value is satisfied, and it is determined that the monitored circuit is abnormal. At this time, 2.5 V appears at the output of the minimum value detection circuit (point A), but at the upper limit determination circuit (C _u ), voltage (2.5 points) ≧ predetermined upper limit value 6 V, so that the upper limit value is exceeded. This condition is not satisfied and does not contribute to alarm determination. Therefore, the output of the determination result on the lower limit determination circuit side is output as an alarm signal of logic level “L”.
Finally, using the “H” and “L” signals output from the comparison unit 41, the system side uses them for control operations of the CPU, etc., or drives the LEDs for alarm monitoring and control. Is to do.
[0014]
【The invention's effect】
The conventional type has the number of comparison judgment circuits corresponding to the number of circuits for each monitoring target circuit, two variable resistors for setting the upper and lower limits of the range in one pair of comparison judgment circuits, and 2n in the n circuit However, in the present invention using a peak detection circuit, the number of variable resistors for adjustment is 1 as compared with the conventional one by providing one variable resistor for setting in the DC amplifier circuit and n in the n circuit. Therefore, the number of man-hours for adjusting the voltage with the variable resistor can be halved.
Further, when the load on the monitoring target circuit increases by one circuit, the conventional circuit includes a DC amplifier circuit (operational amplifier: 1), a comparison / determination circuit (operational amplifier: 2 units, variable resistor: 2 units, logic IC: 1). In contrast, the present invention uses a peak detection circuit, so a DC amplification circuit (1 operational amplifier, 1 variable resistor), a peak detection circuit (diode) : 2) four parts are required, but the comparison unit does not require the addition of circuit parts, and only a pair of determination circuits (C _u , C _l ) provided first is sufficient. Therefore, the number of parts required every time the number of monitoring targets increases by one circuit may be about ½ that of the conventional circuit.
As described above, the effect of improving the reliability of an apparatus such as a tower-top receiving amplifier attached to an antenna tower or the like due to ease of adjustment and maintenance as well as reduction in manufacturing cost due to circuit simplification is extremely great.
[Brief description of the drawings]
FIG. 1 is a current monitoring circuit diagram using a peak detection unit and a comparison unit according to the present invention.
FIG. 2 is an operation level diagram of a peak detection circuit according to the present invention.
FIG. 3 is a block diagram of a device using a conventional current monitoring circuit.
FIG. 4 is a current monitoring circuit diagram using a conventional comparison unit.
[Explanation of symbols]
1,11 potential difference detection unit 2, 21 DC amplifying section 3, 41 comparing unit 31 peak detector _{M 1, M 2, ··· M} n monitored circuit _{V 1, V 2, ··· V} n potential difference A _1, A ₂ ,... A _n DC amplifier circuits C ₁ , C ₂ ,... C _n comparison / judgment circuits C _u , C _l judgment circuits

Claims (1)

A potential difference detection unit that detects currents flowing through a plurality of n loads of a monitoring target circuit as a plurality of n potential difference outputs; and
A direct current amplifier for amplifying each of the plurality of n potential difference outputs;
A maximum value detecting circuit for detecting a maximum value among the plurality of n pieces from a plurality of n amplified output voltage values of the direct current amplifier; and a minimum value detecting circuit for detecting the lowest value of the plurality of n pieces. A peak detector;
An upper limit determination circuit for determining whether or not the highest voltage obtained from the highest value detection circuit is equal to or higher than a predetermined upper limit value, and the lowest voltage obtained from the lowest value detection circuit is a predetermined lower limit value. It has a lower limit determination circuit for determining whether or not it is less than or equal to, and the determination result in the upper limit determination circuit is determined to be greater than or equal to the upper limit or the determination result in the lower limit determination circuit is determined to be less than or equal to the lower limit And a comparator that outputs an alarm signal indicating that the monitored circuit is in an abnormal state.

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