JP4017371B2 - Active matrix display device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to an active matrix display device, and more particularly to an active matrix display device provided with a plurality of holding circuits corresponding to pixels.
[0002]
[Prior art]
In recent years, portable display devices such as mobile TVs and mobile phones are required as market needs. In response to such demands, research and development has been actively conducted in order to cope with the reduction in size, weight, and power consumption of display devices.
[0003]
FIG. 6 shows a circuit configuration diagram of one pixel electrode of a liquid crystal display (LCD) according to a conventional example. A gate signal line 51 and a drain signal line 61 intersect with each other on an insulating substrate (not shown), and a selection pixel selection TFT 70 connected to both signal lines 51 and 61 is provided in the vicinity of the intersection. It has been. The source 70 s of the selection pixel selection TFT 70 is connected to the pixel electrode 17 of the liquid crystal 21.
[0004]
In addition, an auxiliary capacitor 85 for holding the voltage of the pixel electrode 17 for one field period is provided. One terminal 86 of the auxiliary capacitor 85 is connected to the source 70 s of the selected pixel selection TFT 70, and the other electrode 87. A common potential is applied to each pixel electrode.
[0005]
Here, when a gate signal is applied to the gate signal line 51, the selected pixel selection TFT 70 is turned on, and an analog video signal is transmitted from the drain signal line 61 to the pixel electrode 17 and held in the auxiliary capacitor 85. . The video signal voltage applied to the pixel electrode 17 is applied to the liquid crystal 21, and the liquid crystal 21 is aligned according to the voltage. An LCD can be obtained by arranging such pixel electrodes in a matrix.
[0006]
A conventional LCD can obtain a display regardless of a moving image or a still image. When a still image is displayed on such an LCD, for example, an image of a dry cell is displayed as a battery remaining amount display for driving the mobile phone on a part of a liquid crystal display unit of the mobile phone.
[0007]
However, in the liquid crystal display device having the above-described configuration, even when a still image is displayed, the selection pixel selection TFT 70 is turned on by a gate signal and a video signal is transmitted to each video signal as in the case of displaying a moving image. It has been necessary to rewrite the pixel electrode.
[0008]
Therefore, a driver circuit for generating a drive signal such as a gate signal and a video signal and an external LSI for generating various signals for controlling the operation timing of the driver circuit always operate, and thus always consume a large amount of power. It was. For this reason, a mobile phone or the like having only a limited power source has a drawback that the usable time is shortened.
[0009]
On the other hand, a liquid crystal display device having a static memory in each pixel electrode is disclosed in Japanese Patent Laid-Open No. 8-194205. A part of the publication will be described by citing. FIG. 7 is a plan circuit diagram of an active matrix display device with a holding circuit disclosed in Japanese Patent Laid-Open No. 8-194205. A plurality of gate signal lines 51 and reference lines 52 are arranged in the row direction, and a plurality of drain signal lines 61 are arranged in the column direction. A TFT 53 is provided between the holding circuit 54 and the pixel electrode 17. By performing display based on the data held in the holding circuit 54, the gate driver 50 and the drain driver 60 are stopped to reduce power consumption.
[0010]
FIG. 8 is a circuit configuration diagram showing one pixel of the liquid crystal display device. Pixel electrodes are arranged in a matrix on the substrate. Between the pixel electrodes 17, gate signal lines 51 are arranged in the left-right direction on the paper surface, and drain signal lines 61 are arranged in the up-down direction. A reference line 52 is arranged in parallel with the gate signal line 51, a holding circuit 54 is provided at the intersection of the gate signal line 51 and the drain signal line 61, and a switch element 53 is provided between the holding circuit 54 and the pixel electrode 17. It has been. The holding circuit 54 uses a memory in which the two-stage inverters 55 and 56 are positively fed back, that is, a static memory (Static Random Access Memory; SRAM), as a digital video signal holding circuit. In particular, SRAM is preferable because it does not require refresh for data retention, unlike DRAM.
[0011]
Here, in accordance with the binary digital signal held in the static memory, the switch element 53 controls the resistance value between the reference line Vref and the pixel electrode 17 according to the output of the holding circuit 54, and the liquid crystal 21. The bias state is adjusted. On the other hand, an AC signal Vcom is input to the common electrode. Ideally, this apparatus does not require a refresh to the memory if there is no change in the display image as in a still image.
[0012]
[Problems to be solved by the invention]
However, when a static RAM is used for the holding circuit 54, the number of transistors constituting the holding circuit is as large as four or six, and the circuit area is large. When such a static RAM is arranged between the pixel electrodes 17, the area of the pixel electrode 17 is reduced and the aperture ratio of the liquid crystal display device is reduced, or one pixel size must be increased to increase the definition. There was a problem that was difficult.
[0013]
In view of the above, an object of the present invention is to provide a display device having a holding circuit with higher definition or higher aperture ratio.
[0014]
[Means for Solving the Problems]
The present invention has been made to solve the above problems, and supplies a predetermined voltage to a plurality of pixel electrodes arranged in a matrix, a plurality of holding circuits arranged corresponding to the pixel electrodes, and a holding circuit. In an active matrix display device in which a voltage corresponding to data held by a holding circuit is supplied to a pixel electrode for display, the power supply line extends in one direction of the matrix and extends in one direction. This is an active matrix display device that is shared by the holding circuits corresponding to the pixel electrodes arranged side by side and shared by the holding circuits corresponding to the pixel electrodes adjacent in the other direction of any one of the matrices.
[0015]
According to such a configuration, in the active matrix display device having a holding circuit, the number of power supply lines can be reduced by half compared to arranging the power supply line for each row, and the pixel size can be reduced. A higher definition active matrix display device can be obtained.
[0016]
The pixel electrodes are arranged in a matrix, the plurality of gate signal lines are arranged in the row direction, and the plurality of drain signal lines are arranged in the column direction. In an active matrix display device that is selected by a scanning signal and is supplied with a video signal from a drain signal line, the pixel electrode selected by the scanning signal input from the gate signal line corresponds to the video signal from the drain signal line. A first display circuit that supplies a signal, and a holding circuit that is supplied with a predetermined voltage and holds a video signal from the drain signal line in accordance with a signal input from the gate signal line. A second display circuit for supplying a signal corresponding to the display electrode to the display electrode, and a circuit selection for selectively connecting the first and second display circuits to the drain signal line according to the circuit selection signal. And a power supply line that supplies a predetermined voltage to the holding circuit extends in one direction of the matrix and is shared by the holding circuit corresponding to the pixel electrodes arranged in one direction and adjacent to the other direction of the matrix This is an active matrix display device shared by a plurality of pixels.
[0017]
According to such a configuration, in the active matrix display device capable of selecting either the first or second display circuit, the number of power supply lines can be reduced to half compared to the case where the power supply lines are arranged for each row. Since the pixel size can be reduced, a higher definition active matrix display device can be obtained.
[0018]
The preferred embodiment is as follows. That is, each holding circuit is connected to at least two drive power supply lines that extend in one direction of the matrix and supply different drive voltages, and at least one of the drive power supply lines includes a plurality of adjacent ones in the other direction of the matrix. Shared by pixel.
[0019]
Further, each holding circuit is connected to at least two reference power supply lines that extend in one matrix direction and supply different reference voltages. The holding circuit selects a reference voltage according to the held data, and At least one of the reference power supply lines supplied to the electrodes is shared by a plurality of pixels adjacent in the other direction of the matrix.
[0020]
Furthermore, the shared power supply line supplies the same voltage to all the holding circuits. Further, the shared power supply line is disposed between pixels adjacent in the other direction of the matrix, and the holding circuit in the pixels adjacent in the other direction of the matrix is arranged between the pixels adjacent in the other direction of the matrix by an axis or center. Are arranged symmetrically across the power line shared by the two.
[0021]
DETAILED DESCRIPTION OF THE INVENTION
Next, a display device according to an embodiment of the present invention will be described. FIG. 1 shows a circuit configuration diagram when the display device of the present invention is applied to a liquid crystal display device.
[0022]
In the liquid crystal display panel 100, a plurality of pixel electrodes 17 are arranged in a matrix on the insulating substrate 10. A plurality of gate signal lines 51 connected to a gate driver 50 for supplying a gate signal are arranged in one direction, and a plurality of drain signal lines 61 are arranged in a direction intersecting with the gate signal lines 51. Yes.
[0023]
Sampling transistors SP1, SP2,..., SPn are turned on to the drain signal line 61 in accordance with the timing of the sampling pulse output from the drain driver 60, and the data signal (analog video signal or digital video signal) of the data signal line 62 is turned on. ) Is supplied.
[0024]
The gate driver 50 selects a certain gate signal line 51 and supplies a gate signal thereto. A data signal is supplied from the drain signal line 61 to the pixel electrode 17 in the selected row.
[0025]
Hereinafter, a detailed configuration of each pixel will be described. In the vicinity of the intersection of the gate signal line 51 and the drain signal line 61, a circuit selection circuit 40 including a P-channel circuit selection TFT 41 and an N-channel circuit selection TFT 42 is provided. Both drains of the circuit selection TFTs 41 and 42 are connected to the drain signal line 61 and both gates thereof are connected to the circuit selection signal line 88. One of the circuit selection TFTs 41 and 42 is turned on in response to a selection signal from the selection signal line 88. Further, as will be described later, a circuit selection circuit 43 is provided in a pair with the circuit selection circuit 40. In the circuit selection circuits 40 and 43, the respective transistors only need to operate in a complementary manner, and the P channel and the N channel may be reversed. Further, only one of the circuit selection circuits 40 and 43 can be omitted.
[0026]
As a result, it is possible to select and switch between an analog video signal display (corresponding to a full-color moving image), which is a normal operation mode, which will be described later, and a digital video display (corresponding to low power consumption, still image), which is a memory operation mode. In addition, a pixel selection circuit 70 including an N-channel pixel selection TFT 71 and an N-channel TFT 72 is disposed adjacent to the circuit selection circuit 40. The pixel selection TFTs 71 and 72 are connected in series with the circuit selection TFTs 41 and 42 of the circuit selection circuit 40, respectively, and a gate signal line 51 is connected to their gates. The pixel selection TFTs 71 and 72 are configured so that both are turned on simultaneously in response to a gate signal from the gate signal line 51.
[0027]
In addition, an auxiliary capacitor 85 for holding an analog video signal is provided. One electrode of the auxiliary capacitor 85 is connected to the source of the pixel selection TFT 71. The other electrode is connected to a common auxiliary capacitance line 87 and supplied with a bias voltage Vsc. The source of the pixel selection TFT 71 is connected to the pixel electrode 17 via the circuit selection TFT 44 and the contact 16. When the gate of the pixel selection TFT 70 is opened by the gate signal, the analog video signal supplied from the drain signal line 61 is input to the pixel electrode 17 through the contact 16 to drive the liquid crystal as the pixel voltage. The pixel voltage must be held for one field period until the pixel selection TFT 71 is deselected and then selected again. However, with only the capacity of the liquid crystal, the pixel voltage gradually decreases with time, and one field is required. Not enough hold for a period. Then, the drop in the pixel voltage appears as display unevenness and a good display cannot be obtained. Therefore, an auxiliary capacitor 85 is provided to hold the pixel voltage for one field period.
[0028]
A P-channel TFT 44 of the circuit selection circuit 43 is provided between the auxiliary capacitor 85 and the pixel electrode 17 and is configured to be turned on / off simultaneously with the circuit selection TFT 41 of the circuit selection circuit 40. An operation mode in which the circuit selection TFT 41 is turned on and an analog signal is supplied as needed to drive the liquid crystal is called a normal operation mode or an analog operation mode.
[0029]
A holding circuit 110 is provided between the TFT 72 of the pixel selection circuit 70 and the pixel electrode 17. The holding circuit 110 includes two inverter circuits positively fed back and a signal selection circuit 120, and constitutes a static memory that holds a digital binary value.
[0030]
The signal selection circuit 120 is a circuit that selects a signal in accordance with signals from two inverters, and includes two N-channel TFTs 121 and 122. Since complementary output signals from the two inverters are applied to the gates of the TFTs 121 and 122, the TFTs 121 and 122 are complementarily turned on and off.
[0031]
Here, when the TFT 122 is turned on, an AC drive signal (signal B) is selected, and when the TFT 121 is turned on, an AC drive signal (signal A) equal to the counter electrode signal VCOM is selected, and the liquid crystal is supplied via the TFT 45 of the selection circuit 43. Supplied to 21 pixel electrodes 17. The operation mode in which the circuit selection TFT 42 is turned on and the display is performed based on the data held in the holding circuit 110 is called a memory mode or a digital operation mode.
[0032]
To summarize the above-described configuration, a circuit (analog display circuit) including a pixel selection TFT 71 as a pixel selection element and an auxiliary capacitor 85 for holding an analog video signal, a TFT 72 as a pixel selection element, and a binary digital video signal. A circuit (digital display circuit) composed of a holding circuit 110 for holding is provided in one pixel electrode, and circuit selection circuits 40 and 43 for selecting these two circuits are provided.
[0033]
Next, peripheral circuits of the liquid crystal panel 100 will be described. A panel driving LSI 91 is provided on an external circuit board 90 which is a separate substrate from the insulating substrate 10 of the liquid crystal panel 100. A vertical start signal STV is input to the gate driver 50 from the panel driving LSI 91 of the external circuit board 90, and a horizontal start signal STH is input to the drain driver 60. A video signal is input to the data line 62.
[0034]
Next, a method for driving the display device having the above-described configuration will be described.
(1) In the normal operation mode (analog operation mode) When the analog display mode is selected according to the mode signal, the LSI 91 is set to supply an analog signal to the data signal line 62, and the circuit selection signal The potential of the line 88 becomes “L”, the circuit selection TFTs 41 and 43 of the circuit selection circuits 40 and 43 are turned on, and the circuit selection TFTs 42 and 45 are turned off.
[0035]
Further, the sampling transistors SP are sequentially turned on in accordance with the sampling signal based on the horizontal start signal STH, and the analog video signal of the data signal line 62 is supplied to the drain signal line 61.
[0036]
A gate signal is supplied to the gate signal line 51 based on the vertical start signal STV. When the pixel selection TFT 71 is turned on according to the gate signal, the analog video signal An. Sig is transmitted to the pixel electrode 17 and held in the auxiliary capacitor 85. A video signal voltage applied to the pixel electrode 17 is applied to the liquid crystal 21, and the liquid crystal 21 is aligned according to the voltage, whereby a liquid crystal display can be obtained.
[0037]
In this analog display mode, the liquid crystal is driven at any time according to an analog signal input at any time, which is suitable for displaying a full-color moving image. However, the LSI 91 and the drivers 50 and 60 of the external circuit board 90 are constantly consuming power to drive them.
(2) In the case of the memory operation mode (digital display mode) When the digital display mode is selected in accordance with the mode signal, the LSI 91 digitally converts the video signal and extracts the upper one bit as the data signal line 62. And the potential of the circuit selection signal line 88 becomes “H”. Then, the circuit selection TFTs 41 and 44 of the circuit selection circuits 40 and 43 are turned off and the circuit selection TFTs 42 and 45 are turned on, so that the holding circuit 110 is in an effective state.
[0038]
A start signal STH is input from the panel driving LSI 91 of the external circuit board 90 to the gate driver 50 and the drain driver 60. In response to this, sampling signals are sequentially generated, and the sampling transistors SP1, SP2,..., SPn are sequentially turned on in accordance with the respective sampling signals, and the digital video signal D.D. Sig is sampled and supplied to each drain signal line 61.
[0039]
Here, the first row, that is, the gate signal line 51 to which the gate signal G1 is applied will be described. First, each pixel selection TFT 72 of each pixel electrode connected to the gate signal line 51 by the gate signal G1 is turned on for one horizontal scanning period. When attention is paid to the pixel electrode in the first row and the first column, the digital video signal S11 sampled by the sampling signal SP1 is inputted to the drain signal line 61. When the selected pixel selection TFT 72 is turned on by the gate signal, the digital signal D.D. Sig is input to the holding circuit 110 and held by two inverters.
[0040]
The signal held by the inverter is input to the signal selection circuit 120, the signal selection circuit 120 selects the signal A or the signal B, the selected signal is applied to the pixel electrode 17, and the voltage is applied to the liquid crystal. 21 is applied.
[0041]
By scanning from the gate signal line of the first row to the gate signal line of the last row in this way, scanning for one screen (one field period), that is, all dot scanning is completed, and one screen is displayed.
[0042]
Here, when one screen is displayed, voltage supply to the gate driver 50, the drain driver 60, and the external panel driving LSI 91 is stopped to stop driving them. The holding circuit 110 is always driven by supplying the drive voltages VDD and VSS, the counter electrode voltage is supplied to the counter electrode 32, and the signals A and B are supplied to the selection circuit 120.
[0043]
That is, the drive voltages VDD and VSS for driving the holding circuit are supplied to the holding circuit 110, the counter electrode voltage VCOM is applied to the counter electrode, and the liquid crystal display panel 100 is normally white (NW). The signal A is applied with an AC drive voltage having the same potential as the counter electrode voltage, and the signal B is simply applied with an AC voltage (for example, 60 Hz) for driving the liquid crystal. By doing so, one screen can be held and displayed as a still image. In addition, no voltage is applied to the other gate driver 50, drain driver 60, and external LSI 91.
[0044]
At this time, when “H (high)” is input to the drain signal line 61 as a digital video signal to the holding circuit 110, “L” is input to the first TFT 121 in the signal selection circuit 120. Therefore, the first TFT 121 is turned off, and “H” is input to the other second TFT 122, so that the second TFT 122 is turned on. Then, the signal B is selected and the voltage of the signal B is applied to the liquid crystal. That is, since the alternating voltage of signal B is applied and the liquid crystal rises due to the electric field, the display can be observed as a black display on the NW display panel.
[0045]
When “L” is input to the drain signal line 61 as a digital video signal to the holding circuit 110, “H” is input to the first TFT 121 in the signal selection circuit 120. Is turned on, and “L” is input to the other second TFT 122, so that the second TFT 122 is turned off. Then, the signal A is selected and the voltage of the signal A is applied to the liquid crystal. That is, since the same voltage as that of the counter electrode 32 is applied, no electric field is generated and the liquid crystal does not stand up, so that the display can be observed as white display on the NW display panel.
[0046]
In this way, it is possible to display a still image by writing one screen and holding it, but in this case, since the driving of the drivers 50 and 60 and the LSI 91 is stopped, the power consumption can be reduced accordingly. it can.
[0047]
In the above embodiment, the holding circuit 110 holds only 1 bit, but of course, if the holding circuit 110 is multi-bit, gradation display can be performed in the memory operation mode, and the holding circuit 110 stores an analog value. If this memory is used, full-color display can be performed in the memory operation mode.
[0048]
As described above, according to the embodiment of the present invention, a full-color moving image display (in the case of the analog display mode) and a low power consumption digital gradation display (in the case of the digital display mode) are performed on the single liquid crystal display panel 100. It is possible to correspond to the two types of displays.
[0049]
Next, the layout of this embodiment will be described with reference to FIG. FIG. 2 is a conceptual diagram showing the layout of this embodiment. A P-channel circuit selection TFT 41 of the circuit selection circuit, an N-channel pixel selection TFT 71 of the pixel selection circuit, and a P-channel TFT 44 of the circuit selection circuit are connected in series, connected to the pixel electrode 17 via the contact 16 and an auxiliary capacitor 85. It is connected to the. Further, the N channel circuit selection TFT 42, the N channel pixel selection TFT 72, the holding circuit 110, and the N channel TFT 45 of the circuit selection circuit are connected to the pixel electrode 17 through the contact 16. All of the above configurations are arranged so as to overlap the pixel electrode 17.
[0050]
The circuit configuration arranged in each pixel is substantially the same in each pixel, but the circuit arrangement between adjacent pixels in the column direction is substantially line-symmetric with respect to each other as an axis. That is, in the pixel in the first column in the drawing, the gate signal line 51 is disposed at the upper end of the pixel, and the holding circuit 110 is disposed in the lower half of the pixel. In the pixel in the second column of the drawing, the gate signal line 51 is disposed at the lower end of the pixel, and the holding circuit 110 is disposed in the upper half of the pixel. Similarly, the pixel in the third column (not shown) has the same arrangement as the pixel in the first column in which the gate signal line 51 is arranged at the upper end and the holding circuit 110 is arranged in the lower half.
[0051]
The holding circuit 110 is an SRAM as described above. The holding circuit 110 is connected to a total of four power supply lines, two kinds of high and low drive power supply lines (LVDD, LVSS) and two kinds of reference power supply lines (signal A, signal B). These power supply lines extend in the row direction, and are shared by each pixel in the row, like the gate signal line 51 and the auxiliary capacitance line 87. The above is common in the circuit arrangement of each pixel. In the present embodiment, the circuit layout of each pixel is different. The circuit layout of each pixel is laid out in line symmetry with pixels adjacent in the column direction. The holding circuits 110 of the pixels adjacent in the column direction are arranged close to each other across the four power supply lines, and the four power supply lines are common to both the holding circuits 110. That is, each power supply line is arranged at a ratio of one to two rows of pixels, and is connected to all the holding circuits corresponding to the two rows of pixels. Therefore, the power supply lines extending in the row direction can be reduced by half compared to the case where the power supply lines are arranged for each row. Since an active matrix display device having the holding circuit 110 has many circuits installed for each pixel, reducing the components of the circuit directly leads to a reduction in pixel area. Accordingly, a display device with a holding circuit can be made high definition.
[0052]
For example, since the gate signal lines 51 need to be turned on at different timings in each row, they cannot be shared across different rows. On the other hand, the four power supply lines shared in the present embodiment are lines for supplying the driving voltage and the reference voltage of the holding circuit 110, and the selection and non-selection of the pixel and the display contents of the pixel (white Regardless of (black), the voltage applied in common to the holding circuits 110 of all the pixels is continuously supplied. Therefore, it can be shared across a plurality of rows. For the same reason, even if the active matrix display device is a type that performs color display, the power supply line can be shared by adjacent pixels. That is, the present invention can be implemented in exactly the same manner not only in a stripe arrangement in which the same color is arranged in the column direction but also in a delta arrangement in which RGB are alternately arranged.
[0053]
Next, the layout relationship between the four power lines and the pixel electrode 17 will be described. FIG. 3 is a layout conceptual diagram showing a boundary portion between pixels GS1 and GS2 adjacent in the column direction in FIG. As shown in the figure, the power line 19 shared by the two pixels GS1 and GS2 (in the figure, the power line LVDD supplied to the SRAM of the holding circuit 110) extends over one pixel, for example, the pixel GS2. In addition, it branches from the middle in the direction of the pixels GS1 and GS2, and is contacted via the contacts 18 and 18 to the sources 110S and 110S of the thin film transistors (TFT) constituting the respective SRAMs.
[0054]
In such a layout, a parasitic capacitance is formed between the pixel electrode 17 of the pixel GS2 and the power supply line 19 via an insulating film. Since the parasitic capacitance is much larger than the parasitic capacitance formed between the pixel electrode 17 and the power supply line 19 of the pixel GS1, the influence of the parasitic capacitance on the pixel electrodes 17 and 17 becomes unbalanced. For this reason, the influence of the parasitic capacitance occurs every other pixel, and appears as horizontal stripes or vertical stripes on the screen, and the display quality deteriorates.
[0055]
In view of this, in the pixel GS1 on the side where the power supply line 19 does not overlap with the pixel electrode 17, by providing the overlapping region 20 formed by extending the branched power supply line 19 on the pixel electrode 17, the pixel electrode 17 and the power supply line 19 are connected to each other. The parasitic capacitance between them is increased to balance the parasitic capacitance of the adjacent pixel GS2, and the influence of the parasitic capacitance is eliminated. Here, by providing the extended overlapping region 20 of the power supply line 19, the parasitic capacitance value formed between the pixel electrode 17 and the power supply line 19 can be made equal to the adjacent pixels GS1 and GS2. preferable.
[0056]
Note that the power supply line 19 is not limited to the drive power supply line (LVDD) on the high voltage side of the holding circuit 110, but the reference power supply line (signal A, signal B) and the drive power supply line (LVSS) on the low voltage side of the holding circuit 110. Any of the reference power supply lines for transmitting the signal B may be used.
[0057]
In the layout described above, the power supply line 19 is directly capacitively coupled by being superimposed on the pixel electrode 17, but it is not always necessary to be superimposed on the pixel electrode 17. For example, as in the case where the source of the TFT and the pixel electrode 17 are connected via an intermediate electrode layer, the power supply line 19 is indirectly capacitively coupled to the pixel electrode 17 via the intermediate electrode layer. May be. Therefore, the overlapping region 20 formed by extending the power supply line 19 on the pixel electrode 17 is not necessarily overlapped on the pixel electrode 17 but is overlapped on the intermediate electrode layer as described above. If it is, the same effect is produced.
[0058]
By the way, the LCD of this embodiment is a reflective LCD. FIG. 4 shows a cross-sectional view of the reflective LCD of the present embodiment taken along the line AA ′ in FIG. On one insulating substrate 10, a semiconductor layer 11 made of polycrystalline silicon is disposed, and a gate insulating film 12 is disposed thereon. A gate electrode 13 is disposed above the semiconductor layer 11 and on the gate insulating film 12, and a source and drain are formed in the lower semiconductor layer 11 located on both sides of the gate electrode 13. On the gate electrode 13 and the gate insulating film 12, an interlayer insulating film 14 is formed so as to cover them. A contact is formed at a position corresponding to the drain and the source. The drain is connected to the pixel selection TFT 71 via the contact, and the source is connected to the pixel electrode 17 via the contact 16. Each pixel electrode 17 formed on the planarization insulating film 15 is made of a reflective material such as aluminum (Al). An alignment film 20 made of polyimide or the like for aligning the liquid crystal 21 is formed on each pixel electrode 17 and the planarization insulating film 15.
[0059]
On the other insulating substrate 30, a color filter 31 exhibiting each color of red (R), green (G), and blue (B), a counter electrode 32 made of a transparent conductive film such as ITO (Indium Tin Oxide), And the alignment film 33 which orientates the liquid crystal 21 is formed in order. Of course, the color filter 31 is not necessary when color display is not used.
[0060]
The periphery of the pair of insulating substrates 10 and 30 formed in this way is bonded with an adhesive sealing material, and the liquid crystal 21 is filled in the gap formed thereby.
[0061]
In the reflective LCD, as indicated by a dotted arrow in the figure, external light incident from the insulating substrate 30 side is reflected by the pixel electrode 17 and emitted to the viewer 1 side, so that the display can be observed.
[0062]
Since the reflective LCD does not transmit light through the pixel electrode 17, no matter what elements are arranged under the pixel electrode 17, the aperture ratio is not affected. By disposing the holding circuit 110 that requires a large area under the pixel electrode 17, the pixel interval can be made equal to that of a normal LCD. Further, it is not necessary to dispose all the components below the pixel electrodes as in the present embodiment, and some of the components may be disposed between the pixel electrodes.
[0063]
Next, a second embodiment of the present invention will be described with reference to the drawings. FIG. 5 is a conceptual diagram showing a planar layout of the present embodiment. The present embodiment is a stripe arrangement in which pixels of each RGB color are arranged and arranged, and each of the pixel electrodes 17 is arranged corresponding to any one of RGB color filters. Shown as 17B. Each pixel of RGB has a circuit similar to that in FIG. 2, and the data of the pixel can be held in the holding circuit 110 in each pixel.
[0064]
The characteristic point of this embodiment is that the layout of the pixel electrode 17 and the circuit layout of the holding circuit, the selection circuit, the auxiliary capacitor, and the like do not match. This point will be described in more detail below. First, attention is focused on the pixel electrode 17R. The pixel electrode 17R is disposed at the left end of the drawing and has a rectangular shape that is long in the vertical direction. A contact connecting the pixel electrode 17R and its circuit is indicated by 16R. The circuit selection TFTs 41R and 44R and the pixel selection TFT 71R are connected in series, and a part thereof extends to the pixel electrode 17G which is an adjacent pixel. Similarly, the auxiliary capacitor 85R and the holding circuit 110R extend to the pixel electrode 17G. The pixel electrode 17G is connected to a corresponding circuit through a contact 16G, and the circuit selection TFT 41G, the pixel selection TFT 71G, the auxiliary capacitor 85G, and the holding circuit 110G are arranged so as to overlap with the pixel electrode 17R that is an adjacent pixel. Has been.
[0065]
The circuits corresponding to the pixel electrodes 17R and 17G share the gate signal line 51 and are arranged point-symmetrically with respect to one point on the gate signal line. Hereinafter, similarly, a circuit corresponding to the pixel electrode 17B further extends to a pixel electrode (not shown) adjacent thereto. If this pixel is the pixel electrode 17R ′, the circuit corresponding to the pixel electrode 17R ′ is superimposed on the pixel electrode 17B.
[0066]
The merits of such an arrangement will be described below. For example, if three pixels of RGB are used as one picture element, and this picture element is used in a substantially square shape, each pixel of RGB is a 3: 1 vertical rectangle. In general, each pixel of RGB in a stripe arrangement is a rectangle that is long in one direction. If the holding circuit 110 or the like is arranged under such an elongated rectangular pixel electrode 17 in accordance with the layout, circuit design becomes difficult. On the other hand, according to the present invention, the layout of the pixel electrode 17 and the circuit layout are different, so that unnecessary bypassing of wiring and the like is unnecessary, space efficiency is increased, and the area required for the holding circuit is reduced. Can do. In the case of an LCD with a holding circuit, the area occupied by the holding circuit is dominant in the minimum area of one pixel. Therefore, it can be said that reducing the holding circuit directly leads to higher definition of the LCD.
[0067]
Next, the merit of arranging the circuits symmetrically across the gate signal line will be described below. When sharing the area between adjacent pixels, it is necessary to adjust the layout in the circuit for each pixel. However, if the pixels are arranged symmetrically between adjacent pixels, a circuit for one pixel is designed and the circuit is mirrored. The circuit design is efficient. However, it is necessary to adjust the connection to the four power supply lines shown at the upper and lower ends of the pixel in the drawing. Further, if the circuit layout is not point-symmetric but moved in parallel, the gate signal lines of adjacent pixels need to be arranged apart from each other, and two gate signal lines need to be arranged in each row. On the other hand, in the present embodiment, since the circuits are arranged symmetrically, the gate signal line may be one in each row, and there is no need to increase it.
[0068]
Also in this embodiment, as in the first embodiment, the holding circuits 110 are arranged at the upper and lower ends of the pixels, and the holding circuits 110 between the pixels adjacent in the column direction are connected to the power supply lines (VDD, VSS, signal A, The signals B) are arranged close to each other and share these four power supply lines. Therefore, as in the first embodiment, the number of power supply lines can be reduced to half compared to the case where the power supply lines are arranged for each row.
[0069]
In the first and second embodiments, four power supply lines are shared by adjacent pixels, but it is not always necessary to share all the power supply lines. When four power supply lines are arranged adjacent to each other in the immediate vicinity, all the wirings branched in the column direction from each power supply line to connect to the holding circuit 110 intersect with the other three power supply lines. Therefore, parasitic capacitance is generated. In addition, it may be assumed that the layout efficiency is better overall if one of the power supply lines is arranged, for example, between the layout holding circuit 110 and the auxiliary capacitor 85 of the present embodiment. In such a case, any power supply line among the four power supply lines may be shared.
[0070]
In the first and second embodiments, as a result of sharing the power supply line, the circuit arrangement is not completely line-symmetrical or point-symmetrical. Therefore, the parasitic capacitance formed by each power supply line and the pixel electrode 17 is reduced. There may be differences between pixels. As a result, the signal delay differs between pixels, and the display quality may deteriorate. Therefore, in order to make this parasitic capacitance uniform, if the number of shared power lines is 2n (n is a natural number), n lines are stacked on each pixel, and if the number of shared power lines is 2n + 1, It is sufficient that n pixels are overlapped with each other and one power supply line is disposed between the pixels.
[0071]
In the first and second embodiments described above, the four power supply lines (VDD, VSS, signal A, signal B) are described as extending in the row direction and shared by adjacent pixels in the column direction. As shown in the circuit diagram of FIG. 1, it may be arranged extending in the column direction. In this case, the circuit arrangement of each pixel is made line symmetric with respect to the column as an axis, and the power supply line is shared, and the same effects as those of the first and second embodiments can be achieved. However, particularly in the case of the stripe arrangement as in the second embodiment, there is little layout margin for extending the wiring in the column direction. Therefore, the power supply line should be laid out so as to extend in the row direction.
[0072]
In the above embodiment, the description has been made using the reflective LCD. However, the present invention can be applied to a transmissive LCD, and a transparent pixel electrode and a holding circuit can be superposed. However, in the transmissive LCD, the area where the metal wiring is disposed is shielded from light, so that the aperture ratio is inevitably lowered. In addition, when a holding circuit is disposed under a pixel electrode in a transmissive LCD, the transistors of the holding circuit and the selection circuit may malfunction due to transmitted light. Therefore, it is necessary to provide a light-shielding film on the gates of all transistors. . Therefore, it is difficult to increase the aperture ratio in a transmissive LCD.
[0073]
On the other hand, the reflective LCD does not affect the aperture ratio no matter what circuit is arranged under the pixel electrode. Further, unlike the transmissive liquid crystal display device, it is not necessary to use a so-called backlight on the side opposite to the viewer side, so that no power is required to turn on the backlight. Since the original purpose of the LCD with a holding circuit is to reduce power consumption, the display device of the present invention is preferably a reflective LCD that does not require a backlight and is suitable for low power consumption.
[0074]
Moreover, although the said embodiment demonstrated using the liquid crystal display device, this invention is not restricted to this and can be applied to various display apparatuses, such as an organic EL display apparatus and an LED display apparatus.
[0075]
【The invention's effect】
As described above, according to the active matrix display device of the present invention, in the active matrix display device having the holding circuit corresponding to the pixel electrode, the power supply line connected to the holding circuit extends in the row direction, for example. In addition to being shared by the holding circuits corresponding to the pixel electrodes arranged in the row direction and shared by the holding circuits corresponding to the pixel electrodes adjacent in the column direction, as compared with the arrangement of the power supply line for each row. Since the number of power supply lines can be reduced to half and the pixel size can be reduced, an active matrix display device with a higher-definition holding circuit can be provided.
[0076]
In particular, since the shared power supply line supplies the same voltage to all the holding circuits, it can be shared in the row direction and the column direction.
[0077]
In particular, the shared power supply line is arranged in the vicinity between pixels adjacent in the other direction of the matrix, and the arrangement of the holding circuits in the pixels adjacent in the other direction of the matrix is an axis or center between the pixels adjacent in the other direction of the matrix. Since the shared power supply lines are arranged symmetrically, the wiring connecting from the shared power supply line to the holding circuit can be shortened, thereby improving the layout efficiency.
[Brief description of the drawings]
FIG. 1 is a circuit diagram showing a first embodiment of the present invention.
FIG. 2 is a conceptual diagram showing a planar layout of the first embodiment of the present invention.
FIG. 3 is a conceptual diagram showing a planar layout of the first embodiment of the present invention.
FIG. 4 is a cross-sectional view of an embodiment of the present invention.
FIG. 5 is a conceptual diagram showing a planar layout of a second embodiment of the present invention.
FIG. 6 is a circuit diagram illustrating one pixel of a liquid crystal display device.
FIG. 7 is a circuit diagram showing a conventional display device with a holding circuit.
FIG. 8 is a circuit diagram showing one pixel of a conventional liquid crystal display device with a holding circuit.
[Explanation of symbols]
17 Pixel electrodes 40 and 43 Circuit selection circuit 70 Pixel selection circuit 85 Auxiliary capacitor 110 Holding circuit

Claims (5)

A plurality of pixel electrodes arranged in a matrix, a plurality of holding circuits arranged corresponding to the pixel electrodes, and at least two power supply lines for supplying a predetermined voltage to the holding circuit, the holding circuit holding In an active matrix display device that performs display by supplying a voltage corresponding to data to be supplied to the pixel electrode, the holding circuit is a static memory having two inverters that are positively fed back, and the power line is The matrix extends in any one direction and is shared by the holding circuits corresponding to the pixel electrodes arranged in the one direction, and is shared by the holding circuits corresponding to the pixel electrodes adjacent in any other direction of the matrix ,
One of the shared power lines is arranged to overlap a plurality of pixels arranged in one matrix direction,
2. The active matrix display device according to claim 1, wherein the other of the shared power supply lines is arranged so as to overlap with a plurality of adjacent pixels in the other direction of the matrix. A pixel electrode arranged in a matrix; a plurality of gate signal lines arranged in a row direction; and a plurality of drain signal lines arranged in a column direction. In an active matrix display device selected by a scanning signal and supplied with a video signal from the drain signal line,
A first display circuit for supplying a signal corresponding to a video signal from the drain signal line to a pixel electrode selected by a scanning signal input from the gate signal line;
A holding circuit comprising a static memory having two inverters that are fed back to each other and hold a video signal from the drain signal line in response to a scanning signal that is supplied with a predetermined voltage and that is input from the gate signal line; A second display circuit for supplying a signal corresponding to the signal from the holding circuit to the display electrode;
A circuit selection circuit for selectively connecting the first and second display circuits to the drain signal line in response to a circuit selection signal;
At least two power supply lines for supplying a predetermined voltage to the holding circuit extend in one direction of any one of the matrixes, and are shared by the holding circuits corresponding to the pixel electrodes arranged in the one direction. Shared by multiple pixels adjacent in the other direction ,
One of the shared power lines is arranged to overlap a plurality of pixels arranged in one matrix direction,
2. The active matrix display device according to claim 1, wherein the other of the shared power supply lines is arranged so as to overlap with a plurality of adjacent pixels in the other direction of the matrix. A plurality of pixel electrodes arranged in a matrix, a plurality of holding circuits arranged corresponding to the pixel electrodes, a power supply line for supplying a predetermined voltage to the holding circuit, and according to data held by the holding circuit In the active matrix display device in which the voltage is supplied to the pixel electrode for display, the power supply line extends in one direction of the matrix and is shared by the holding circuit corresponding to the pixel electrode arranged in the one direction. In addition, each of the holding circuits is shared by holding circuits corresponding to pixel electrodes adjacent to each other in any direction of the matrix, and each of the holding circuits extends in one direction of the matrix and supplies different reference voltages. reference power lines are connected, said holding circuit selects said reference voltage is supplied to the pixel electrode in accordance with the held data, least one well of the reference power supply line, the matrix either An active matrix display device characterized by being shared by a plurality of pixels adjacent in the direction. The reference power line shared by adjacent pixels is capacitively coupled to the pixel electrode of one pixel, and an extended region is provided so that the reference power line is capacitively coupled to the pixel electrode of the other pixel The active matrix display device according to claim 3 . The reference power line shared by adjacent pixels is superimposed on the pixel electrode of one pixel, and an overlapping region is formed by extending the reference power line on the pixel electrode of the other pixel. The active matrix display device according to claim 3 .

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