JP4015517B2 - Ferroelectric liquid crystal device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a ferroelectric liquid crystal device, and more particularly to a ferroelectric liquid crystal device characterized by a drive voltage waveform applied to a scan electrode of a ferroelectric liquid crystal panel.
[0002]
[Prior art]
When a ferroelectric liquid crystal in which molecules are arranged in a spiral shape is disposed between substrates having a gap of about 2 μm, for example, a spiral structure cannot be formed, and the molecules are arranged along the substrate surface. When grooves are formed on the surface of the substrate by rubbing or vapor deposition so that the alignment direction is aligned over the entire ferroelectric liquid crystal panel, one of two different alignment states can be selected according to the electric field applied from the outside.
[0003]
This state will be described with reference to FIG. In FIG. 3, a state A shows a case where the electric field is directed from the top to the bottom of the paper, and a state B shows a case where the electric field is directed from the bottom to the top of the paper. FIG. 3A illustrates the direction of this electric field. FIG. 3B shows a molecular arrangement state. In the state A, the molecules 31 in the ferroelectric liquid crystal panel are arranged in a downward-sloping manner, and in the state B, the molecules 31 are downward-sloping to the right. Are arranged. This is two molecular arrangement states obtained by the direction of the applied electric field. FIG. 3C shows a state of the spontaneous polarization 32 of the molecule. In the case of a ferroelectric liquid crystal, the spontaneous polarization 32 is perpendicular to the long axis of the molecule 33 and exists at the end of the molecule. In the case of the state A, the spontaneous polarization 32 at the upper end of the molecule 33 that is descending to the left is directed from the top to the bottom of the paper, similarly to the electric field. In the case of the state B, the spontaneous polarization 32 at the upper end of the molecule 33 that is descending to the right is directed from the bottom to the top of the paper in the same manner as the electric field. In the ferroelectric liquid crystal panel, the arrangement direction of the molecules 31 is changed by the reversal of the spontaneous polarization 32.
[0004]
In a ferroelectric liquid crystal panel, two polarizing plates whose polarization axes are orthogonal to each other are arranged so as to sandwich a transparent substrate. At this time, if the molecular axes in one arrangement state and the polarization axis of one polarizing plate coincide with each other, an optical switch can be configured, and transmission and non-transmission of light can be controlled. In FIG. 3B, when the axes of the molecules in the arrangement state of state B coincide with the polarization axes of the polarizing plates, the light transmission white display state (on state) is obtained in the arrangement state of state A. In this state, a black non-transparent black display state (off state) is obtained. The characteristics of this optical switch are shown in FIG. The vertical axis represents the transmittance T, and the horizontal axis represents the product Vt of the voltage V applied between the substrates and the time t (hereinafter referred to as “applied voltage Vt”). When the applied voltage Vt is increased from the black display state where the transmittance is 0, the transmittance T starts to increase at the threshold value VA, and the white display state is entered. Conversely, when the applied voltage Vt is decreased from the white display state, the transmittance T starts to decrease at the threshold value VB, and the state shifts to the black display state. Since this optical switch has a hysteresis characteristic, it has a memory function. That is, since it has two threshold values VA and VB, each becomes an applied voltage Vt for writing and erasing and operates as a memory. If this optical switch is subdivided into pixels, the pixels are arranged in a matrix, and a memory property is used, a ferroelectric liquid crystal panel capable of graphic display is obtained. The matrix type ferroelectric liquid crystal panel will be described below.
[0005]
An example of a liquid crystal device using this ferroelectric liquid crystal panel will be described with reference to the block diagram of FIG. The power source + V supplies a voltage V1 and a ground level voltage to the liquid crystal device. The power source + V is connected to the display control circuit 504, the electrode drive voltage generation circuit 505, the scan electrode drive circuit 506, and the signal electrode drive circuit 507 from the outside of the liquid crystal device. The control signal group CS is input to the display control circuit 504 from an external central processing unit (hereinafter referred to as “CPU”). The control signal group CS is supplied to an element (hereinafter referred to as “display RAM”) that stores display data in the display control circuit 504 and an element that stores drive data (hereinafter referred to as “command register”). On the other hand, it is a signal group for controlling data writing and reading. The data bus DB is data to be written from the CPU to the display RAM and the instruction register, and data to be read from the display RAM and the instruction register to the CPU.
[0006]
The display control circuit 504 generates a clock with an oscillator (built in the display control circuit 504), and generates an electrode drive voltage generation circuit 505, a scan electrode drive circuit 506, and a signal electrode drive circuit 507 based on the clock and the value of the command register. Display control signals 514, 513, and 512 are output, respectively. Further, the display control circuit 504 outputs display data 511 read from the display RAM to the signal electrode drive circuit 507 by a memory control circuit (built in the display control circuit 504) that operates with a clock.
[0007]
The electrode drive voltage generation circuit 505 is applied to the scan electrodes 508 and the signal electrodes 509 of the ferroelectric liquid crystal panel 510 based on the display control signal 514 to drive the liquid crystal (hereinafter referred to as “drive voltage”). 516 and 515 are output to the scan electrode drive circuit 506 and the signal electrode drive circuit 507. Scan electrode drive circuit 506 generates a drive voltage waveform to be applied to scan electrode 508 from drive voltage 516 and display control signal 513. The signal electrode drive circuit 507 generates a drive voltage waveform to be applied to the signal electrode 509 from the drive voltage 515, the display control signal 512, and the display data 511. The intersection of the scanning electrode 508 and the signal electrode 509 is a pixel.
[0008]
In the ferroelectric liquid crystal panel, various devices have been added to the drive voltage waveform so that both the use of memory and the securing of reliability can be achieved at the same time. FIG. 6 shows an example of a drive voltage waveform for this purpose. FIG. 6A is a diagram showing drive voltage waveforms COMn-1 and COMn applied to the (n-1) th scan electrode and the nth scan electrode. The drive voltage waveforms COMn-1 and COMn both have a ternary level, and have a long pulse train at the beginning of application. The drive voltage waveforms COMn-1 and COMn have a selection pulse with the next short pulse width, and the selection pulse of the drive voltage waveform COMn appears after the selection pulse of the drive voltage waveform COMn-1.
[0009]
The long pulse train at the beginning is for initializing the entire ferroelectric liquid crystal panel before data is written to the ferroelectric liquid crystal panel. In the period in which this pulse train exists (hereinafter referred to as “reset period (Re)”), the entire ferroelectric liquid crystal panel is brought into a white display state in the period in which the first high voltage is applied. The entire ferroelectric liquid crystal panel is brought into a black display state during the period when the next low voltage is applied. This is repeated once more, and the entire ferroelectric liquid crystal panel is initialized to a black display state before data writing. In a ferroelectric liquid crystal panel, a large electric field due to spontaneous polarization exists in the liquid crystal layer, and impurity ions are unevenly distributed or the layer structure is changed by this electric field. This causes so-called “burn-in”, so that a long pulse train (product Vt of voltage V and pulse width t) is applied in the reset period before writing to diffuse impurity ions and stabilize the layer structure. I am trying.
[0010]
Next, the selection pulse will be described with reference to FIG. The selection pulse of the drive voltage waveform COMn-1 and the drive voltage waveform COMn applied to the scan electrode has a period (pulse width tp) in which a low voltage -Vs is first applied, and then a high voltage + Vs is applied. (Hereinafter referred to as “selection period (Se)”). In the drive voltage waveforms COMn-1 and COMn, the reference voltage VM having an intermediate value between + Vs and -Vs is applied in the non-selection period (NSe) that is a period excluding the selection period.
[0011]
First, the case where the pixel selected by the drive voltage waveform COMn displays black will be described. The drive voltage waveform SEGb applied to the signal electrode at this time has a voltage −Vd in the first half of the selection period and a voltage + Vd in the second half as shown in FIG. 6B. These voltages + Vd and -Vd are equal in absolute value to the center reference voltage VM. In the first half of the selection period, the voltage applied to the pixel is smaller than the threshold value VA in FIG. Ie
(−Vs − (− Vd)) × tp <VA
Therefore, the pixel is maintained in a black display state, which is an initialized state. Even in the second half of the selection period, the applied voltage to the pixel is
(+ Vs − (+ Vd)) × tp <VA
Since the voltages + Vs and + Vd are set such that the pixel is not rewritten, the black display state is maintained.
[0012]
In the non-selection period, other pixels may be displayed in black, so that the pulse has the same shape as the drive voltage waveform SEGb in FIG. 6B (the voltage value is alternately −Vd and + Vd with the pulse width tp). (Repeating pulse train) may be applied to the pixel on the nth scanning electrode from the signal electrode. However, in the non-selection period, the reference voltage VM is applied to the nth scan electrode, and the absolute value of the voltage (± Vd × tp) applied to the pixel is smaller than the threshold value VA, so that the display data of this pixel is rewritten. Absent. For this reason, this pixel continues to maintain the black display state. In addition, since the absolute values of the applied voltages in the first half and the second half of the selection period are equal and opposite in sign, the sum of the applied voltages becomes 0 in all periods including the reset period, the selection period, and the non-selection period, and the AC drive is performed. Is established. As a result, no direct current component remains in the pixel, so that it is possible to drive with high reliability.
[0013]
Next, a case where the pixel selected by the drive voltage waveform COMn displays white will be described. At this time, the drive voltage waveform SEGw applied to the signal electrode becomes the central reference voltage VM throughout the selection period. In the first half of the selection period, the voltage applied to the pixel is smaller than the threshold value VA in FIG. Ie
(−Vs−VM) × tp <VA
Therefore, the pixel maintains the black display state, which is the previous state. In the second half of the selection period, the voltage applied to the pixel is
(+ Vs−VM) × tp> VA
Thus, since the voltage + Vs is set, the pixel is rewritten and a white display state is obtained. In the subsequent non-selection period, as described above, other pixels may display black, and thus a pulse having the same shape as the drive voltage waveform SEGb in FIG. 6B is applied to this pixel. However, since the reference voltage VM is applied in the non-selection period, the absolute value of the applied voltage (± Vd × tp) is smaller than the absolute value of the threshold value VA or the threshold value VB, and the display data of the pixel is not rewritten. The monochrome display state is maintained until the next initialization. In this case, AC driving is also established.
[0014]
When the scan electrode drive circuit 506 shown in FIG. 5 is an integrated circuit (hereinafter referred to as “scan electrode drive IC”), at least the scan electrode drive IC includes
(+ Vs) × 2
A large voltage is applied. In general, a high breakdown voltage IC has a large chip size, and the chip area is approximately proportional to the square of the breakdown voltage. Therefore, the scan electrode driving IC of the ferroelectric liquid crystal panel is large. On the other hand, an oscillating power supply is known as a method for obtaining a drive voltage waveform as shown in FIG. Oscillating power supplies are widely used in super twisted nematic (hereinafter referred to as “STN”) panels and active matrix panels having two-terminal switches (called “MIM active panels” or “TFD active panels”). . A technique in which this is applied to a ferroelectric liquid crystal panel is disclosed. (For example, refer to Patent Document 1).
[0015]
[Patent Document 1]
Japanese Patent Laid-Open No. 62-237432
[0016]
The swing power supply will be described with reference to the waveform diagram shown in FIG. The signal DF is a signal that gives the timing and polarity of oscillation with respect to the oscillation power sources VDD, VCC, and VSS, and is periodically inverted by one of the signals of the display control signal group 514 in FIG. The signal IN is an example of another signal of the display control signal group 514. Here, in the signals DF and IN, the high level is the power supply voltage V1 of the liquid crystal device shown in FIG. 5, and the low level is the ground level (0 V). In FIG. 7A, since the voltage −Vd and the ground level are equal, the ground level is not shown again. The upper oscillating power supply VDD is a square wave and in an inverted relationship with the signal DF, and has a maximum voltage value of + Vs and a minimum voltage value of + Vd. The logic oscillation power supply VCC is a square wave having the same shape as the oscillation power supply VDD, the highest voltage is clamped to the power supply voltage V1, and the lowest voltage value is −Vs + V1. Similarly, the oscillating power supply VSS is a square wave having the same shape as the oscillating power supply VDD, the highest voltage is clamped to -Vd, and the lowest voltage value is -Vs.
[0017]
Here, the voltage VM functions as a reference voltage level in driving the ferroelectric liquid crystal panel. FIGS. 7B and 7C are diagrams showing waveforms when the signal IN is shifted from the power supply level of the liquid crystal device to the level of the oscillating power supply in two stages. In the first stage, when the control signal IN is at a high level, the power supply voltage V1 is obtained. In the second stage, the signal Lev1 is converted into a signal OUT that becomes the oscillating power supply VCC when the control signal IN is at the high level and becomes the oscillating power supply VSS when the control signal IN is at the low level. Since the potential difference between the oscillating power supply VCC and the oscillating power supply VSS is about 3 V, the control circuit of the scan electrode driving IC is a low voltage circuit.
[0018]
With reference to FIG. 8, a method of generating the drive voltage waveform COMn of the scan electrode shown in FIG. 6 from the oscillating power supplies VDD and VSS will be described. The relationship between the voltages of the oscillating power supply is the same as in FIG. In FIG. 8A, the oscillating power supplies VDD and VSS have a long pulse width during the reset period (Re) and a short pulse width during the selection period (Se) in which writing is performed. The drive voltage waveform COMn selects one voltage from the oscillation power supply VDD, VSS and the center reference voltage VM based on a control signal of a circuit for driving the nth scan electrode (hereinafter referred to as “output buffer”). Generated. Specifically, in the reset period, the drive voltage waveform COMn is first selected as VDD, second as the swing power supply VSS, third again as VDD, and finally as VSS in accordance with the switching of the swing power supply. In the selection period, the driving voltage waveform COMn is selected to be VSS in the first half and VDD in the second half. In other periods, the center reference voltage VM is selected. As a result, the drive voltage waveform COMn in FIG. 8B is equal to the drive voltage waveform COMn of the scan electrode in FIG.
[0019]
FIG. 9 is a diagram showing the configuration of the nth output buffer. This output buffer is provided in the scan electrode driving circuit 506 of FIG. The source of the P-type transistor Tr1 is connected to the oscillation power supply VDD, and the control signal S1 is input to the gate. The source of the N-type transistor Tr4 is connected to the swing power supply VSS, and the control signal S4 is input to the gate. The P-type transistor Tr2 and the N-type transistor Tr3 form a transmission gate, the source is connected to the reference voltage VM, and control signals S2 and S3 are input to the respective gates. The control signals S2 and S3 are in an inverted relationship. The drains of the transistors Tr1, Tr2, Tr3, Tr4 are connected to Pad, and the protection circuit diodes D1, D2 are also connected to Pad.
[0020]
When the transistor Tr1 is turned on by the control signal S1, the swing power supply VDD is output from the Pad, and the swing power supply VDD is selected. Similarly, when the transistor Tr4 is turned on by the control signal S4, the swing power supply VSS is selected. Further, when the transistors Tr2 and Tr3 are turned on by the control signals S2 and S3, the reference voltage VM is selected.
[0021]
As can be seen from FIG. 8A, when the oscillating power source is used, the maximum voltage (MaxV) applied to the scan electrode driving IC is the difference between the oscillating power source VDD and the oscillating power source VSS. This difference is indicated as MaxV in FIG. Since the maximum voltage value of VDD is + Vs and the maximum voltage value of VSS is −Vd with respect to the reference voltage VM, MaxV is + Vs + Vd. This is almost halved compared to the maximum voltage (+ Vs) × 2 applied to the scan electrode driving IC when no oscillating power supply is used. As a result, the scan electrode driving IC can halve the withstand voltage by using the oscillating power supply, and the chip area can be reduced to almost ¼.
[0022]
[Problems to be solved by the invention]
In the description so far, the load of the ferroelectric liquid crystal panel driven by the scan electrode driving IC has been ignored. This load was negligible in the STN panel and the two-terminal type active panel. However, in the ferroelectric liquid crystal panel, as described above, the liquid crystal layer is thin, for example, about 2 μm, and the relative permittivity of the ferroelectric liquid crystal is very large. Therefore, a large capacitive load is parasitic on each scanning electrode. For this reason, the drive voltage waveform is greatly deformed. This state will be described with reference to FIG. The actual drive voltage waveform COMn2 (solid line) discharges the charges charged in the pixels as opposed to the waveform (dashed line) when the panel load is ignored, so that the edge portion of the pulse draws a time constant curve. In particular, the scan electrode driving IC may be destroyed at the edge portion e1 where the voltage −Vs changes to the voltage + Vs.
[0023]
This will be described with reference to FIG. Immediately after the edge portion e1, the transistor Tr1 becomes conductive, and the oscillation power supply VSS becomes the voltage −Vd. On the other hand, the voltage of the pad portion is close to the voltage −Vs due to the large parasitic capacitance described above. As a result, a current flows through the diode D2 and the transistor Tr1. In particular, the voltage between the source and the drain of the transistor Tr1 is (+ Vs) × 2, and a current flows and heat is generated intensely in a large potential difference far exceeding the breakdown voltage, so that the transistor Tr1 is most easily destroyed. The same applies to the reset period as well as the selection period. Further, in the reset period, the transistor Tr4 may be destroyed at the edge portion where the drive voltage waveform COMn changes from the voltage + Vs to the voltage −Vs.
[0024]
Accordingly, an object of the present invention is to provide a ferroelectric liquid crystal device in which a scan electrode driving IC is not destroyed even when an oscillating power supply is used.
[0025]
[Means for Solving the Problems]
In the present invention, the circuit for driving the scanning electrode of the ferroelectric liquid crystal panel is an integrated circuit, and this integrated circuit is driven by the oscillating power source, and the pulse width of the driving voltage waveform of the scanning electrode is greater than the pulse width of the oscillating power source. It is characterized by being short. Also, the time from the rear end of the pulse in the drive voltage waveform of the scan electrode to the front end of the pulse in the oscillating power supply is the same as the period in which the edge portion of the rear end of the pulse in the drive voltage waveform of the scan electrode shows a time constant curve, It is characterized by being longer than that. Similarly, the pulse width of the drive voltage waveform of the signal electrode is preferably shorter than the pulse width of the oscillating power supply.
[0026]
Further, the pulse in the drive voltage waveform of the scan electrode has a positive pulse and a negative pulse, and a period that is an intermediate value between the positive pulse and the negative pulse may be provided between the pulses. Desirably, the drive voltage waveform of the scan electrode is preferably provided with a period that becomes an intermediate value after setting the penetration removal period from the rear end of the pulse in the drive voltage waveform of the scan electrode.
[0027]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to FIGS. 1 and 2. FIG. 1 shows a waveform diagram in the reset period (Re), and FIG. 1 (a) shows a drive voltage waveform COMn according to the present invention output from the nth output buffer when there is no load. FIG. 1B shows a drive voltage waveform COMn1 according to the present invention when a load having a capacity output from the nth output buffer is generated when the scan electrodes are connected. FIG. 1C shows a control signal for the nth output buffer.
[0028]
FIG. 2 is a waveform diagram in the selection period, and FIG. 2A shows a drive voltage waveform COMn according to the present invention output from the nth output buffer when there is no load. FIG. 2B shows a drive voltage waveform COMn1 according to the present invention when a load having a capacity output from the nth output buffer is generated when the scan electrodes are connected. FIG. 2C shows a control signal for the nth output buffer. FIG. 2D shows the drive voltage waveform of the signal electrode. The output buffer built in the scan electrode driving IC which is an integrated circuit is the same as that shown in FIG. 9, but the driving voltage waveform COMn has a different waveform because the control signals are different. However, since the circuit of the output buffer is common, the symbols in FIG. 1 and FIG. 2 are the same as those in FIG. 8 and FIG.
[0029]
First, the state of the reset period will be described with reference to FIG. In FIG. 1A, in the first pulse of the drive voltage waveform COMn, the rising edge of the front edge is delayed from the rising time of the oscillating power supply VDD, and the falling edge of the trailing edge is the oscillating power supply VDD. The fall is earlier than the time. In the second pulse, the falling edge of the front edge is delayed from the falling time of the oscillating power supply VSS, and the rising edge of the rear edge is earlier than the rising time of the oscillating power supply VSS. The third and fourth pulses are the same as the first and second pulses, respectively. Thus, the pulse width of the drive voltage waveform COMn of the scan electrode is shorter than the period (pulse width) in which the oscillating power supplies VDD and VSS oscillate.
[0030]
The drive voltage waveform COMn1 in FIG. 1B is deformed from the drive voltage waveform COMn in FIG. 1A due to the capacitive load of the scan electrodes. The first positive pulse in the drive voltage waveform COMn1 rises with the leading edge drawn by a time constant curve determined by the capacitive load of the transistor Tr1 and the scan electrode, and the trailing edge from the capacitive load of the transistors Tr2, Tr3 and the scan electrode. It falls in the period t1 while drawing the determined time constant curve. At this time, the drive voltage waveform COMn1 returns to the reference voltage VM before the oscillating power supply VDD falls. In other words, the next pulse of the oscillating power source starts after the period t1 when the trailing edge of the pulse in the drive voltage waveform COMn1 shows a time constant curve. That is, whether the time t from the rear end of the pulse of the drive voltage waveform COMn1 to the front end of the pulse of the oscillating power supply is the same as the period t1 showing the time constant curve at the rear end edge of the pulse of the drive voltage waveform COMn1. It is set longer than that. In other words, after the waveform based on the time constant curve is shown at the trailing edge portion of the pulse of the drive voltage waveform COMn1, the next pulse of the oscillating power supply starts after the constant voltage VM is reached. Note that the time t may be substantially the same as the period t1 indicating the time constant curve. That is, it is sufficient if t ≧ t1. However, when t> t1, the influence of the time constant curve is less likely to be affected.
[0031]
Similarly, for the second negative pulse, the leading edge falls while drawing the time constant curve determined by the capacitive load of the transistor Tr4 and the scanning electrode at the leading edge, and the transistors Tr2, Tr3 and the scanning electrode at the trailing edge. It rises in the period of t1 while drawing a time constant curve determined from the capacity load. At this time, the drive voltage waveform COMn1 returns to the reference voltage VM before the oscillation power supply VSS rises. The third and fourth pulses are the same as the first and second pulses, respectively.
[0032]
FIG. 1C shows the waveforms of the control signals S1, S3 and S4 in FIG. The transistor Tr1 becomes conductive when the control signal S1 is at a low level, and at this time, VDD is output from Pad. The transistor Tr4 is turned on when the control signal S4 is at a high level, and at this time, VSS is output from the Pad. The transmission gate composed of the transistors Tr2 and Tr3 is turned on when the control signal S3 is at a high level. The control signal S2 is omitted because it is in an inverted relationship with the control signal S3. The control signal S3 becomes a high level between the edges of the oscillation power supply VDD and VSS, that is, before and after the positive pulse and the negative pulse of the drive voltage waveform COMn, and at this time, the reference voltage VM is output from the Pad.
[0033]
Thus, the time t from the trailing edge of each pulse of the drive voltage waveform COMn at the time of no load to the edge of the oscillating power supply VDD and VSS is the charge / discharge time determined by the capacity load of the scan electrode and the capability of each transistor, That is, it is set to be equal to or larger than the period t1 indicating the time constant curve (t ≧ t1). By setting in this way, even when a time constant curve is generated at the edge portion of the pulse as seen in the drive voltage waveform COMn1 in FIG. 1B, the edge falls to the reference voltage VM or rises. Therefore, when the switching power supply VSS is switched from the oscillating power supply VSS to the oscillating power supply VDD or vice versa, a current flows in the transistor Tr1 or the transistor Tr4 in a potential difference exceeding the withstand voltage. There is nothing.
[0034]
Note that a through current removal period c1 with a minute delay is provided between the falling edge of the control signal S4 and the rising edge of the control signal S3 in FIG. This period c1 is provided to turn on the transmission gate after the transistor Tr4 is completely non-conductive, and to remove unnecessary through current that causes an increase in power consumption and IC breakdown. Generated using a delay circuit. Similarly, a minute delay for removing a through current between the transistor Tr1 and the transmission gate is also provided, and one is turned off and the other is turned on.
[0035]
Next, the state of the selection period (Se) will be described with reference to FIG. The pulse width in the oscillation power source is shown in the same manner as the reset period (Re) in FIG. 1A, but actually, in the selection period (Se) as compared to the reset period (Re) as shown in FIG. The pulse width of the oscillating power supply is shortened. However, the time constant curve is commonly generated in the reset period (Re) and the selection period (Se). In FIG. 2A, the selection pulse of the drive voltage waveform COMn has a negative pulse and a positive pulse. The positive polarity pulse of the first half is delayed from the falling time of the oscillating power supply VSS at the falling edge of the leading edge, and the rising time of the trailing edge is earlier than the rising time of the oscillating power supply VSS. In the latter half of the positive polarity pulse, the rising edge of the leading edge is delayed from the rising time of the oscillating power supply VDD, and the falling edge of the trailing edge is earlier than the falling time of the oscillating power supply VDD. That is, the pulse width of the drive voltage waveform COMn is shorter than the pulse width of the oscillating power supply.
[0036]
A drive voltage waveform COMn1 in FIG. 2B shows a state deformed from the drive voltage waveform COMn in FIG. 2A due to the capacitive load of the scan electrode. Regarding the deformation, similarly to the waveform of the reset period shown in FIG. 1B, the same time constant curve is drawn at the edge portions at the front and rear ends of the pulse in the waveform of the selection period shown in FIG. FIG. 2C shows the waveforms of the control signals S1, S4 and S3 in FIG. The operation of these control signals is the same as the operation of the signals shown in FIG.
[0037]
FIG. 2D shows a voltage waveform applied to the signal electrode. When the black display state is maintained, the drive voltage waveform SEGb is applied to the signal electrode, and in order to shift to the white display state, the drive voltage waveform SEGw is applied. As shown in FIG. 2D, the pulse width of the drive voltage waveform SEGb is shorter than the pulse width of the oscillating power supply VDD and VSS, like the pulse width of the drive voltage waveform COMn shown in FIG. Before and after the reference voltage VM. This occurs when the drive voltage waveform of the signal electrode is switched, and differential noise propagating to the scan electrode due to capacitive coupling is shifted from the switching timing of the oscillating power supply VDD and VSS, so that the scan electrode drive IC is destroyed or malfunctions. It is for preventing.
[0038]
【The invention's effect】
Ferroelectric liquid crystal has a much larger capacitive load than STN panels, and in the reset period and selection period, there is a positive polarity pulse immediately after the negative polarity pulse. If used, the scan electrode driving IC is destroyed. In the present invention, the pulse width of the drive voltage waveform of the scan electrode is made shorter than the pulse width of the oscillating power supply, not by correcting the deformation of the drive voltage waveform, but by changing the pulse edge of the drive voltage waveform. This is because the drive voltage waveform is made substantially equal to the reference voltage, which is the center voltage, before the oscillating power supply changes. This means that the charge flowing back from the capacitance parasitic on the scan electrode is returned to the reference voltage. For this reason, even if a positive pulse and a negative pulse continue in the drive voltage waveform, there is no current flowing from the highest voltage to the lowest voltage. Therefore, according to the present invention, it is possible to provide a ferroelectric liquid crystal device in which an IC is not destroyed even when a scan electrode driving IC having a reduced breakdown voltage using an oscillating power supply is used.
[0039]
In the above embodiment, the leading edge or trailing edge of the driving voltage waveform pulse is delayed from the leading edge or trailing edge of the oscillation power supply pulse. However, the same effect can be obtained by matching the front end of the pulse of the drive voltage waveform with the front end of the pulse of the oscillating power supply.
[0040]
Although the present invention has been described using the drive voltage waveforms applied to the scan electrodes and the signal electrodes, the drive device of the present invention can be applied to an “MIM type active panel” or “TFD type active panel” having a two-terminal type switch. Even if is used, the same effect can be obtained.
[Brief description of the drawings]
FIG. 1 is a waveform diagram of a reset period in an embodiment of the invention.
FIG. 2 is a waveform diagram of a selection period in the embodiment of the invention.
FIG. 3 is a diagram for explaining a molecular arrangement of a ferroelectric liquid crystal panel.
FIG. 4 is a graph showing hysteresis characteristics of a ferroelectric liquid crystal panel.
FIG. 5 is a block diagram of a conventional ferroelectric liquid crystal device.
FIG. 6 is a waveform diagram of a conventional example.
FIG. 7 is a waveform diagram of an oscillation power supply.
FIG. 8 is an explanatory diagram of a relationship between an oscillation power supply and a driving voltage waveform.
FIG. 9 is an explanatory diagram of an output buffer circuit.
[Explanation of symbols]
506 Scan electrode drive circuit
507 Signal electrode drive circuit
508 Scan electrode
509 Signal electrode
510 Ferroelectric liquid crystal panel
Drive voltage waveform of the nth scan electrode at no load of COMn
COMn1, COMn2 Drive voltage waveform of the nth scan electrode when the scan electrode is connected
VDD, VSS, VCC Oscillating power supply
S1, S2, S3, S4 nth output buffer control signals
c1 Through-current removal period
SEGb Signal electrode drive voltage waveform when maintaining black display state
SEGw Signal electrode drive voltage waveform when shifting to the white display state
VA, VB threshold
+ Vs, -Vs, + Vd, -Vd, VM Voltage
Tr1, Tr2, Tr3, Tr4 transistors

Claims (5)

A ferroelectric liquid crystal device having a scanning electrode and a signal electrode between a pair of substrates sandwiching a ferroelectric liquid crystal,
The circuit for generating the drive voltage waveform of the scan electrode is an integrated circuit,
The integrated circuit generates the drive voltage waveform using an oscillating power supply,
A ferroelectric liquid crystal device, wherein a pulse width of the generated drive voltage waveform is shorter than a pulse width of the oscillation power supply. 2. The ferroelectric liquid crystal device according to claim 1, wherein a pulse width of a driving voltage waveform of the signal electrode is shorter than a pulse width of the oscillating power source. The time t from the rear end of the pulse of the drive voltage waveform of the scan electrode to the front end of the pulse of the oscillating power supply is the period t1 in which the edge portion of the pulse of the drive voltage waveform of the scan electrode shows a time constant curve. The ferroelectric liquid crystal device according to claim 1, wherein the ferroelectric liquid crystal device is equal to or longer than. The drive voltage waveform of the scan electrode has a positive polarity pulse and a negative polarity pulse, and the voltage value of the positive polarity pulse and the negative polarity pulse are between the positive polarity pulse and the negative polarity pulse. 2. The ferroelectric liquid crystal device according to claim 1, wherein a period having a voltage value intermediate to the voltage value is provided. 2. The ferroelectric liquid crystal device according to claim 1, wherein a through current removal period is set at a rear end of a pulse of the drive voltage waveform of the scan electrode. 3.

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