JP4013842B2 - Method for manufacturing silicon carbide semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To prevent lowering of breakdown strength of a gate insulating film involved in formation of an ohmic contact to SiC. <P>SOLUTION: The method comprises processes for: forming a first metallic film 12 for an ohmic contact on a gate electrode 8 wherein a layer insulating film 10 is selectively removed and on an ohmic contact formation region; and leaving a first metallic film 12 only in the ohmic contact formation region by selectively removing the first metallic film 12 formed on the gate electrode 8 in the first metallic film 12 formed in the process. <P>COPYRIGHT: (C)2005,JPO&amp;NCIPI

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a method for manufacturing a silicon carbide semiconductor device including a heat treatment for forming a low-resistance ohmic contact to a silicon carbide semiconductor.
[0002]
[Prior art]
In recent years, research on semiconductor devices utilizing the thermally and chemically stable properties of silicon carbide (hereinafter referred to as SiC) has been actively conducted. Silicon carbide semiconductor crystals are roughly classified into hexagonal α-type and cubic β-type, and there are many polymorphs such as 2H, 3C, 4H, 6H, and 15R. SiC is one of the wide band gap semiconductors. The 4H type has a forbidden band width of 3.26 eV, which is about three times larger than that of silicon. Therefore, it has excellent electrical withstand voltage characteristics and can be applied to power control devices. Is expected.
[0003]
On the other hand, there is a problem in the manufacturing process caused by the large energy band gap. One of them is the formation of ohmic contacts. At present, a good ohmic contact formation process includes a so-called room temperature contact method in which contact metal is deposited on the SiC surface to obtain the ohmic contact as it is, and a method of forming an interface reaction layer with SiC by performing a heat treatment after the deposition ( Post Deposition Annealing method (hereinafter referred to as PDA method).
[0004]
In the stable operation under high temperature environment and the miniaturization of elements, which are the characteristics of SiC devices, the use of dry etching processing technology for the opening of contact holes, and the room temperature contact method that currently does not use heat treatment Considering that good ohmic characteristics cannot be obtained for p-type SiC, etc., the formation of ohmic contacts in the device process has the advantage that the design / manufacturing margin can be expanded by using the PDA method.
[0005]
As a conventional semiconductor device using SiC having such characteristics, for example, those described in the following document (see Patent Document 1) are known, and an ohmic contact is made between a silicon carbide substrate and a metal electrode. As a technique of the manufacturing method, for example, one described in the following document (see Patent Document 2) is known.
[0006]
Typical examples of the metal material used for forming the ohmic contact by the PDA method include Ni, Ti, and Pd. Ni forms an intermetallic compound (silicide) with SiC by heat treatment at 900 to 1000 ° C., and not only provides good ohmic contact with n-type SiC, but also has ohmic properties with respect to p-type SiC. Show. For this reason, it is widely used for forming elements such as MOSFET, MESFET, and JFET made of SiC.
[0007]
As an example applied to a SiC vertical MOSFET expected as an ultra-low loss switching device, for example, one described in the following document (see Non-Patent Document 1) is known. The SiC vertical MOSFET described in this document shows a method for forming an ohmic contact by using Ni as a source and p-well contact material and performing a heat treatment at a contact annealing temperature of 900 ° C.
[0008]
Further, nitrogen monoxide gas (NO gas) is used to form the gate oxide film, and high electron mobility is obtained in the inversion channel. For the gate electrode, PolySi (polysilicon) doped with phosphorus at a high concentration, which is widely used in the manufacturing process of silicon semiconductors, is used. This indicates that good MOSFET static characteristics can be obtained.
[0009]
[Patent Document 1]
JP 2000-022137 A
[0010]
[Patent Document 2]
JP 2002-289555 A
[0011]
[Non-Patent Document 1]
R. Schorner et al. , Applied Physics Letters, Volume 80, Number 22, 2002.
[0012]
[Problems to be solved by the invention]
However, in manufacturing the conventional silicon carbide semiconductor device as described above, the following problems have been caused.
[0013]
FIG. 8A and FIG. 8B are diagrams showing a cross-sectional structure of a MOS capacitor formed on the same substrate as the SiC-MOSFET. In FIG. 8A, on the high-concentration n-type SiC substrate 80, 1 × 10¹⁶cm^-3An n-type epitaxial layer 81 having an impurity concentration of about 10 is formed to a thickness of about 10 μm. On the surface of the n-type epitaxial layer 81, a gate oxide film 82 made of a silicon oxide film is formed in a predetermined position at a thickness of about 50 nm and a field oxide film 83 is formed at a thickness of about 600 nm. From the gate oxide film 82 to the field oxide film 83, a high-concentration n-type polysilicon film for controlling the gate potential is deposited by LPCVD to a thickness of about 350 nm, and patterned by photolithography and etching to form a gate electrode. 84 is formed. Further, a thick interlayer insulating film 85 is formed on the gate electrode 84 so as to cover the gate electrode 84.
[0014]
In order to form an ohmic contact for wiring extraction on the polysilicon gate electrode 84, first, the interlayer insulating film 85 facing the 350 nm thick gate electrode 84 immediately above the gate oxide film 82 is formed simultaneously with the source and p-well contacts. A contact hole 86a is formed by opening. Thereafter, the same contact metal material as that of the source and p-well contacts, for example, Ni is deposited on the gate electrode 84 of the contact hole 86a, and heat treatment is performed at about 1000 ° C. for about 2 minutes in an Ar atmosphere, thereby forming Ni of the contact metal material. And a reaction layer 87a of polysilicon of the gate electrode 84 is formed. At this time, although not shown, a reaction layer of Ni and SiC is also formed on the source and p-well contact of the MOSFET formed on the same SiC substrate 80.
[0015]
Finally, on the Ni / polysilicon reaction layer 87a and the interlayer insulating film 85, an extraction electrode 88, which is one electrode of the MOS capacitor, is formed of, for example, Al, and the other electrode 89 of the MOS capacitor is formed on the SiC substrate. The MOS capacitor is completed on the back surface of 80.
[0016]
On the other hand, in the configuration shown in FIG. 6B, the process until the formation of the interlayer insulating film 85 is the same as that in FIG. 6A, but the contact hole 86b is gated as shown in FIG. As shown in FIG. 5B, not on the oxide film 82, an interlayer insulating film 85 on the polysilicon gate electrode 84 extended on the field oxide film 83 is formed with an opening, and formed contacts. A reaction layer 87b of Ni as a contact metal material and polysilicon of the gate electrode 84 is formed in the hole 86b.
[0017]
When the C (capacitance) -V (voltage) characteristics or the I (current) -V (voltage) characteristics of the MOS capacitors shown in FIGS. 8A and 8B were examined, the gates in FIG. A large leakage current was observed between the electrode 84 and the SiC substrate 80, and a breakdown voltage defect of the gate oxide film 82 occurred in the short mode. On the other hand, in the MOS capacitor having the configuration shown in FIG. 4B, the same leakage current was not observed, and the breakdown voltage defect of the gate oxide film 82 did not occur.
[0018]
Such a phenomenon can be explained as follows.
[0019]
Ni, which is an ohmic contact metal deposited on a polysilicon gate electrode 84 having a thickness of about 350 nm, is thermally diffused in the polysilicon by a contact annealing process at about 1000 ° C. for about 2 minutes. . The diffusion constant (D) of Ni in silicon at about 1000 ° C. is 2 × 10^-9cm²Assuming approximately / sec, the diffusion length √Dt for diffusing in silicon by heat treatment for 2 minutes is approximately 4.9 μm.
[0020]
Thereby, Ni deposited on the polysilicon surface easily reaches the interface of the polysilicon / silicon oxide film (gate oxide film 82). Ni that has reached the polysilicon / silicon oxide film interface is deposited by forming an intermetallic compound (silicide) in the cooling process after the heat treatment. The silicide deposited at this time bites into the silicon oxide film and locally thins the silicon oxide film. For this reason, it is considered that the effective electric field of the silicon oxide film in the thinned portion increases and the breakdown voltage of the silicon oxide film decreases. In the case where the precipitation is so intense that the precipitate breaks through the silicon oxide film, a leak failure due to pinholes occurs.
[0021]
Accordingly, the present invention has been made in view of the above, and an object of the present invention is to provide a method for manufacturing a silicon carbide semiconductor device that prevents a decrease in breakdown voltage of a gate insulating film due to the formation of an ohmic contact with SiC. There is to do.
[0022]
[Means for Solving the Problems]
  In order to achieve the above object, means for solving the problems of the present invention is a method for manufacturing a silicon carbide semiconductor device in which a silicon carbide semiconductor device is manufactured using a silicon carbide semiconductor as a base, on one surface of the silicon carbide semiconductor, A first step of selectively forming a first insulating film; a second step of selectively forming a gate insulating film on one surface of the silicon carbide semiconductor; and the first step. The gate formed on the first insulating film and in the second stepInsulationA third step of forming a gate electrode on the film;A fourth step of selectively covering the surface of the gate electrode with a second insulating film;An interlayer insulating film is formed onSecond insulating filmThe interlayer insulating film on the upper side and the interlayer insulating film on the ohmic contact formation region for forming an ohmic contact with the silicon carbide semiconductor are selectively removed.5And the step5The interlayer insulating film is selectively removed in the step,Second insulating filmForming a first metal film on the top and on the ohmic contact formation region;6And the process ofA seventh step of forming an intermetallic compound by reacting the first metal film formed on the ohmic contact formation region and the silicon carbide semiconductor;Formed on the gate electrodeThe second insulating film andSelective removal of the first metal filmDoFirst8And on the gate electrode and theIntermetallic compoundsA second metal film selectively formed on the second metal film;9It has the process of this.
[0023]
【The invention's effect】
ADVANTAGE OF THE INVENTION According to this invention, the fall of the withstand voltage in a gate insulating film by the metal used for ohmic contact with a silicon carbide semiconductor diffusing can be prevented, and a highly reliable silicon carbide semiconductor device can be manufactured.
[0024]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings.
[0025]
1, FIG. 2, FIG. 3 and FIG. 4 are cross-sectional views showing steps of the method for manufacturing the silicon carbide semiconductor device according to the first embodiment of the present invention. The manufacturing method of the first embodiment described below is an embodiment in which the present invention is applied to a SiC vertical MOSFET.
[0026]
First, in FIG. 1A, a low-concentration n-type epitaxial layer 2 is formed on a high-concentration n-type SiC substrate 1. There are many polymorphs of SiC crystals, but any polymorph such as 2H, 4H, 6H, 3C, and 15R may be used. Further, for example, the 4H type has been studied for the plane orientation of the surface of the SiC substrate 1, and any of (0001), (000-1), (11-20), (03-38), etc. is used. Thereafter, the same structure can be used for manufacturing.
[0027]
Next, in FIG. 1B, a source region 5 which is a high-concentration n-type region by ion implantation of phosphorus, nitrogen or the like and a p-type region by ion implantation of Al, boron or the like on the epitaxial layer 2. The p-type well region 3 and a high-concentration p-type region (p-type region) for increasing the surface concentration of the p-type well region 3 and making it easy to obtain ohmic contact⁺Type p-well contact) 4 is formed. These ion implantations are generally performed at a high temperature of about 500 to 1000 ° C. so that the impurities to be introduced are easily activated electrically.
[0028]
After introducing impurities into a predetermined region by such so-called high-temperature ion implantation, annealing treatment is performed in a temperature range of about 1500 to 1800 ° C. to electrically activate the introduced impurities. Conditions such as annealing time and atmosphere largely depend on the form of the annealing apparatus. For example, in the case of rapid high temperature annealing (RTA) processing using a lamp, activation of impurities, rough surface of the epitaxial layer 2, etc. Is performed in Ar gas for about 1 to 10 minutes.
[0029]
Although not shown in FIG. 1B, a thermal oxide film having a thickness of about 10 to 50 nm is grown on the surface of the epitaxial layer 2 by high-temperature thermal oxidation, and this is once removed by etching with an HF solution or the like. By performing this step, the surface of the epitaxial layer 2 can be exposed cleanly. The thermal oxide film formed here is generally called a sacrificial oxide film, and is an extremely important process for forming a good gate oxide film and a good ohmic contact between SiC and metal. Utility is allowed. The sacrificial oxidation process may be performed immediately before the formation of the gate oxide film in consideration of the effect and ease of manufacturing.
[0030]
Next, in FIG. 1C, a thick silicon oxide film is formed on the surface of the epitaxial layer 2 by atmospheric pressure CVD, a predetermined region is removed by photolithography and etching, and a region to be the field oxide film 6 is formed. Form. Although a thick silicon oxide film may be formed by a thermal oxidation method, the oxidation rate varies greatly depending on the crystal plane orientation of SiC.
[0031]
For example, in the case of dry oxygen oxidation by a thermal oxidation method, in 4H-SiC, the oxidation rate of the (000-1) plane is approximately 10 times that of the (0001) plane, so In the case of forming a thick oxide film, a thermal oxidation method may be used. In this case, the source region 5, the p-well contact region 4, and the p-well region 3 formed on the SiC substrate 1 by thermal oxidation are oxidized so that the junction depth does not become shallow or disappear due to the penetration of the oxidizing species. It is necessary to decide the conditions.
[0032]
Further, when the field oxide film 6 is made of the same material as the gate insulating film, the present invention is a problem of the prior art, which is caused by diffusion in the metal atom having a diffusion coefficient having temperature characteristics as shown in FIG. Needless to say, a thickness greater than that of the gate insulating film is necessary in order to prevent a breakdown voltage failure of the gate insulating film. When the thick field oxide film 6 is formed of a silicon oxide film, a film thickness of about 0.3 to 1.0 μm is used.
[0033]
Next, in FIG. 2D, the exposed surface other than the region of the field oxide film 6 is oxidized in a high-temperature thermal oxidation atmosphere to form a gate oxide film 7 having a MOS structure. Many methods have been researched and developed for forming a gate oxide film having a MOS structure. Also, for this oxidation method, the optimum temperature, atmosphere, annealing, and other conditions differ depending on the crystal plane orientation, and therefore optimum process conditions are appropriately selected. For example, an oxidation or annealing method using NO gas has been proposed for the (0001) plane of 4H—SiC.
[0034]
Next, in FIG. 2E, after the gate oxide film 7 is formed, polycrystalline silicon is deposited on the surface of SiC by a low pressure CVD method so as to have a thickness of about 350 nm. Since polycrystalline silicon is used as a gate electrode, it must have low resistance. For this reason, methods such as mixing gases containing impurity elements such as phosphorus and boron during deposition by the low pressure CVD method, or adding annealing to the liquid diffusion method and spin coating method after the deposition of polycrystalline silicon Similarly, impurities such as phosphorus and boron are introduced at a high concentration.
[0035]
Thereafter, photolithography is performed and the polycrystalline silicon is patterned by dry etching to form the gate electrode 8 on the field oxide film 6 and the gate oxide film 7. In FIG. 5E, the polycrystalline silicon on the gate oxide film 7 and the polycrystalline silicon on the field oxide film are separated and described. In FIG. Because there is a part that is omitted. In practice, these polycrystalline silicons have an integral structure and are electrically at the same potential. That is, in FIG. 9 (e), the gate electrode 8 on the field oxide film 6 and the gate electrode 8 on the gate oxide film 7 are shown separately, but FIG. 8 (e) is a sectional view only. For example, the shape of the channel region is an integrated gate electrode 8 electrically connected as a polygon such as a circle, hexagon, or rectangle.
[0036]
Subsequently, the gate oxide film 7 exposed by the etching of the polycrystalline silicon is removed by wet etching precisely adjusted such as dilute hydrofluoric acid solution so that the field oxide film 6 does not recede significantly.
[0037]
Next, as shown in FIG. 2F, the surface of the patterned polycrystalline silicon is selectively covered with a silicon oxide film 9. As a method for forming the silicon oxide film 9, a thermal oxidation method is preferable because it is also deposited on the surface of SiC that has been previously exposed by etching in the ordinary CVD method. Also in the thermal oxidation method, it is desirable that the difference in oxidation rate between SiC and polycrystalline silicon is larger.
[0038]
The oxidation rate of thermal oxidation by a general reaction tube depends on temperature and atmosphere. Regarding the temperature, SiC has a higher activation energy for oxidation than silicon, and hardly oxidizes at low temperatures. According to experiments by the inventors, for example, when a 4H—SiC (0001) surface is oxidized at 1100 ° C. for about 420 minutes by dry oxygen oxidation, only a thermal oxide film having a thickness of about 30 nm grows at most. On the other hand, when the silicon single crystal substrate is oxidized under the same conditions, it is oxidized by about 600 nm, so that the oxidation rate ratio is 20 times.
[0039]
Furthermore, the partial pressure of water vapor (P_H2O) Is high, the oxidation rate ratio between SiC and silicon further increases. FIG. 6 shows an H-type method in which ultrapure water, one of the thermal oxidation methods carried out by the inventors, is introduced directly into the interior of the reaction₂3 shows the dependency of the oxide film thickness on SiC and silicon on the partial pressure of water vapor in the oxidizing atmosphere by the direct oxidation method. In FIG. 6, if the water vapor partial pressure is 1.0, the oxidation rate on SiC becomes very small even at an oxidation temperature of about 1100 ° C. On the other hand, since the oxide film on silicon is formed thick, the oxidation rate ratio of SiC can be increased to almost infinite.
[0040]
From these experimental facts, it is possible to grow an oxide film selectively only on the surface of polycrystalline silicon by performing oxidation in an atmosphere at a low temperature and a high water vapor partial pressure.
[0041]
The silicon oxide film 9 on the polycrystalline silicon serves to prevent the metal thin film, which is an ohmic contact material on the SiC, from contacting the polycrystalline silicon in forming the contact hole on the gate electrode 8. Therefore, it is sufficient that the film thickness is about 10 to 200 nm.
[0042]
Next, in FIG. 3G, a thick interlayer insulating film 10 is formed so as to cover the surface by a method capable of forming a film at a relatively low temperature of about 300 to 400 ° C. such as an atmospheric pressure CVD method or a plasma CVD method. To do. Here, the thickness of the interlayer insulating film 10 formed on the gate electrode 8 is relatively thicker than the thickness of the interlayer insulating film 10 formed at least on the ohmic contact formation region for forming an ohmic contact on SiC. It is formed. As a method of forming the interlayer insulating film 10 formed on the gate electrode 8 to be thicker than the thickness of the interlayer insulating film 10 formed on the ohmic contact formation region, the surface of the gate electrode 8 is more than the surface of SiC. Is formed by using thermal oxidation conditions in which the oxidation rate by thermal oxidation is high.
[0043]
As the interlayer insulating film 10, for example, a so-called PSG film or BPSG film containing several mol% of phosphorus and boron can be used. Thereby, the gate electrode 8 and the source electrode (not shown) can be electrically insulated and separated.
[0044]
Next, as shown in FIG. 3H, n formed on the SiC substrate 1 is formed.⁺In order to open a contact hole for forming an extraction electrode to the gate electrode 8 extended on the source electrode 5 and the high-concentration p-type region 4 and the gate electrode 8 extended on the field oxide film 6, a predetermined position is formed by photolithography. A photoresist pattern 11 is selectively formed.
[0045]
Subsequently, etching is performed by dry etching or wet etching so that the exposed interlayer insulating film 10 on the SiC substrate 1 is completely removed, thereby forming a contact hole. At this time, since the silicon oxide film 9 is formed on the polysilicon forming the gate electrode 8 on the field oxide film 6, the interlayer insulating film 10 on the source region 5 and the high concentration p-type region 4 is removed. Even in this case, the thin silicon oxide film 9 remains at the bottom of the contact hole opened on the gate electrode 8. Of course, if the etching is performed excessively, the silicon oxide film 9 on the gate electrode 8 is also removed, so that the etching conditions are determined in consideration of the film thickness of the interlayer insulating film 10.
[0046]
Next, a metal such as Ni, Ti, Pd, Pt, Nb, W, Hf, V, Ta, Fe, Mo, Co, and Zr is used alone or as appropriate as the first metal film 12 by electron beam evaporation, sputtering, or the like. A combination or a silicide film of these metals is deposited to a thickness of about 50 to 300 nm. As the metal material to be vapor-deposited, a metal material that can provide ohmic contact with respect to n-type / p-type SiC is selected. For example, in Ni, silicide is formed by annealing at a temperature of about 800 to 1000 ° C. after deposition, and 10% of n-type SiC.^-6Ω · cm² Good ohmic contact on the order of tens can be obtained. Furthermore, for p-type SiC
10^-3Ω · cm²A level of ohmic contact can be obtained. This makes it possible to form an ohmic contact simultaneously with the n and p type regions by a single deposition.
[0047]
In the first embodiment, an ohmic contact is formed in the same contact hole with the same metal for the n-type source region 5 and the high-concentration p-type region 4. However, contact holes may be individually formed in each region by photolithography and etching, and different metals may be used so that the ohmic contact has the lowest resistance value for p-type and n-type. In addition, an element such as Al or B may be appropriately mixed with the metal material to form a thin film structure that has a low resistance to p-type SiC.
[0048]
The first metal film 12 is deposited on the photoresist pattern 11 on SiC, the bottom of the contact hole on the source region 5 and the high concentration p-type region 4, and the bottom of the contact hole on the gate electrode 8. The first metal film 12 at the bottom of the contact hole on the source region 5 and the high concentration p-type region 4 is in direct contact with the SiC surface, but is deposited on the bottom of the contact hole of the gate electrode 8. Is deposited on the silicon oxide film 9 and is not in contact with the polysilicon forming the gate electrode 8.
[0049]
Next, in FIG. 3I, the photoresist pattern 11 and the first metal film 12 on the photoresist pattern 11 are removed by dipping in a solvent that dissolves a photoresist material such as acetone, and contact is made by a so-called lift-off method. The first metal film 12 is left only at the bottom of the hole. When dissolving the photoresist pattern 11, if an ultrasonic wave is applied to the solution, the excess metal film can be effectively removed.
[0050]
At this time, since the shape of the contact hole changes depending on the type of photoresist used, the manufacturing method, the etching method of the interlayer insulating film 10 and the like, not only the contact hole on the SiC but also the inside of the contact hole on the gate electrode 8. The first metal film 12 may remain. In that case, only the first metal film 12 in direct contact with SiC can be left on the SiC by the following method.
[0051]
Next, the first method will be described with reference to FIG. In this method, the thin silicon oxide film 9 sandwiched between the first metal film 12 and the gate electrode 8 is etched with a dilute hydrofluoric acid solution or a buffered hydrofluoric acid solution with adjusted hydrofluoric acid concentration. Thus, the first metal film 12 such as Ni is lifted off and selectively removed. This method is particularly effective when a metal such as Ni that is not significantly etched by the hydrofluoric acid solution is used. Further, if the process is performed before the lift-off process for the photoresist pattern 11, the damage to the interlayer insulating film 10 can be reduced.
[0052]
In FIG. 4I-1, first, heat treatment (PDA) is performed to form an intermetallic compound 13 of the first metal film 12 and SiC. When Ni is used as the first metal film 12, an intermetallic compound 13 with SiC can be formed, for example, by performing heat treatment (PDA) under the annealing conditions described above.
[0053]
Subsequently, the thin silicon oxide film 9 remaining on the gate electrode 8 is removed with a dilute hydrofluoric acid solution, a buffered hydrofluoric acid solution, or the like with adjusted hydrofluoric acid concentration. At this time, the interlayer insulating film 10, the first metal film 12 formed in the contact hole opened on the SiC, or the intermetallic compound 13 of the first metal and SiC is also exposed to the hydrofluoric acid solution. If the treatment is performed at a low temperature for a short time, the silicon oxide film 9 on the gate electrode 8 can be removed without damaging other regions.
[0054]
In a contact hole formed by a single photolithography process, a metal layer in which an intermetallic compound 13 is formed that can provide ohmic contact with SiC only within the contact hole on SiC by the above-described first method is selected. Can be formed.
[0055]
Next, in FIG. 4 (j), an intermetallic compound 13 for obtaining an ohmic contact with SiC is selectively formed inside the contact hole on the SiC. After the surface is exposed, a second metal film is deposited by a method such as EB or sputtering. As the second metal film, it is necessary to obtain a low-resistance contact with both the gate electrode material and the intermetallic compound 13. Further, the second metal film has a role as an extraction electrode, and a metal such as Al having high adhesiveness with the interlayer insulating film 10 is desirable. Further, the second metal film may be an alloy film made of a plurality of different elements or a metal layer having a laminated structure. For example, Ti / Al, Ti / Al / W, etc. may be used.
[0056]
Subsequently, the second metal film is patterned by photolithography and etching to form a gate electrode pad 14 bonded to the gate electrode 8 and a source electrode pad 15 bonded to the intermetallic compound 13.
[0057]
  Finally, after removing an excess oxide film, CVD film, etc. formed during the manufacturing process as appropriate by etching or grinding, the back surface of the SiC substrate 1 is good for high-concentration n-type SiC as the SiC substrate 1 A metal film capable of forming an ohmic contact is deposited, and the drain electrode 16 is formed on the back surface of the SiC substrate 1 to complete the vertical MOSFET.
[0058]
  In the first embodiment, since the first metal film 12 is formed only in the ohmic contact formation region with SiC, the first metal film 12 for ohmic contact is formed. The metal material atoms of the first metal film 12 used for the ohmic contact are thermally diffused in the gate electrode 8 due to the high temperature heat treatment performed when forming the ohmic contact, and the withstand voltage of the gate insulating film is lowered. Can be prevented. Thereby, a MOSFET element of a silicon carbide semiconductor device having high reliability can be provided.
[0059]
  In the first embodiment, since polycrystalline silicon is used as the material of the gate electrode 8, ohmic contact with the metal can be easily formed without performing high-temperature annealing.
[0060]
  Furthermore, in the first embodiment, as a method of forming the interlayer insulating film 10 on the gate electrode 8 to be relatively thicker than that on SiC, after the formation of the gate electrode 8, the surface of the gate electrode 8 is formed more than the SiC surface. By using thermal oxidation conditions in which the oxidation rate by thermal oxidation is higher, the interlayer insulating film 10 on the gate electrode 8 can be formed with a relatively thicker thickness than on SiC. This makes it possible to use a different metal material for the ohmic contact between SiC and the gate electrode 8.
[0061]
  In the first embodiment, in forming the ohmic contact between SiC and metal, the first metal film 12 for forming the ohmic contact is deposited and then subjected to high-temperature heat treatment, and then gated by the second metal film. Since the ohmic contact is formed on the electrode 8 and the ohmic contact is formed on the first metal film, the ohmic contact is performed by a high-temperature heat treatment performed when forming a low-resistance ohmic contact on SiC. It can be prevented that the metal material atoms of the first metal film 12 used for the contact are thermally diffused in the gate electrode 8 and the withstand voltage of the gate insulating film is lowered.
[0062]
Next, a second embodiment of the present invention will be described.
[0063]
FIG. 7 is a cross-sectional view showing a step of the method for manufacturing the silicon carbide semiconductor device according to the second embodiment of the present invention. This second embodiment is different from the previous first embodiment in that only the first metal film 12 in direct contact with SiC in FIG. 3I is formed as an intermetallic compound 13 with SiC. This is an embodiment of the second method to be left on, and is characterized in that the first metal film 12 is formed by vapor deposition in the contact hole formed on the SiC and the contact hole formed on the gate electrode 8. In this state, high-temperature heat treatment is performed. Other steps are the same as those in the first embodiment.
[0064]
In FIG. 7, after the process shown in FIG. 3I is completed, the first metal film 12 is formed only inside the contact hole by the lift-off process of the photoresist pattern 11, and the first metal film 12 is formed on the interlayer insulating film 10. No metal film 12 remains. The first metal film 12 on SiC forms an intermetallic compound 13 with SiC by high-temperature heat treatment. The first metal film 12 formed on the silicon oxide film 9 in the contact hole on the gate electrode 8 cannot form an intermetallic compound, and maintains the form of the first metal film 12.
[0065]
For example, Ni reacts with SiC by heat treatment at 900 to 1000 ° C. for about 1 to 10 minutes, and nickel silicide (for example, NiSi)₂However, Ni in contact with the silicon oxide film 9 does not cause a reaction to form an intermetallic compound. Nickel silicide is not etched in a sulfuric acid, phosphoric acid, or nitric acid solution, but is etched in a solution containing hydrofluoric acid. On the other hand, Ni is etched by, for example, a mixed solution of nitric acid and acetone. Therefore, only Ni inside the contact hole on the gate electrode 8 is etched and removed by an etching solution for once etching Ni. Subsequently, the thin silicon oxide film 9 remaining on the bottom of the contact hole on the gate electrode 8 is etched with a diluted hydrofluoric acid solution to expose the surface of the gate electrode 8. Note that the larger the etching rate ratio between nickel silicide and silicon oxide film by dilute hydrofluoric acid solution, the better.
[0066]
Also in the second embodiment, the same effect as that of the first embodiment can be obtained, and the first metal film in direct contact with SiC is left on SiC as the intermetallic compound 13. Can do.
[0067]
In the above embodiment, an embodiment using an n-type SiC substrate has been described. However, if a p-type SiC substrate is used depending on the type of element, of course, an ohmic contact is provided to the p-type SiC. Needless to say, metal materials and construction methods suitable for forming are used.
[0068]
In the above embodiment, the vertical MOSFET has been described as an example. However, the present invention can also be applied to a lateral MOSFET in which the drain region of the MOSFET is formed on the same substrate surface as the source region and the gate electrode. Furthermore, the manufacturing method described above can be applied to a sensor having a MOS structure as well as a so-called power element.
[Brief description of the drawings]
FIG. 1 is a cross sectional view showing a process of a method for manufacturing a silicon carbide semiconductor device according to a first embodiment of the invention.
FIG. 2 is a cross sectional view showing a step in the method for manufacturing the silicon carbide semiconductor device according to the first embodiment of the present invention.
3 is a cross-sectional view showing a process of the method for manufacturing the silicon carbide semiconductor device according to the first embodiment of the invention. FIG.
4 is a cross-sectional view showing a process of the method for manufacturing the silicon carbide semiconductor device according to the first embodiment of the invention. FIG.
FIG. 5 is a diagram showing temperature characteristics of diffusion coefficients in silicon of metal atoms.
FIG. 6 is a diagram showing an oxide film thickness on SiC and a relationship between an oxide film thickness on Si and a water vapor partial pressure.
FIG. 7 is a cross sectional view showing a step in the method for manufacturing the silicon carbide semiconductor device according to the second embodiment of the present invention.
FIG. 8 is a cross sectional view showing a configuration of a conventional silicon carbide semiconductor device.
[Explanation of symbols]
1,80 ... SiC substrate
2, 81 ... epitaxial layer
3 ... p-well region
4 ... p-type region
5 ... Source area
6, 83 ... Field oxide film
7, 82 ... Gate oxide film
8,84 ... Gate electrode
9 ... Silicon oxide film
10, 85 ... interlayer insulating film
11 ... Photoresist pattern
12 ... 1st metal film
13 ... Intermetallic compounds
14 ... Gate electrode pad
15 ... Source electrode pad
16 ... Drain electrode
86a, 86b ... contact holes
87a, 87b ... reaction layer
88 ... Extraction electrode
89 ... Electrode

Claims (3)

In a method for manufacturing a silicon carbide semiconductor device in which a silicon carbide semiconductor device is manufactured using a silicon carbide semiconductor as a base,
A first step of selectively forming a first insulating film on one surface of the silicon carbide semiconductor;
A second step of selectively forming a gate insulating film on one surface of the silicon carbide semiconductor;
A third step of forming a gate electrode on the first insulating film formed in the first step and on the gate insulating film formed in the second step;
A fourth step of selectively covering the surface of the gate electrode with a second insulating film;
An interlayer insulating film is formed on the entire surface, and the interlayer insulating film on the second insulating film and the interlayer insulating film on the ohmic contact formation region for forming an ohmic contact on the silicon carbide semiconductor are selectively removed. And a fifth step
A sixth step of forming a first metal film on the second insulating film and the ohmic contact formation region, wherein the interlayer insulating film is selectively removed in the fifth step;
A seventh step of forming an intermetallic compound by reacting the first metal film formed on the ohmic contact formation region and the silicon carbide semiconductor;
An eighth step of selectively removing said second insulating film and the first metal film formed on the gate electrode,
And a ninth step of selectively forming a second metal film on the gate electrode and the intermetallic compound . A method for manufacturing a silicon carbide semiconductor device, comprising: 2. The method of manufacturing a silicon carbide semiconductor device according to claim 1, wherein the gate electrode is formed of polycrystalline silicon doped with impurities at a high concentration. By using thermal oxidation conditions in which the surface of the gate electrode has a higher oxidation rate due to thermal oxidation than the surface of the silicon carbide semiconductor, the thickness of the interlayer insulating film on the gate electrode is set to the ohmic contact formation region. 3. The method for manufacturing a silicon carbide semiconductor device according to claim 1, wherein the silicon carbide semiconductor device is formed to be relatively thicker than a thickness of the upper interlayer insulating film.

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