JP4007242B2 - Semiconductor device - Google Patents

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JP4007242B2
JP4007242B2 JP2003106732A JP2003106732A JP4007242B2 JP 4007242 B2 JP4007242 B2 JP 4007242B2 JP 2003106732 A JP2003106732 A JP 2003106732A JP 2003106732 A JP2003106732 A JP 2003106732A JP 4007242 B2 JP4007242 B2 JP 4007242B2
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active region
gate
threshold voltage
control terminal
main
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JP2004311901A (en
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功 吉川
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Fuji Electric Co Ltd
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Fuji Electric Holdings Ltd
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/0601Structure
    • H01L2224/0603Bonding areas having different sizes, e.g. different heights or widths
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
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    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48111Disposition the wire connector extending above another semiconductor or solid-state body
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    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484Connecting portions
    • H01L2224/4846Connecting portions with multiple bonds on the same bonding area
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    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484Connecting portions
    • H01L2224/4847Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
    • H01L2224/48472Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
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    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491Disposition
    • H01L2224/4911Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
    • H01L2224/49113Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting different bonding areas on the semiconductor or solid-state body to a common bonding area outside the body, e.g. converging wires
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    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/13Discrete devices, e.g. 3 terminal devices
    • H01L2924/1301Thyristor
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    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/13Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304Transistor
    • H01L2924/1305Bipolar Junction Transistor [BJT]
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    • H01L2924/11Device type
    • H01L2924/13Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304Transistor
    • H01L2924/1305Bipolar Junction Transistor [BJT]
    • H01L2924/13055Insulated gate bipolar transistor [IGBT]
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    • H01L2924/11Device type
    • H01L2924/13Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304Transistor
    • H01L2924/1306Field-effect transistor [FET]
    • H01L2924/13091Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]

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  • Bipolar Integrated Circuits (AREA)

Description

【0001】
【発明の属する技術分野】
この発明は、電力変換装置などに使用されるバイポーラトランジスタやIGBT(絶縁ゲート型バイポーラトランジスタ)などのバイポーラモードで動作するバイポーラ型で自己消弧型の半導体装置に関する。
【0002】
【従来の技術】
ゲートアレイに用いられるMOSFETにおいて、通常、信号用の比較的小電流を流すベーシックセルと、出力部に用いられる大きな電流を流すベーシックセルとを別々に形成している。そのため、ゲートアレイにおけるベーシックセルの使用率の低下と回路設計の自由度の低下を招いていた。これを解決するために、ベーシックセルを構成するMOSFETにおいて、複数個にゲート電極を分割し、個別電極に選択的に電圧を印加することで、チャネル長を変更し複数種類の動作状態を有するようにすることで、ゲートアレイにおけるベーシックセルの使用率の向上と回路設計の自由度の確保がなされていることが知られている(特許文献1参照)。
【0003】
また、過電流保護機能を内蔵したMOSFETにおいて、被検出MOSFETのゲート電極をゲート幅方向(チャネル長と直角方向)に幾つか分割し、分割されたゲート電極の電位をしきい値以下に低下させる駆動素子を設け、過電流レベルで順次分割されたゲート電極の電位をしきい値以下にすることでドレイン電流を絞り込み過電流保護することが知られている(特許文献2参照)。
また、MOS構造のゲートを持つ半導体素子をチップに複数個形成し、各素子に形成されたゲートに時間差をつけたゲート信号を与えてオン領域を次第に増減させ、ターンオン・ターンオフ時のコレクタ電流、コレクタ・エミッタ間電圧の時間的変化率を緩和して、ターンオン時の電流波形の立ち上がりに生じる定格を超えるほどのピークや振動、ターンオフ時の電圧波形の立ち上がりに生じる定格を超えるほどのピークや振動を抑え、半導体装置の誤動作や破壊を防ぐことが知られている(特許文献3参照)。
【0004】
また、近年、パワー半導体デバイスは、大容量化が進み、電流容量が数100A〜数1000A程度のデバイスが発表されている。一般的に、1つのパワー半導体デバイスは、パワー半導体デバイスの基本構造となる基本セルが島状に複数個あるいはストライプ状に複数本繰り返し配置される構造となっており、大容量化はチップサイズを大きくしたりチップを複数個並列に接続することで対応している。
電力変換装置に適用されるパワー半導体デバイスには、サイリスタなどのターンオフ能力を持たない非自己消弧型デバイスとトランジスタなどのターンオフ能力を持つ自己消弧型デバイスに大別される。非自己消弧型デバイスは主電流を遮断するために転流回路が必要になることと、動作周波数が低いことから、インバータ回路などの電力変換装置では、通常、自己消弧型デバイスが用いられる。この自己消弧型デバイスで代表的なバイポーラ型デバイスとしては、バイポーラトランジスタ、IGBT(絶縁ゲート型バイポーラトランジスタ)、GTOサイリスタ(ゲートターンオフサイリスタ)およびMOSサイリスタなどがある。また、ユニポーラ型デバイスとしてはMOSFETがある。
【0005】
バイポーラ型の自己消弧型半導体デバイスではオン状態とオフ状態は、制御電極に電流あるいは電圧を与えることで、半導体内部のキャリアの量を増減させて実現される。半導体内部のキャリアの量が多い状態ではオン状態となり、少ない(ほとんど無い)状態ではオフ状態となる。尚、キャリアの量は半導体基板のドナーあるいはアクセプタ濃度と蓄積キャリアの量の和である。
オン状態からオフ状態の移行する期間がターンオフ時間であり、半導体内部に蓄積した過剰キャリアが掃き出される期間(排出される期間)である。
バイポーラ型の自己消弧型半導体デバイスがターンオフする場合、半導体内部に蓄積した過剰キャリアの排出と消滅に時間がかかるため、制御電極へのオフ信号入力からターンオフ完了までにタイムラグを生じる。このタイムラグがターンオフ時間である。
【0006】
このバイポーラ型の自己消弧型半導体デバイスに蓄積する過剰キャリアの量は導通面積が一定の場合には、通電電流依存性が小さく、大きな電流を流した場合に対して小さい電流を流した場合に蓄積する過剰キャリアの量は、その通電電流の比率では小さくならず、比較的大きな値となる。一方、この蓄積する過剰キャリアの量は通電面積(動作している活性領域の面積)に対しては比例する。
バイポーラ型の自己消弧型半導体デバイスを誘導負荷状態で、小電流状態で動作させた場合、前記のように、比較的多くの蓄積キャリアが半導体内部に存在し、この過剰キャリアが誘導負荷を通して小さな電流となって徐々に外部へ排出されるために、過剰キャリアの排出には時間がかかり、ターンオフ時間が長くなる。
【0007】
図5は、従来のIGBTチップの要部平面図であり、同図(a)は活性領域が分割されていない場合、同図(b)は活性領域が分割されている場合の図である。IGBTチップ51、61の大きさはいずれも21.5mm□である。
同図(a)において、図示しないゲート電極は活性領域42同一の大きさで活性領域42上に形成され、ゲートパッド53と接続部54で接続されている。
同図(b)において、活性領域66は16個の単位活性領域62に分割されて、各単位活性領域62の大きさは約2mm×約8mmである。また、図示しないゲート電極は単位活性領域62に合わせて16個に分割されて形成され、各単位活性領域62上に形成された図示しないゲート電極は接触部63でゲートランナー64と接続し、このゲートランナー64はゲートパッド65に接続する。
【0008】
図6は、誘導負荷状態におけるIGBTにターンオフ波形を示す図で、同図(a)はコレクタ電流が125Aの場合、同図(b)はコレクタ電流が6.2Aの場合の図である。これは、図5(b)のIGBTチップ61を収納した4.5kV級のIGBTのターンオフ波形である。図中のVbus は到達電圧、Rgは外部に接続するゲート抵抗、Tjは接合温度、Icはコレクタ電流、VCEはコレクタ電圧、VGEはゲート電圧である。
コレクタ電流が125Aの場合のターンオフタイムは2.5μsであるのに対して、コレクタ電流が6.2Aの場合のターンオフタイムは6μsと大幅に長くなる。このターンオフ波形は図5(a)のチップの場合も同じである。また小電流でのターンオフ時間が長くなる要因は前記した通りである。
【0009】
【特許文献1】
特開平9−260660号公報
【特許文献2】
特許第3126540号公報
【特許文献3】
特開平8−32064号公報
【0010】
【発明が解決しようとする課題】
インバータなどの電力変換装置では、上下アームが短絡しないようにするために、デッドタイムを設ける。このデットタイムは、上アームのデバイスがオフしてから下アームのデバイスがオンするまでの期間(または、下アームのデバイスがオフしてから上アームのデバイスがオンするまでの期間)のことであり、前記のターンオフ時間に若干の余裕時間を加えて設定される。そのためターンオフ時間が長くなると、デバイスの導通期間に対して休止期間の割合が大きくなる。特に、高周波動作ではこの割合が大きくなり、インバータの出力の高周波化を図る上で、また高調波成分の少ない正弦波を得る上で障害となる。
【0011】
この発明の目的は、前記の課題を解決して、誘導負荷状態で、小電流通電状態でもターンオフ時間を短くできるバイポーラ型で自己消弧型の半導体装置を提供することにある。
【0012】
【課題を解決するための手段】
前記の目的を達成するために、半導体基板に形成される大きさが異なる複数個の活性領域と、該複数個の活性領域の第1主面に一括形成される第1主電極と、各活性領域にそれぞれ形成される制御端子と、前記前記複数個の活性領域の第2主面に形成される第2主電極とを具備する構成とし、遮断時の主電流が大きいときは、大きな活性領域の制御端子に送られた制御信号で大きな活性領域を動作させ、該主電流が小さいときは、小さな活性領域の制御端子に送られた制御信号で小さな活性領域を動作させることで、主電流の大きさに応じて動作する活性領域の大きさを変化させる。
【0013】
また、半導体基板に形成される複数個の活性領域と、該複数個の活性領域の第1主面に一括形成される第1主電極と、各活性領域にそれぞれ形成される制御端子と、前記前記複数個の活性領域の第2主面に形成される第2主電極とを具備する構成とし、遮断時の主電流が大きいときは、各活性領域の制御端子に送られた制御信号で各活性領域を同時に動作させ、該主電流が小さいときは、一部の活性領域の制御端子に送られた制御信号で一部の活性領域を動作させることで、主電流の大きさに応じて動作させる活性領域の大きさを変化させる。
また、半導体基板に形成される2個の活性領域と、該2個の活性領域の第1主面に一括形成される第1主電極と、第1活性領域に形成される高いゲートしきい値電圧をもつ第1MOSゲート構造部と、第2活性領域に形成される低いゲートしきい値電圧をもつ第2MOSゲート構造部と、該第1MOSゲート構造部と第2MOSゲート構造部を接続して形成する共通の制御端子と、前記2個の活性領域の第2主面に形成される第2主電極とを具備する構成とし、遮断時の主電流が大きいときは、高いしきい値電圧より高いゲート電圧を前記制御端子に印加して第1および第2活性領域を同時に動作させ、該主電流が小さいときは、低いゲートしきい値電圧と高いゲートしきい値電圧の中間のゲート電圧を前記制御端子に印加して第2活性領域を動作させることで、主電流の大きさに応じて動作させる活性領域の大きさを変化させる。
【0014】
また、半導体基板に形成される第1番目から第n番目のn個の活性領域と、該n個の活性領域の第1主面側に一括形成される第1主電極と、第1番目の活性領域に形成される最大電圧である第1番目のゲートしきい値電圧をもつ第1MOSゲート構造部と、第n番目の活性領域に形成される最小電圧である第n番目のゲートしきい値電圧をもつ第nMOSゲート構造部と、その中間の第m番目の活性領域に形成される中間の電圧である第m番目のゲートしきい値電圧をもつ第mMOSゲート構造部と、前記第1MOSゲート構造部から第nMOSゲート構造部と接続する共通の制御端子と、前記n個の活性領域の第2主面側に形成される第2主電極とを具備する構成とし、遮断時の主電流が大きいときは、第1番目のゲートしきい値電圧より高いゲート電圧を前記制御端子に印加して第1から第n番目の活性領域を同時に動作させ、前記主電流が小さいときは、第n番目のゲートしきい値電圧と該ゲートしきい値電圧より次に高い第n−1番目のゲートしきい値電圧の間の大きさのゲート電圧を前記制御端子に印加して、第n番目の活性領域を動作させ、前記主電流が中間の大きさでm番目の場合は、第m番目のゲートしきい値電圧と該ゲートしきい値電圧より次に高い第m−1番目のゲートしきい値電圧の間の大きさのゲート電圧を前記制御端子に印加して、第m番目から第n番目の活性領域を動作させることで、主電流の大きさに応じて動作する活性領域の大きさを変化させることで、主電流の大きさに応じて動作させる活性領域の大きさを変化させる。
【0015】
また、前記半導体装置が、バイポーラ型の自己消弧半導体装置であるとよい。また、前記バイポーラ型の自己消弧型半導体装置が、バイポーラトランジスタ、絶縁ゲート型バイポーラトランジスタ、ゲートターンオフサイリスタおよびMOSサイリスタのいずれか一つであるとよい。
また、複数個のバイポーラ型の自己消弧型半導体チップが並列接続されて同一パッケージに収納された半導体装置において、各チップに形成される制御端子に個別の制御信号を送り、遮断時の主電流の大きさに応じて動作させるチップ数を切替え、該主電流が大きいときは、動作させるチップ数を多くし、該主電流が小さいときは、動作させるチップ数を少なくする。
【0016】
また、前記バイポーラ型の自己消弧型半導体チップが、バイポーラトランジスタチップ、絶縁ゲート型バイポーラトランジスタチップ、ゲートターンオフサイリスタチップおよびMOSサイリスタチップのいずれか一つであるとよい。
〔作用〕
デバイスの活性領域を分割し、分割した活性領域を個別に制御する。ターンオフ時の主電流が小さい場合、動作する活性領域面積を小さくすれば、蓄積しているキャリアの量が小さくなり、ターンオフの際に掃き出す必要のあるキャリア量を少なくできる。その結果、主電流が小電流の場合でもターンオフ時間を短くすることができる。
【0017】
【発明の実施の形態】
〔実施例1〕
図1は、この発明の第1実施例の半導体装置の要部平面図である。この図は、IGBTのチップの平面図であり、このチップを複数個平型パッケージに収納すると加圧接触型の平型IGBTとなる。
IGBTチップ1の大きさは21.5mm□であり、単位活性領域2は多数のセルで構成され、各セルの構造は、図示しないが、良く知られている単位エミッタ領域、単位ゲート電極、単位ウエル領域、単位ドリフト領域および単位コレクタ領域で構成される。つまり、セルとはIGBTを1個のウエル領域(単位ウエル領域)で半導体基板の方向に分割した領域をいう。このセルが多数集合して1個の単位活性領域を形成する。さらに、この単位活性領域が1個または複数個集まって動作する活性領域となる。また、活性領域のエミッタ領域上にはエミッタ電極、コレクタ領域上にはコレクタ電極が形成される。
【0018】
図1では、活性領域は16個の単位活性領域2で構成され、各単位活性領域2の大きさは2mm×8mm程度である。15個の単位活性領域2で大きな活性領域7を構成し、1個の単位活性領域2で小さな活性領域8を構成する。15個の各単位活性領域2の上部に形成される図示しないポリシリコンのゲート電極は接続部3でアルミニウムのゲートランナー4と接続し、このゲートランナー4はアルミニウムのゲートパッド5(制御端子)と接続する。また、残る1個の単位活性領域2の上部に形成される図示しないゲート電極は接続部3でアルミニウムのゲートパッド6(制御端子)と接続し、ゲートパッド6はゲートパッド5と電気的には絶縁されている。また、大きな活性領域7上と小さな活性領域8上に図示しない共通のエミッタ電極がアルミニウムで形成される。
【0019】
図2は、誘導負荷状態におけるIGBTのターンオフ波形を示す図で、同図(a)はコレクタ電流が125Aの場合、同図(b)はコレクタ電流が6.2Aの場合の図である。これは、図1のIGBTチップ1を収納した4.5kV級のIGBTのターンオフ波形である。前記したように、図中のVbus は到達電圧、Rgは外部に接続するゲート抵抗、Tjは接合温度、Icはコレクタ電流、VCEはコレクタ電圧、VGEはゲート電圧である。
コレクタ電流が6.2Aの場合は、ゲートパッド6のみにゲート電圧を印加して小さな活性領域8(1個の単位活性領域2)を動作させる。コレクタ電流が125Aの場合は、ゲートパッド5とゲートパッド6の双方に同時にゲート電圧を印加して、16個全ての単位活性領域2(大きな活性領域7と小さな活性領域8)を同時に動作させる。
【0020】
コレクタ電流が125Aの場合は、動作する活性領域7、8は16個の単位活性領域2であり、その面積は従来のIGBTと同一であるため、ターンオフ時に掃き出されるキャリア量も従来のIGBTと同一になり、ターンオフ波形は同じになる。従って、ターンオフ時間も従来のIGBTと同じであり2.5μsとなる。尚、ゲートパッド5のみの動作させた場合、大きな活性領域7(15個の単位活性領域2)が動作し、動作する活性領域の面積が16個の場合とほぼ同じためにターンオフ時間は殆ど変わらない。勿論、ゲートパッド5のみにゲート電圧を印加して15個の単位活性領域2を動作させても、動作する活性領域の面積が1/16減少するだけであるのでターンオフ時間はほとんど変わらない。
【0021】
一方、6.2Aのターンオフの場合は、ゲートパッド6のみにゲート電圧を印加し、小さな活性領域8(1個の単位活性領域2)を動作させるために、動作面積が小さくなり、ターンオフ時に掃き出されるキャリア量が従来のIGBTより大幅に少なくなる。従って、ターンオフ時間は3.5μsと従来のIGBTの半分程度に短縮される。
このように、コレクタ電流が小さい場合に、動作させる活性領域の面積を小さくし、ターンオフ時に掃き出されるキャリア量を少なくすることで、ターンオフ時間の短縮を図ることができる。
【0022】
前記したことは、バイポーラトランジスタやGTOサイリスタ、MOS(電圧駆動)型サイリスタなどのバイポーラ型の自己消弧半導体装置の場合は同様の効果が得られる。尚、本例において、大小2つの活性領域の比を単位活性領域の数で16:1としたが、小さな活性領域の面積では必要な電流容量に応じて、適宜変更すればよく、単位活性領域の使用個数を変更してもよい。
〔実施例2〕
図3は、この発明の第2実施例の半導体装置の要部平面図である。これは複数個のIGBTチップ11を並列接続して使用するIGBTモジュール10に適用した場合である。
【0023】
絶縁基板18上に形成した銅パターン19上にIGBTチップ11を固着し、銅パターン20上にダイオードチップ14を固着する。銅パターン19とダイオードチップ14のカソード電極15をボッディングワイヤで接続し、銅パターン20とIGBTチップ11のエミッタ電極12をボンディングワイヤ16で接続する。銅パターン19と絶縁膜21で絶縁された制御外部導出端子22と3個のIGBTチップ11のゲートパッド13とボンディングワイヤ17で接続し、制御外部導出端子23と1個のIGBTチップ11とボンディングワイヤ17で接続する。このように複数個のIGBTチップとダイオードチップ14が固着した絶縁基板18を図示しない樹脂パッケージに収納してIGBTモジュール10を形成する。
【0024】
前記したように、同じ動作面積を持つ4個のIGBTチップ11を使用し、うち1個のIGBTチップのみ個別に制御可能な構成し、ターンオフする電流が小さい場合は、制御外部導出端子23と接続する1個のIGBTのゲートパッド13にゲート電圧を印加して1個のIGBTチップ11を動作させる。
ターンオフする電流が大きい通常電流の場合は制御外部導出端子22、21の両方と接続する4個のIGBTチップ11のゲートパッド13にゲート電圧を印加して4個のIGBTチップ11を動作させるか、外部導出端子22に接続する3個のIGBTチップ11のゲートパッド13にゲート電圧を印加して3個のIGBTチップ11を動作させる。
【0025】
このように、ターンオフ時のコレクタ電流が小さい場合に、動作させるIGBTチップ11の個数を減じて、動作面積を小さくすることで、ターンオフ時間を短縮できることは第1実施例と同じである。
また、ここでは同一面積のIGBTチップで構成したが、面積の異なるIGBTチップで構成しても構わない。また、モジュールでなく、平型パッケージにIGBTチップを収納して平型IGBTとしても構わない。
また、IGBTチップの代わりに、パワーバイポーラトランジスタチップ、GTOサイリスタチップおよびMOSサイリスタチップなどのバイポーラ型の自己消弧型半導体チップを収納しても同様の効果が得られることは勿論である。
〔実施例3〕
図4は、この発明の第3実施例の半導体装置の要部平面図である。図1と同様に活性領域を16個の単位活性領域32に分割し、15個の単位活性領域32で構成される大きな活性領域37のゲートしきい値電圧を高くし、1個の単位活性領域32で構成される小さな活性領域38のゲートしきい値電圧を低くする。
【0026】
ゲートしきい値電圧の調整法としてはゲート絶縁膜の膜厚を変える場合、チャネル形成部の不純物濃度を変える場合など種々あるが、ここではゲート絶縁膜の膜厚を厚くして高いしきい値電圧にし、薄くして低いしきい値電圧にした。
IGBTチップ31を動作させるとき、ゲートパッド35に印加されるゲート電圧を高いゲートしきい値電圧と低いゲートしきい値の間に設定することで、ゲートしきい値の低い小さな活性領域38のみ動作させ、ゲート電圧を高いゲートしきい値電圧より高く設定することで大きな活性領域37と小さな活性領域38を同時に動作させる。
【0027】
ターンオフ時のコレクタ電流が小さい場合は前者のゲート電圧に設定し、ターンオフ時のコレクタ電流が大きい場合には、後者のゲート電圧に設定することで、第1実施例と同様の効果を得ることができる。
尚、この実施例では、ゲートしきい値電圧を2レベルに設定したが、さらにレベル数を増やして、コレクタ電流が小さくなるにつれて、順次動作する活性領域を減じても同様の効果が得られることは勿論である。また、図中の33は接続部、34はゲートランナーである。
上記の各実施例において、ターンオフ時のコレクタ電流の大小によってゲート信号を変更しているが、例えば、直前2回のターンオフ時のピーク電流を検出し、電流が減少する傾向を確認し、次回のターンオン時の所定の小さな活性領域のみターンオンさせるべくゲート信号を切り換えるとよい。
【0028】
【発明の効果】
この発明によれば、ターンオフ時のコレクタ電流が大きい場合は、半導体装置の動作する活性領域の面積を大きくし、小さい場合は、動作する活性領域の面積を小さくすることで、コレクタ電流が小さい場合の誘導負荷状態でのターンオフ時間を大幅に短縮することができる。
この半導体装置をインバータなどの電力変換装置に使用することで、誘導負荷状態で微小な負荷電流状態でのデットタイムを短縮化できて、変換装置の動作周波数の高周波化と出力波形の高調波の少ない正弦波化を図ることができる。
【図面の簡単な説明】
【図1】この発明の第1実施例の半導体装置の要部平面図
【図2】誘導負荷状態におけるIGBTのターンオフ波形を示す図で、(a)はコレクタ電流が125Aの場合、(b)はコレクタ電流が6.2Aの場合の図
【図3】この発明の第2実施例の半導体装置の要部平面図
【図4】この発明の第3実施例の半導体装置の要部平面図
【図5】従来のIGBTチップの要部平面図であり、(a)は活性領域が分割されていない場合、(b)は活性領域が分割されている場合の図
【図6】誘導負荷状態におけるIGBTにターンオフ波形を示す図で、(a)はコレクタ電流が125Aの場合、(b)はコレクタ電流が6.2Aの場合の図
【符号の説明】
1、11、31 IGBTチップ
2、32 単位活性領域
3、33 接続部
4、34 ゲートランナー
5、6、35 ゲートパッド
7、37 大きい活性領域
8、38 小さい活性領域
10 IGBTモジュール
12 エミッタ電極
13 ゲートパッド
14 ダイオードチップ
15 カソード電極
16、17 ボンディングワイヤ
18 絶縁基板
19、20 銅パターン
21 絶縁膜
22、23 制御外部導出端子
[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a bipolar self-extinguishing semiconductor device that operates in a bipolar mode, such as a bipolar transistor or IGBT (insulated gate bipolar transistor) used in a power converter.
[0002]
[Prior art]
In a MOSFET used for a gate array, a basic cell for flowing a relatively small current for signals and a basic cell for flowing a large current used for an output unit are usually formed separately. Therefore, the usage rate of basic cells in the gate array and the degree of freedom in circuit design are reduced. In order to solve this problem, in the MOSFET constituting the basic cell, the gate electrode is divided into a plurality of parts, and the voltage is selectively applied to the individual electrodes, so that the channel length is changed to have a plurality of types of operation states. By doing so, it is known that the usage rate of basic cells in the gate array is improved and the degree of freedom in circuit design is secured (see Patent Document 1).
[0003]
In a MOSFET with a built-in overcurrent protection function, the gate electrode of the MOSFET to be detected is divided into several parts in the gate width direction (perpendicular to the channel length), and the potential of the divided gate electrode is lowered below the threshold value. It is known that a drive element is provided and the drain current is narrowed down and overcurrent protection is performed by making the potential of the gate electrode sequentially divided at the overcurrent level equal to or less than a threshold value (see Patent Document 2).
Further, a plurality of semiconductor elements having MOS structure gates are formed on a chip, and a gate signal with a time difference is given to the gates formed in each element to gradually increase / decrease the ON region, collector current at turn-on / turn-off, Relaxing the rate of change of collector-emitter voltage over time, peaks and vibrations exceeding the rating generated at the rise of the current waveform at turn-on, peaks and vibrations exceeding the rating generated at the rise of the voltage waveform at turn-off Is known to prevent malfunction and destruction of the semiconductor device (see Patent Document 3).
[0004]
In recent years, power semiconductor devices have been increased in capacity, and devices having a current capacity of about several hundreds of A to several thousand A have been announced. In general, one power semiconductor device has a structure in which a plurality of basic cells, which are the basic structure of a power semiconductor device, are repeatedly arranged in an island shape or a plurality of stripe shapes. This can be done by increasing the size or connecting multiple chips in parallel.
Power semiconductor devices applied to power converters are roughly classified into non-self-extinguishing devices such as thyristors that do not have turn-off capability and self-extinguishing devices such as transistors that have turn-off capability. Since a non-self-extinguishing type device requires a commutation circuit to cut off the main current and the operating frequency is low, a self-extinguishing type device is usually used in a power converter such as an inverter circuit. . Typical bipolar devices in this self-extinguishing device include bipolar transistors, IGBTs (insulated gate bipolar transistors), GTO thyristors (gate turn-off thyristors), and MOS thyristors. A unipolar device is a MOSFET.
[0005]
In a bipolar self-extinguishing semiconductor device, the on state and the off state are realized by increasing or decreasing the amount of carriers in the semiconductor by applying a current or voltage to the control electrode. When the amount of carriers inside the semiconductor is large, the semiconductor device is turned on, and when it is small (almost no), the semiconductor device is turned off. The amount of carriers is the sum of the donor or acceptor concentration of the semiconductor substrate and the amount of accumulated carriers.
A period during which the ON state transitions to the OFF state is a turn-off time, and a period during which excess carriers accumulated in the semiconductor are swept out (a period during which the carriers are discharged).
When a bipolar self-extinguishing semiconductor device is turned off, it takes time to discharge and disappear excess carriers accumulated in the semiconductor, so that there is a time lag between the turn-off signal input to the control electrode and the turn-off completion. This time lag is the turn-off time.
[0006]
The amount of excess carriers stored in this bipolar self-extinguishing semiconductor device is less dependent on the energizing current when the conduction area is constant, and is smaller when a small current is applied than when a large current is applied. The amount of excess carriers to be accumulated does not decrease with the ratio of the energization current, but is a relatively large value. On the other hand, the amount of excess carriers accumulated is proportional to the current-carrying area (the area of the active region that is operating).
When a bipolar self-extinguishing semiconductor device is operated in an inductive load state and in a small current state, as described above, a relatively large number of accumulated carriers exist in the semiconductor, and this excess carrier is small through the inductive load. Since the current is gradually discharged to the outside, it takes time to discharge excess carriers, and the turn-off time becomes long.
[0007]
FIG. 5 is a plan view of a main part of a conventional IGBT chip. FIG. 5A shows a case where the active region is not divided, and FIG. 5B shows a case where the active region is divided. The sizes of the IGBT chips 51 and 61 are both 21.5 mm □.
In FIG. 2A, a gate electrode (not shown) is formed on the active region 42 with the same size as the active region 42 and is connected to the gate pad 53 through a connection portion 54.
In FIG. 6B, the active region 66 is divided into 16 unit active regions 62, and the size of each unit active region 62 is about 2 mm × about 8 mm. Further, a gate electrode (not shown) is divided into 16 pieces corresponding to the unit active region 62, and the gate electrode (not shown) formed on each unit active region 62 is connected to the gate runner 64 at the contact portion 63. The gate runner 64 is connected to the gate pad 65.
[0008]
6A and 6B are diagrams showing a turn-off waveform in the IGBT in an inductive load state. FIG. 6A shows a case where the collector current is 125 A, and FIG. 6B shows a case where the collector current is 6.2 A. This is a turn-off waveform of a 4.5 kV class IGBT containing the IGBT chip 61 of FIG. In the figure, Vbus is an ultimate voltage, Rg is a gate resistance connected to the outside, Tj is a junction temperature, Ic is a collector current, VCE is a collector voltage, and VGE is a gate voltage.
When the collector current is 125 A, the turn-off time is 2.5 μs, whereas when the collector current is 6.2 A, the turn-off time is significantly increased to 6 μs. This turn-off waveform is the same for the chip of FIG. Further, the factors that increase the turn-off time at a small current are as described above.
[0009]
[Patent Document 1]
JP-A-9-260660 [Patent Document 2]
Japanese Patent No. 3126540 [Patent Document 3]
Japanese Patent Laid-Open No. 8-32064
[Problems to be solved by the invention]
In a power conversion device such as an inverter, a dead time is provided in order to prevent the upper and lower arms from being short-circuited. This dead time is the period from when the upper arm device is turned off to when the lower arm device is turned on (or the period from when the lower arm device is turned off to when the upper arm device is turned on). Yes, it is set by adding a slight margin to the turn-off time. Therefore, when the turn-off time becomes longer, the ratio of the rest period to the conduction period of the device increases. In particular, this ratio increases in high-frequency operation, which is an obstacle to increasing the frequency of the inverter output and obtaining a sine wave with less harmonic components.
[0011]
An object of the present invention is to provide a bipolar self-extinguishing semiconductor device capable of solving the above-described problems and shortening the turn-off time even in an inductive load state and in a small current energizing state.
[0012]
[Means for Solving the Problems]
To achieve the above object, a plurality of active regions having different sizes formed on a semiconductor substrate, a first main electrode formed collectively on a first main surface of the plurality of active regions, and each active region A control terminal formed in each region and a second main electrode formed on the second main surface of the plurality of active regions, and a large active region when the main current at the time of interruption is large The large active region is operated by the control signal sent to the control terminal of the main current, and when the main current is small, the small active region is operated by the control signal sent to the control terminal of the small active region. The size of the active region that operates according to the size is changed.
[0013]
A plurality of active regions formed on the semiconductor substrate; a first main electrode formed collectively on a first main surface of the plurality of active regions; a control terminal formed on each active region; And a second main electrode formed on the second main surface of the plurality of active regions, and when the main current at the time of interruption is large, each control signal sent to the control terminal of each active region When the active region is operated simultaneously and the main current is small, the active region is operated according to the magnitude of the main current by operating the active region with a control signal sent to the control terminal of the active region. The size of the active region to be changed is changed.
Also, two active regions formed in the semiconductor substrate, a first main electrode formed collectively on the first main surface of the two active regions, and a high gate threshold value formed in the first active region A first MOS gate structure having a voltage, a second MOS gate structure having a low gate threshold voltage formed in the second active region, and a connection between the first MOS gate structure and the second MOS gate structure And a second main electrode formed on the second main surface of the two active regions, and when the main current at the time of interruption is large, it is higher than a high threshold voltage A gate voltage is applied to the control terminal to simultaneously operate the first and second active regions, and when the main current is small, an intermediate gate voltage between a low gate threshold voltage and a high gate threshold voltage is Second active region applied to control terminal By operating, changing the size of the active region to be operated in accordance with the magnitude of the main current.
[0014]
In addition, the first to n-th n active regions formed on the semiconductor substrate, a first main electrode collectively formed on the first main surface side of the n active regions, and a first A first MOS gate structure having a first gate threshold voltage which is the maximum voltage formed in the active region; and an nth gate threshold which is a minimum voltage formed in the nth active region. An n-th MOS gate structure having a voltage, an m-th MOS gate structure having an m-th gate threshold voltage, which is an intermediate voltage formed in the m-th active region in the middle, and the first MOS gate The structure includes a common control terminal connected to the nth MOS gate structure from the structure, and a second main electrode formed on the second main surface side of the n active regions, and the main current at the time of interruption is When larger than the first gate threshold voltage When a main gate voltage is applied to the control terminal to simultaneously operate the first to nth active regions, and the main current is small, the nth gate threshold voltage and the gate threshold voltage Next, a gate voltage having a magnitude between the next n-1th gate threshold voltage is applied to the control terminal to operate the nth active region, and the main current has an intermediate magnitude. In the m-th case, a gate voltage having a magnitude between the m-th gate threshold voltage and the (m-1) -th gate threshold voltage that is higher than the gate threshold voltage is applied to the control terminal. Applying and operating the m-th to n-th active regions, changing the size of the active region that operates according to the size of the main current, and operating according to the size of the main current The size of the active region to be changed is changed.
[0015]
The semiconductor device may be a bipolar self-extinguishing semiconductor device. The bipolar self-extinguishing semiconductor device may be any one of a bipolar transistor, an insulated gate bipolar transistor, a gate turn-off thyristor, and a MOS thyristor.
Also, in a semiconductor device in which a plurality of bipolar self-extinguishing semiconductor chips are connected in parallel and housed in the same package, a separate control signal is sent to the control terminal formed on each chip, and the main current at the time of interruption When the main current is large, the number of chips to be operated is increased, and when the main current is small, the number of chips to be operated is decreased.
[0016]
The bipolar self-extinguishing semiconductor chip may be any one of a bipolar transistor chip, an insulated gate bipolar transistor chip, a gate turn-off thyristor chip, and a MOS thyristor chip.
[Action]
The active area of the device is divided, and the divided active areas are individually controlled. When the main current at the time of turn-off is small, if the area of the active region to be operated is reduced, the amount of accumulated carriers is reduced, and the amount of carriers that need to be swept out at the time of turn-off can be reduced. As a result, the turn-off time can be shortened even when the main current is small.
[0017]
DETAILED DESCRIPTION OF THE INVENTION
[Example 1]
FIG. 1 is a plan view of an essential part of a semiconductor device according to a first embodiment of the present invention. This figure is a plan view of an IGBT chip. When a plurality of chips are stored in a flat package, a pressure contact type flat IGBT is obtained.
The size of the IGBT chip 1 is 21.5 mm □, the unit active region 2 is composed of a large number of cells, and the structure of each cell is not shown, but the well-known unit emitter region, unit gate electrode, unit It consists of a well region, a unit drift region and a unit collector region. That is, the cell is a region obtained by dividing the IGBT in the direction of the semiconductor substrate by one well region (unit well region). A large number of these cells aggregate to form one unit active region. Further, one or a plurality of unit active regions become active regions that operate. An emitter electrode is formed on the emitter region of the active region, and a collector electrode is formed on the collector region.
[0018]
In FIG. 1, the active region is composed of 16 unit active regions 2, and the size of each unit active region 2 is about 2 mm × 8 mm. 15 unit active regions 2 constitute a large active region 7, and one unit active region 2 constitutes a small active region 8. A polysilicon gate electrode (not shown) formed on each of the 15 unit active regions 2 is connected to an aluminum gate runner 4 at a connection portion 3. The gate runner 4 is connected to an aluminum gate pad 5 (control terminal). Connecting. Further, a gate electrode (not shown) formed on the remaining one unit active region 2 is connected to an aluminum gate pad 6 (control terminal) at the connection portion 3, and the gate pad 6 is electrically connected to the gate pad 5. Insulated. A common emitter electrode (not shown) is formed of aluminum on the large active region 7 and the small active region 8.
[0019]
2A and 2B are diagrams showing an IGBT turn-off waveform in an inductive load state. FIG. 2A shows a case where the collector current is 125 A, and FIG. 2B shows a case where the collector current is 6.2 A. This is a turn-off waveform of a 4.5 kV class IGBT containing the IGBT chip 1 of FIG. As described above, Vbus in the figure is an ultimate voltage, Rg is a gate resistance connected to the outside, Tj is a junction temperature, Ic is a collector current, VCE is a collector voltage, and VGE is a gate voltage.
When the collector current is 6.2 A, the gate voltage is applied only to the gate pad 6 to operate the small active region 8 (one unit active region 2). When the collector current is 125 A, the gate voltage is applied to both the gate pad 5 and the gate pad 6 at the same time, and all 16 unit active regions 2 (the large active region 7 and the small active region 8) are operated simultaneously.
[0020]
When the collector current is 125 A, the active regions 7 and 8 that operate are the 16 unit active regions 2 and the area thereof is the same as that of the conventional IGBT. The turn-off waveforms are the same. Therefore, the turn-off time is the same as that of the conventional IGBT, which is 2.5 μs. When only the gate pad 5 is operated, the large active region 7 (15 unit active regions 2) operates, and the turn-off time is almost the same because the area of the active region to operate is almost the same as 16. Absent. Of course, even if the 15 unit active regions 2 are operated by applying a gate voltage only to the gate pad 5, the turn-off time is hardly changed because the area of the active region to be operated is only reduced by 1/16.
[0021]
On the other hand, in the case of turn-off of 6.2 A, a gate voltage is applied only to the gate pad 6 to operate a small active region 8 (one unit active region 2). The amount of carriers to be issued is significantly smaller than that of the conventional IGBT. Therefore, the turn-off time is reduced to 3.5 μs, which is about half that of the conventional IGBT.
As described above, when the collector current is small, the area of the active region to be operated is reduced, and the amount of carriers swept out at the time of turn-off is reduced, so that the turn-off time can be shortened.
[0022]
As described above, the same effect can be obtained in the case of bipolar self-extinguishing semiconductor devices such as bipolar transistors, GTO thyristors, and MOS (voltage driven) thyristors. In this example, the ratio of the two large and small active regions is 16: 1 in terms of the number of unit active regions. However, the area of the small active region may be appropriately changed according to the required current capacity. The number used may be changed.
[Example 2]
FIG. 3 is a plan view of an essential part of a semiconductor device according to the second embodiment of the present invention. This is a case where the present invention is applied to an IGBT module 10 in which a plurality of IGBT chips 11 are connected in parallel.
[0023]
The IGBT chip 11 is fixed on the copper pattern 19 formed on the insulating substrate 18, and the diode chip 14 is fixed on the copper pattern 20. The copper pattern 19 and the cathode electrode 15 of the diode chip 14 are connected by a boarding wire, and the copper pattern 20 and the emitter electrode 12 of the IGBT chip 11 are connected by a bonding wire 16. The control external lead terminal 22 insulated by the copper pattern 19 and the insulating film 21 is connected to the gate pad 13 of the three IGBT chips 11 and the bonding wire 17, and the control external lead terminal 23, the single IGBT chip 11 and the bonding wire are connected. 17 to connect. Thus, the IGBT module 10 is formed by housing the insulating substrate 18 to which the plurality of IGBT chips and the diode chip 14 are fixed in a resin package (not shown).
[0024]
As described above, four IGBT chips 11 having the same operation area are used, and only one IGBT chip is individually controllable. When the current to be turned off is small, the control external lead-out terminal 23 is connected. One IGBT chip 11 is operated by applying a gate voltage to the gate pad 13 of one IGBT.
In the case of a normal current with a large turn-off current, the gate voltage is applied to the gate pads 13 of the four IGBT chips 11 connected to both of the control external lead-out terminals 22 and 21, and the four IGBT chips 11 are operated. The gate voltages are applied to the gate pads 13 of the three IGBT chips 11 connected to the external lead-out terminals 22 to operate the three IGBT chips 11.
[0025]
In this way, when the collector current at the time of turn-off is small, the turn-off time can be shortened by reducing the number of IGBT chips 11 to be operated and reducing the operation area, as in the first embodiment.
Moreover, although it comprised with the IGBT chip | tip of the same area here, you may comprise with an IGBT chip | tip with a different area. Further, the IGBT chip may be housed in a flat package instead of a module to form a flat IGBT.
Of course, the same effect can be obtained by storing a bipolar self-extinguishing semiconductor chip such as a power bipolar transistor chip, a GTO thyristor chip, and a MOS thyristor chip instead of the IGBT chip.
Example 3
FIG. 4 is a plan view of the main part of the semiconductor device according to the third embodiment of the present invention. As in FIG. 1, the active region is divided into 16 unit active regions 32, the gate threshold voltage of a large active region 37 composed of 15 unit active regions 32 is increased, and one unit active region is formed. The gate threshold voltage of the small active region 38 composed of 32 is lowered.
[0026]
There are various methods for adjusting the gate threshold voltage, such as changing the thickness of the gate insulating film and changing the impurity concentration of the channel forming portion. Here, the gate threshold voltage is increased to increase the threshold value. The voltage was reduced to a lower threshold voltage.
When the IGBT chip 31 is operated, the gate voltage applied to the gate pad 35 is set between a high gate threshold voltage and a low gate threshold, so that only the small active region 38 having a low gate threshold is operated. The large active region 37 and the small active region 38 are simultaneously operated by setting the gate voltage higher than the high gate threshold voltage.
[0027]
When the collector current at turn-off is small, the former gate voltage is set, and when the collector current at turn-off is large, the latter gate voltage is set to obtain the same effect as in the first embodiment. it can.
In this embodiment, the gate threshold voltage is set to 2 levels. However, as the number of levels is further increased and the collector current is reduced, the same effect can be obtained even if the active regions that are sequentially operated are reduced. Of course. In the figure, 33 is a connecting portion, and 34 is a gate runner.
In each of the above-described embodiments, the gate signal is changed depending on the magnitude of the collector current at the time of turn-off. The gate signal may be switched so as to turn on only a predetermined small active region at the time of turn-on.
[0028]
【The invention's effect】
According to the present invention, when the collector current at turn-off is large, the area of the active region in which the semiconductor device operates is increased, and when the collector current is small, the area of the active region in operation is decreased to reduce the collector current. The turn-off time in the inductive load state can be greatly shortened.
By using this semiconductor device for power converters such as inverters, dead time in a minute load current state can be shortened in an inductive load state, and the operating frequency of the converter device can be increased and the output waveform harmonics can be reduced. Fewer sine waves can be achieved.
[Brief description of the drawings]
FIG. 1 is a plan view of a principal part of a semiconductor device according to a first embodiment of the present invention. FIG. 2 is a diagram showing a turn-off waveform of an IGBT in an inductive load state. FIG. 3 is a plan view of the main part of the semiconductor device according to the second embodiment of the present invention. FIG. 4 is a plan view of the main part of the semiconductor device according to the third embodiment of the present invention. 5A and 5B are plan views of a main part of a conventional IGBT chip, in which FIG. 6A is a diagram when the active region is not divided, and FIG. 6B is a diagram when the active region is divided. The figure which shows the turn-off waveform in IGBT, (a) when collector current is 125A, (b) when collector current is 6.2A
1, 11, 31 IGBT chip 2, 32 Unit active region 3, 33 Connection portion 4, 34 Gate runner 5, 6, 35 Gate pad 7, 37 Large active region 8, 38 Small active region 10 IGBT module 12 Emitter electrode 13 Gate Pad 14 Diode chip 15 Cathode electrode 16, 17 Bonding wire 18 Insulating substrate 19, 20 Copper pattern 21 Insulating film 22, 23 Control external lead-out terminal

Claims (8)

半導体基板に形成される大きさが異なる複数個の活性領域と、該複数個の活性領域の第1主面に一括形成される第1主電極と、各活性領域にそれぞれ形成される制御端子と、前記前記複数個の活性領域の第2主面に形成される第2主電極とを具備し、遮断時の主電流が大きいときは、大きな活性領域の制御端子に送られた制御信号で大きな活性領域を動作させ、該主電流が小さいときは、小さな活性領域の制御端子に送られた制御信号で小さな活性領域を動作させることで、主電流の大きさに応じて動作する活性領域の大きさを変化させることを特徴とする半導体装置。A plurality of active regions of different sizes formed on a semiconductor substrate; a first main electrode formed in a lump on a first main surface of the plurality of active regions; and a control terminal formed in each active region And a second main electrode formed on the second main surface of the plurality of active regions, and when the main current at the time of interruption is large, a large control signal is sent to the control terminal of the large active region When the active region is operated and the main current is small, the small active region is operated by the control signal sent to the control terminal of the small active region. A semiconductor device characterized by changing the thickness. 半導体基板に形成される複数個の活性領域と、該複数個の活性領域の第1主面に一括形成される第1主電極と、各活性領域にそれぞれ形成される制御端子と、前記前記複数個の活性領域の第2主面に形成される第2主電極とを具備し、遮断時の主電流が大きいときは、各活性領域の制御端子に送られた制御信号で各活性領域を同時に動作させ、該主電流が小さいときは、一部の活性領域の制御端子に送られた制御信号で一部の活性領域を動作させることで、主電流の大きさに応じて動作させる活性領域の大きさを変化させることを特徴とする半導体装置。A plurality of active regions formed in a semiconductor substrate; a first main electrode formed collectively on a first main surface of the plurality of active regions; a control terminal formed in each active region; A second main electrode formed on the second main surface of each active region, and when the main current at the time of interruption is large, each active region is simultaneously controlled by a control signal sent to the control terminal of each active region When the main current is small, the active region is operated according to the magnitude of the main current by operating a part of the active region with a control signal sent to the control terminal of the part of the active region. A semiconductor device characterized in that the size is changed. 半導体基板に形成される2個の活性領域と、該2個の活性領域の第1主面に一括形成される第1主電極と、第1活性領域に形成される高いゲートしきい値電圧をもつ第1MOSゲート構造部と、第2活性領域に形成される低いゲートしきい値電圧をもつ第2MOSゲート構造部と、該第1MOSゲート構造部と第2MOSゲート構造部とを接続して形成する共通の制御端子と、前記2個の活性領域の第2主面に形成される第2主電極とを具備し、遮断時の主電流が大きいときは、前記第1MOSゲート構造部のしきい値電圧より高いゲート電圧を前記制御端子に印加して第1および第2活性領域を同時に動作させ、該主電流が小さいときは、前記第1MOSゲート構造部のしきい値電圧より低く、前記第2MOSゲート構造部のしきい値電圧より高いゲート電圧を前記制御端子に印加して第2活性領域を動作させることで、主電流の大きさに応じて動作させる活性領域の大きさを変化させることを特徴とする半導体装置。Two active regions formed in a semiconductor substrate, a first main electrode formed collectively on the first main surface of the two active regions, and a high gate threshold voltage formed in the first active region A first MOS gate structure having a low gate threshold voltage formed in the second active region, and the first MOS gate structure and the second MOS gate structure are connected to each other. A common control terminal and a second main electrode formed on the second main surface of the two active regions, and when the main current at the time of interruption is large, the threshold value of the first MOS gate structure A gate voltage higher than the voltage is applied to the control terminal to simultaneously operate the first and second active regions. When the main current is small, the second MOS is lower than the threshold voltage of the first MOS gate structure. Threshold voltage of gate structure Ri high gate voltages by operating the second active region is applied to the control terminal, the semiconductor device characterized by changing the size of the active region to be operated in accordance with the magnitude of the main current. 半導体基板に形成される第1番目から第n番目のn個の活性領域と、該n個の活性領域の第1主面側に一括形成される第1主電極と、第1番目の活性領域に形成される最大電圧である第1番目のゲートしきい値電圧をもつ第1MOSゲート構造部と、第n番目の活性領域に形成される最小電圧である第n番目のゲートしきい値電圧をもつ第nMOSゲート構造部と、その中間の第m番目の活性領域に形成される中間の電圧である第m番目のゲートしきい値電圧をもつ第mMOSゲート構造部と、前記第1MOSゲート構造部から第nMOSゲート構造部と接続する共通の制御端子と、前記n個の活性領域の第2主面側に形成される第2主電極とを具備し、遮断時の主電流が大きいときは、第1番目のゲートしきい値電圧より高いゲート電圧を前記制御端子に印加して第1から第n番目の活性領域を同時に動作させ、前記主電流が小さいときは、第n番目のゲートしきい値電圧と該ゲートしきい値電圧より次に高い第n−1番目のゲートしきい値電圧の間の大きさのゲート電圧を前記制御端子に印加して、第n番目の活性領域を動作させ、前記主電流が中間の大きさでm番目の場合は、第m番目のゲートしきい値電圧と該ゲートしきい値電圧より次に高い第m−1番目のゲートしきい値電圧の間の大きさのゲート電圧を前記制御端子に印加して、第m番目から第n番目の活性領域を動作させることで、主電流の大きさに応じて動作する活性領域の大きさを変化させることで、主電流の大きさに応じて動作させる活性領域の大きさを変化させることを特徴とする半導体装置。First to n-th n active regions formed on a semiconductor substrate, a first main electrode collectively formed on the first main surface side of the n active regions, and a first active region A first MOS gate structure having a first gate threshold voltage, which is the maximum voltage formed at the same time, and an nth gate threshold voltage, which is the minimum voltage formed in the nth active region. An nth MOS gate structure having an mth gate threshold voltage, which is an intermediate voltage formed in the mth active region in the middle thereof, and the first MOS gate structure A common control terminal connected to the nth MOS gate structure portion and a second main electrode formed on the second main surface side of the n active regions, and when the main current at the time of interruption is large, A gate voltage higher than the first gate threshold voltage The first to nth active regions are simultaneously operated by applying to the control terminal, and when the main current is small, the nth gate threshold voltage and the second higher threshold voltage than the gate threshold voltage are applied. When a gate voltage having a magnitude between the (n-1) th gate threshold voltage is applied to the control terminal to operate the nth active region, and the main current is the middle magnitude and the mth Applies a gate voltage having a magnitude between the mth gate threshold voltage and the (m-1) th gate threshold voltage, which is higher than the gate threshold voltage, to the control terminal; By operating the mth to nth active regions, the size of the active region that operates according to the size of the main current is changed, so that the active region that operates according to the size of the main current is changed. A semiconductor device characterized in that the size is changed. 前記半導体装置が、バイポーラ型の自己消弧半導体装置であることを特徴とする1〜4のいずれか一項に記載の型半導体装置。The type semiconductor device according to any one of claims 1 to 4, wherein the semiconductor device is a bipolar self-extinguishing semiconductor device. 前記バイポーラ型の自己消弧型半導体装置が、バイポーラトランジスタ、絶縁ゲート型バイポーラトランジスタ、ゲートターンオフサイリスタおよびMOSサイリスタのいずれか一つであることを特徴とする請求項5に記載の半導体装置。6. The semiconductor device according to claim 5, wherein the bipolar self-extinguishing semiconductor device is any one of a bipolar transistor, an insulated gate bipolar transistor, a gate turn-off thyristor, and a MOS thyristor. 複数個のバイポーラ型の自己消弧型半導体チップが並列接続されて同一パッケージに収納された半導体装置において、各チップに形成される制御端子に個別の制御信号を送り、遮断時の主電流の大きさに応じて動作させるチップ数を切替え、該主電流が大きいときは、動作させるチップ数を多くし、該主電流が小さいときは、動作させるチップ数を少なくすることを特徴とする半導体装置。In a semiconductor device in which a plurality of bipolar self-extinguishing semiconductor chips are connected in parallel and housed in the same package, an individual control signal is sent to the control terminal formed on each chip, and the main current at the time of interruption is large. According to the semiconductor device, the number of chips to be operated is switched, the number of chips to be operated is increased when the main current is large, and the number of chips to be operated is decreased when the main current is small. 前記バイポーラ型の自己消弧型半導体チップが、バイポーラトランジスタチップ、絶縁ゲート型バイポーラトランジスタチップ、ゲートターンオフサイリスタチップおよびMOSサイリスタチップのいずれか一つであることを特徴とする請求項7に記載の半導体装置。8. The semiconductor according to claim 7, wherein the bipolar self-extinguishing semiconductor chip is one of a bipolar transistor chip, an insulated gate bipolar transistor chip, a gate turn-off thyristor chip, and a MOS thyristor chip. apparatus.
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