JP4007210B2 - Demultiplexer - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a demultiplexer (DEMUX) suitable for use in a receiver or the like in an optical communication system that employs electrical time division multiplexing (ETDM).
[0002]
In an optical communication system that employs electric time division multiplexing, which is a technique for increasing transmission capacity, a multiplexer (MUX) that multiplexes multiple channels of electrical signals into a single channel of electrical signals is essential for the transmitter. A demultiplexer for returning a multiplexed single-channel electrical signal to a multi-channel electrical signal is essential for the device.
[0003]
[Prior art]
FIG. 7 is a circuit diagram showing an example of a conventional 1: 2 demultiplexer. In FIG. 7, 1 is a master-slave-master D-type flip-flop (Master-Slave-Master D-FF) for separating signals formed by cascading three D latches 2, 3, 4, 5 is 2 This is a master / slave D flip-flop (Master-Slave D-FF) for signal separation formed by connecting D latches 6 and 7 in cascade.
[0004]
FIG. 8 is a circuit diagram showing the configuration of the D latches 2, 3, 4, 6, and 7 (see, for example, Patent Document 1). The D latches 2, 3, 4, 6, and 7 are configured by an edge trigger type latch circuit using SCFL (source coupled FET logic) which is a kind of CML (current mode logic), and the bit rate is 10 Gb / s. The circuit constants are set so as to have an operation speed corresponding to the electrical signal.
[0005]
In FIG. 8, GND is a ground power supply, VSS is a negative power supply, D is a positive phase data input terminal, ND is a negative phase data input terminal, C is a positive phase clock input terminal, NC is a negative phase clock input terminal, and Q is a positive phase. Data output terminal NQ is a reverse phase data output terminal.
[0006]
Further, 8 to 18 are transistors (for example, HEMT: high electron mobility transistor), the transistors 8 and 9 constitute a differential pair to which the positive phase input data and the negative phase input data are inputted, and the transistors 10 and 11 are It constitutes a differential pair to which normal phase output data and reverse phase output data are input.
[0007]
The transistors 12 and 13 constitute a differential pair to which a normal phase clock and a reverse phase clock are input, the transistors 14 and 15 constitute a source follower circuit, and the transistors 16 to 18 constitute a current source. VC1 is a control voltage of the transistor 16, and VC2 is a control voltage of the transistors 17 and 18.
[0008]
Further, reference numerals 19 to 21 denote level shift diodes, and 22 to 26 denote resistors. The resistor 23 is a load resistor of the transistor 8, the resistor 24 is a load resistor of the transistor 9, and the resistors 25 and 26 are to stabilize the current source. For resistance.
[0009]
In the D latch shown in FIG. 8, when the positive phase clock input terminal C is at the H level and the negative phase clock input terminal NC is at the L level, the transistors 8 and 9 are activated and the transistors 10 and 11 are deactivated. The input data is output as it is as output data.
[0010]
On the other hand, when the positive phase clock input terminal C is at L level and the inverted clock input terminal NC is at H level, the transistors 8 and 9 are inactive and the transistors 10 and 11 are activated. As a result, the input data is Instead of being output, the previous output data is latched and output.
[0011]
A master-slave-master type D flip-flop can be configured by connecting three D latches in cascade and alternately inputting clocks having a phase difference of 180 ° to each D latch. Further, a master-slave type D flip-flop can be configured by connecting two D latches in cascade and inputting clocks having different phases by 180 ° alternately to each D latch.
[0012]
In the conventional 1: 2 demultiplexer shown in FIG. 7, a 10 Gb / s single-channel electrical signal DATA obtained by time-division multiplexing two-channel electrical signals DATA-A and DATA-B with a bit rate of 5 Gb / s. -AB is distributed to D flip-flops 1,5.
[0013]
On the other hand, a 5 GHz clock CLK, which is half the frequency of 10 Gb / s, which is the bit rate of the electric signal DATA-AB, is supplied to the D flip-flops 1 and 5 with phases different by 180 °.
[0014]
As a result, the electric signal DATA-AB is alternately latched in the D flip-flops 1 and 5 with a period of 1/10 nsec. From the D flip-flops 1 and 5, the parallelized 2-channel electric signal of 5 Gb / s. DATA-A and DATA-B are output.
[0015]
FIG. 9 is a timing chart showing the operation of the conventional 1: 2 demultiplexer shown in FIG. FIG. 9A shows the operation of the D flip-flop 1 and shows the electric signal DATA-AB, the clock CLK, the output of the D latch 3, the reverse phase clock / CLK, and the separated electric signal DATA-A. FIG. 9B shows the operation of the D flip-flop 5 and shows the electrical signal DATA-AB, the reverse phase clock / CLK, and the separated electrical signal DATA-B.
[0016]
One D flip-flop 1 is a master / slave / master type, and the other D flip-flop 5 is a master / slave type. This is to match the output timing of the output signal DATA-B of the D flip-flop 5.
[0017]
[Patent Document 1]
JP-A-7-273668 [0018]
[Problems to be solved by the invention]
FIG. 10 is a timing chart for explaining the problems of the conventional 1: 2 demultiplexer shown in FIG. 7, in which the electric signal DATA-AB, the clock CLK, the output of the D latch 2, the inverted clock / CLK, the D latch. 3 outputs.
[0019]
In the D flip-flop 1, the D latch 2 in the first stage operates with a clock CLK having a frequency (5 GHz) lower than the bit rate (10 Gb / s) of the electric signal DATA-AB. For this reason, the cycle of the electric signal DATA-A input to the D latch 3 in the subsequent stage becomes longer. When the period of the electric signal DATA-AB is T and the period of the electric signal DATA-A input to the D latch 3 is T ′, T <T ′ <2T.
[0020]
That is, if the bit rate of the electrical signal DATA-AB is BR, the bit rate BR ′ of the electrical signal DATA-A output from the D latch 2 is (multiplicity 2-1) × BR <BR ′ <multiplicity 2 X BR. As a result, it can be said that the D latches 3 and 4 are sufficient to operate at a lower speed than the D latch 2. Similarly, it can be said that a low-speed operation circuit is sufficient for the D latch 7 compared to the D latch 6.
[0021]
However, in the conventional 1: 2 demultiplexer shown in FIG. 7, the D latches 3, 4, and 7 have an operation speed corresponding to an electric signal of 10 Gb / s, like the D latches 2 and 6. For this reason, there was a problem that current consumption was large.
[0022]
In view of the above, an object of the present invention is to provide a demultiplexer capable of reducing power consumption while maintaining high speed of demultiplexing operation.
[0023]
[Means for Solving the Problems]
The present invention is composed of a plurality of D latches that operate in synchronism with a clock and connected in cascade, the time division multiplexed signal have a D flip-flop of the same number as the multiplicity of signal separation to be dispensed, said plurality Among the D latches of the first stage, a clock having a frequency (the bit rate of the time division multiplexed signal / the multiplicity of the time division multiplexed signal) is given as the clock to the D latch of the first stage. The demultiplexer is provided with a clock whose frequency is (the bit rate of the time-division multiplexed signal / the multiplicity of the time-division multiplexed signal) and whose phase is 180 ° different from that of the clock applied to the preceding D latch. The first stage D latch has an operation speed corresponding to the time division multiplexed signal, and the D latches other than the first stage have the bit rate of the time division multiplexed signal × {2 / (The multiplicity of the time-division multiplexed signal + 1)} .
[0024]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, with reference to FIGS. 1-6, 1st Embodiment and 2nd Embodiment of this invention are described.
[0025]
(First embodiment: FIGS. 1 to 3)
FIG. 1 is a circuit diagram showing a first embodiment of the present invention. In the first embodiment of the present invention, the present invention is applied to a 1: 2 demultiplexer. In FIG. 1, reference numeral 27 denotes a signal-separating master / slave / master type D flip-flop formed by connecting three D latches 28, 29 and 30 in cascade.
[0026]
The D latch 28 is a D latch having an operation speed corresponding to an electric signal having a bit rate of 10 Gb / s, and has a configuration shown in FIG. The D latches 29 and 30 are low-speed D latches having an operation speed corresponding to an electric signal having a bit rate of 6.7 Gb / s, and have a configuration described later.
[0027]
31 is a master / slave type D flip-flop for signal separation, which is formed by connecting two D latches 32 and 33 in cascade. The D latch 32 is a D latch having an operation speed corresponding to an electric signal having a bit rate of 10 Gb / s, and has a configuration shown in FIG. The D latch 33 is a low-speed D latch having an operation speed corresponding to an electric signal having a bit rate of 6.7 Gb / s, and has a configuration described later.
[0028]
Here, if the period of the electric signal DATA-AB is T and the period of the electric signal DATA-A input to the D latch 29 is T ′, 1T <T ′ <2T. Therefore, if T ′ is 1.5T, which is between 1T and 2T, the operating speed of the D latches 29, 30, and 33 can correspond to an electrical signal of 10 Gb / s ÷ 1.5 = 6.7 Gb / s. It will be enough if there is.
[0029]
FIG. 2 is a circuit diagram showing the configuration of the D latches 29, 30 and 33. Here, the gate width of the transistor 16 shown in FIG. 8 is Wg1, the gate width of the transistors 17 and 18 shown in FIG. 8 is Wg2, the resistance value of the resistor 22 shown in FIG. 8 is R1, and the resistance values of the resistors 23 and 24 are R2. Assuming that the resistance values of the resistors 25 and 26 are R3, the gate width of the transistor 16 shown in FIG. 2 is Wg1 × 0.5, the gate widths of the transistors 17 and 18 are Wg2 × 0.5, and the resistance value of the resistor 22 is R1. The resistance value of × 2, resistors 23 and 24 is R2 × 2, the resistance values of resistors 25 and 26 are R3 × 2, and the drive current is ½ that of the D latch shown in FIG.
[0030]
As described above, when the drive currents of the D latches 29, 30, and 33 are reduced, the gate widths of the transistors 8 to 15 are narrowed so that the bias of each node of the circuit becomes the same as that of the D latches 28 and 32. It is necessary to increase the resistance value by increasing the gate length. In addition, since the current density is reduced, the size of the diodes 19 to 21 can be reduced.
[0031]
FIG. 3 is a timing chart showing the operation of the first embodiment of the present invention. FIG. 3A shows the operation of the D flip-flop 27, showing the electric signal DATA-AB, the clock CLK, the output of the D latch 29, the reverse phase clock / CLK, and the separated electric signal DATA-A. FIG. 3B shows the operation of the D flip-flop 31 and shows the electric signal DATA-AB, the reverse phase clock / CLK, and the separated electric signal DATA-B.
[0032]
In the first embodiment of the present invention, a single-channel electric signal DATA-AB of 10 Gb / s obtained by time-division multiplexing two-channel electric signals DATA-A and DATA-B with a bit rate of 5 Gb / s is D. Distributed to flip-flops 27 and 31.
[0033]
On the other hand, a 5 GHz clock CLK, which is half the frequency of 10 Gb / s, which is the bit rate of the electric signal DATA-AB, is supplied to the D flip-flops 27 and 31 with phases different by 180 °.
[0034]
As a result, the electric signal DATA-AB is alternately latched by the D flip-flops 27 and 31 with a period of 1/10 nsec. From the D flip-flops 27 and 31, the parallelized two-channel electric signal of 5 Gb / s is obtained. DATA-A and DATA-B are output.
[0035]
According to the first embodiment of the present invention, the first-stage D latches 28 and 32 constituting the signal separation flip-flops 27 and 31 have an operation speed corresponding to an electric signal having a bit rate of 10 Gb / s. Since the D latches 29, 30, and 33 other than the first stage are low-speed D latches having an operation speed corresponding to an electric signal having a bit rate of 6.7 Gb / s, each demultiplexer is demultiplexed. It is possible to maintain high speed operation and reduce the current consumption of the D latches 29, 30, and 33 other than the first stage, thereby reducing the power consumption.
[0036]
In the D latches 29, 30, and 33, when the drive current is reduced, when the size of the transistors 8 to 15 is reduced, the chip area can be reduced and the chip cost can be reduced. . On the other hand, when the gate length of the transistors 8 to 15 is increased, the power consumption can be further reduced, the circuit reliability can be improved, and the yield can be improved.
[0037]
(Second embodiment: FIGS. 4 to 6)
FIG. 4 is a circuit diagram showing a second embodiment of the present invention. In the second embodiment of the present invention, the present invention is applied to a 1: 4 demultiplexer. In FIG. 4, 34 is a signal-separating master / slave / master type D flip-flop formed by connecting three D latches 35, 36, and 37 in cascade. The D latch 35 is a D latch having an operation speed corresponding to an electric signal having a bit rate of 10 Gb / s, and the D latches 36 and 37 have an operation speed corresponding to an electric signal having a bit rate of 4 Gb / s. This is a low-speed D-latch.
[0038]
A master / slave type D flip-flop 38 includes two D latches 39 and 40 connected in cascade. The D latch 39 is a D latch having an operation speed corresponding to an electric signal having a bit rate of 10 Gb / s, and the D latch 40 is a low speed having an operation speed corresponding to an electric signal having a bit rate of 4 Gb / s. D latch for
[0039]
Reference numeral 41 denotes a signal-separating master-slave-master type D flip-flop formed by connecting three D latches 42, 43, 44 in cascade. The D latch 42 is a D latch having an operation speed corresponding to an electric signal having a bit rate of 10 Gb / s. The D latches 43 and 44 have an operation speed corresponding to an electric signal having a bit rate of 4 Gb / s. This is a low-speed D-latch.
[0040]
45 is a master / slave type D flip-flop formed by connecting two D latches 46 and 47 in cascade. The D latch 46 is a D latch having an operation speed corresponding to an electric signal having a bit rate of 10 Gb / s, and the D latch 47 is a low speed having an operation speed corresponding to an electric signal having a bit rate of 4 Gb / s. This is a D latch for use.
[0041]
Here, the D latches 35, 39, 42, 46 have the configuration shown in FIG. 8, and the D latches 36, 37, 40, 43, 44, 47 are transistors 16 of the D latch shown in FIG. The gate widths of the transistors 17 and 18 are further reduced, and the resistance values of the resistors 22 to 26 are further increased so that the gate-source voltages of the transistors 17 and 18 are the same as those of the transistors 17 and 18 shown in FIG. Can be configured.
[0042]
Reference numeral 48 denotes a toggle flip-flop that divides the clock signal CLK of 5 GHz and outputs two clock signals CLK0 ° and CLK90 ° of 2.5 GHz having a phase difference of 90 °. The clock CLK90 ° is a clock delayed by 90 ° with respect to the clock CLK0 °.
[0043]
In the second embodiment of the present invention, a 10 Gb / s single-channel electric signal obtained by time-division multiplexing 2.5-Gb / s four-channel electric signals DATA-A, DATA-B, DATA-C, and DATA-D. The signal DATA-ABCD is distributed to the D flip-flops 34, 38, 41, 45.
[0044]
In addition, a clock signal CLK0 ° of 2.5 GHz is supplied to the D flip-flops 34 and 38 with phases different from each other by 180 °. Latched alternately to the flip-flops 34 and 38.
[0045]
In addition, a 2.5 GHz clock CLK90 ° is supplied to the D flip-flops 41 and 45 at phases different from each other by 180 °, and the DATA-B and DATA-D in the electric signal DATA-ABCD have a period of 1/20 nsec. 41 and 45 are alternately latched.
[0046]
As a result, D flip-flops 34, 38, 41, and 45 output 2.5 Gb / s parallel 4-channel electrical signals DATA-A, DATA-C, DATA-B, and DATA-D. It will be.
[0047]
FIG. 5 is a timing chart showing the operation of the second embodiment of the present invention. Electric signal DATA-ABCD, clock CLK0 °, separated electric signals DATA-A, DATA-C, clock CLK90 °, separated electricity Signals DATA-B and DATA-D are shown.
[0048]
FIG. 6 is a timing chart showing the operation of the D flip-flop 34, and shows the electrical signal DATA-ABCD, the clock CLK0 °, the output of the D latch 35, the clock / CLK0 °, and the output of the D latch 36.
[0049]
Here, in the D flip-flop 34, the first-stage D latch 35 operates with a clock CLK having a frequency (2.5 GHz) lower than the bit rate (10 Gb / s) of the electric signal DATA-ABCD. For this reason, the cycle of the electrical signal DATA-A input to the D latch 36 at the subsequent stage becomes longer.
[0050]
Here, if the cycle of the electrical signal DATA-ABCD is T and the cycle of the electrical signal DATA-A input to the D latch 36 is T ′, 2T <T ′ <3T. Therefore, if T ′ is 2.5T, which is between 2T and 3T, the operating speed of the D latches 36, 37, 40, 43, 44, 47 is 10Gb / s ÷ 2.5 = 4Gb / s electrical signal. It will be enough if it can cope.
[0051]
According to the second embodiment of the present invention, the first-stage D latches 35, 39, 42, and 46 constituting the signal separation flip-flops 34, 38, 41, and 45 are converted into electrical signals having a bit rate of 10 Gb / s. The D latches 36, 37, 40, 43, 44 and 47 other than the first stage are low-speed D latches having an operation speed corresponding to an electric signal with a bit rate of 4 Gb / s. Therefore, with respect to the 1: 4 demultiplexer, the demultiplexing operation is maintained at high speed, and the current consumption of the D latches 36, 37, 40, 43, 44, 47 other than the first stage is reduced, thereby reducing the power consumption. Can be planned.
[0052]
Further, in the D latches 36, 37, 40, 43, 44, and 47 other than the first stage, the chip area is reduced when the size of the transistors 8 to 15 is reduced due to the reduction of the drive current. Cost can be reduced. On the other hand, when the gate length of the transistors 8 to 15 is increased, the power consumption can be further reduced, the circuit reliability can be improved, and the yield can be improved.
[0053]
In the first and second embodiments of the present invention, the case where the HEMT is used as the transistor has been described. However, a transistor having a different structure such as a bipolar transistor can also be used.
[0054]
The D flip-flops 34, 38, 41, 45 are arranged in order to align the phases of the electrical signals DATA-A, DATA-C, DATA-B, DATA-D output from the D flip-flops 34, 38, 41, 45. A D latch that operates with a clock of 2.5 GHz may be provided in the subsequent stage.
[0055]
【The invention's effect】
As described above, according to the present invention, among the plurality of D latches constituting the same number of D flip-flops as the signal separation multiplicity , the operation speed of the D latches other than the first stage is lower than that of the first stage D latch. Therefore, by using a high-speed D latch of the first stage, it is possible to maintain the high speed of the demultiplexer operation, reduce the current consumption of the D latches other than the first stage, and reduce the power consumption. it can.
[Brief description of the drawings]
FIG. 1 is a circuit diagram showing a first embodiment of the present invention.
FIG. 2 is a circuit diagram showing a configuration of a low-speed D-latch provided in the first embodiment of the present invention.
FIG. 3 is a timing chart showing the operation of the first embodiment of the present invention.
FIG. 4 is a circuit diagram showing a second embodiment of the present invention.
FIG. 5 is a timing chart showing the operation of the second exemplary embodiment of the present invention.
FIG. 6 is a timing chart showing an operation of a master-slave-master type D flip-flop provided in the second embodiment of the present invention;
FIG. 7 is a circuit diagram showing an example of a conventional demultiplexer.
FIG. 8 is a circuit diagram showing a configuration of a D latch included in the conventional demultiplexer shown in FIG.
9 is a timing chart showing the operation of the conventional demultiplexer shown in FIG.
10 is a timing chart for explaining problems of the conventional demultiplexer shown in FIG.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 ... Master-slave-master type D flip-flop 2, 3, 4 ... D latch 5 ... Master-slave type D flip-flop 6, 7 ... D latch 8-18 ... Transistor 19-21 ... Diode 22-26 ... Resistor 27... Master-slave-master type D flip-flops 28, 29, 30... D latch 31... Master-slave type D flip-flop 32, 33. 36, 37 ... D latch 38 ... Master / slave type D flip-flop 39, 40 ... D latch 41 ... Master / slave / master type D flip-flop 42, 43, 44 ... D latch 45 ... Master / slave type D flip-flops 46, 47... D latch

Claims (4)

A plurality of D latches operate in synchronization with the clock is constructed by cascade connection, time division multiplexed signals have a D flip-flop of the same number as the multiplicity of signal separation to be dispensed,
Of the plurality of D latches, the D latch at the first stage is given a clock having a frequency (bit rate of the time division multiplexed signal / multiplicity of the time division multiplexed signal) as the clock. The latch has a frequency (the bit rate of the time-division multiplexed signal / the multiplicity of the time-division multiplexed signal) as the clock, and a demultiplexer to which a clock that is 180 ° out of phase with the clock supplied to the preceding D-latch is given. Because
The first stage D latch has an operation speed corresponding to the time division multiplexed signal,
The D latches other than the first stage have an operation speed of the bit rate of the time division multiplexed signal × {2 / (the multiplicity of the time division multiplexed signal + 1)} . Each of the plurality of D latches includes a transistor that determines a drive current;
In the D latches other than the first stage, the current flowing through the transistor that determines the driving current is reduced compared to the D latch in the first stage, so that the bit rate of the time division multiplexed signal × {2 / (the time division 2. The demultiplexer according to claim 1 , wherein the demultiplexer has an operation speed of multiplicity of multiplexed signals + 1)} . 3. The demultiplexer according to claim 2 , wherein a resistor is inserted on a source side of the transistor that determines the driving current . 3. The demultiplexer according to claim 2 , wherein the D latches other than the first stage have the same bias of each node as that of the first stage D latch .

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