KR101095974B1 - Demultiplexer - Google Patents

Abstract

The demultiplexer includes a first NRZ de-flop that generates a first Non-Return-to-Zero (NRZ) output signal based on an input signal and a first clock signal and a second NRZ based on the input signal and a second clock signal. And a second NRZ de flip-flop that produces an output signal. The frequency of the first clock signal corresponds to half of the frequency of the input signal and the second clock signal corresponds to an inverted signal of the first clock signal. Each of the first NRZ de flip-flop and the second NRZ de flip-flop generates an output signal corresponding to the input signal and samples the generated output signal based on a clock signal input to the corresponding de flip-flop. An RZ de-flop that generates a to-Zero (RZ) output signal and an SR latch that receives the RZ output signal and generates an NRZ output signal.

Description

Demultiplexer {DEMULTIPLEXER}

The disclosed technique relates to a demultiplexer, and more particularly, to a demultiplexer using a device having negative differential resistance characteristics.

A multiplexer is a device that multiplexes a plurality of input signals to output one output signal, and a demultiplexer is a device that demultiplexes one input signal into a plurality of output signals.

In data processing systems such as communication systems, the faster the multiplexing or demultiplexing operation, the more data can be processed. Therefore, in order to increase data throughput and improve processing speed, the multiplexing or demultiplexing calculation speed must be improved.

In one or more embodiments, the demultiplexer may generate a first NRZ de flip-flop and a first NRZ de-flop that generates a first non-return-to-zero (NRZ) output signal based on an input signal and a first clock signal. And a second NRZ de flip-flop that generates a second NRZ output signal as a basis. The frequency of the first clock signal corresponds to half of the frequency of the input signal and the second clock signal corresponds to an inverted signal of the first clock signal. Each of the first NRZ de flip-flop and the second NRZ de flip-flop generates an output signal corresponding to the input signal and samples the generated output signal based on a clock signal input to the corresponding de flip-flop. An RZ de-flop that generates a to-Zero (RZ) output signal and an SR latch that receives the RZ output signal and generates an NRZ output signal.

In one or more embodiments, the demultiplexer may generate a first NRZ de flip-flop and a first NRZ de-flop that generates a first non-return-to-zero (NRZ) output signal based on an input signal and a first clock signal. And a second NRZ de flip-flop that generates a second NRZ output signal as a basis. The frequency of the first clock signal corresponds to half of the frequency of the input signal and the second clock signal corresponds to an inverted signal of the first clock signal. Each of the first NRZ de flip-flop and the second NRZ de flip-flop generates an output signal corresponding to the input signal and samples the generated output signal based on a clock signal input to the corresponding de flip-flop. RZ di flip-flop that generates a to-Zero (RZ) output signal, receives an RZ output signal from the RZ de flip-flop, generates an RZ output signal in phase with the RZ output signal, and has a constant voltage gain regardless of the connected load And an SR latch configured to receive an RZ output signal from the emitter follower and to generate an NRZ output signal.

Among the embodiments, the demultiplexer demultiplexes the input signal into a plurality of output signals based on the input signal and the multiphase clock signal. The demultiplexer includes a plurality of NRZ de flip-flops for generating a non-return-to-zero (NRZ) output signal based on a clock signal of a specific phase of the multiphase clock signal and the input signal, and the frequency of the clock signal. Corresponds to half of the frequency of the input signal. Each of the plurality of NRZ de flip-flops generates an output signal corresponding to the input signal and samples the generated output signal based on a clock signal input to the corresponding de-flop flop to return-to-zero (RZ) output. An RZ de flip-flop for generating a signal and an SR latch for receiving the RZ output signal and generating an NRZ output signal.

1 is a diagram illustrating a DC IV curve of an RTD.
2 illustrates a demultiplexer according to an embodiment of the disclosed technology.
FIG. 3 is a diagram for describing an RZ de flip-flop of FIG. 2.
4 is a view for explaining the SR latch of FIG.
FIG. 5 is a diagram illustrating a load diagram of a voltage of an output node, a current flowing through an RTD and a transistor in the SR latch of FIG. 4.
FIG. 6 is a timing diagram for describing an operation of the SR latch of FIG. 4.
FIG. 7 is a diagram illustrating an RZ de flip-flop of FIG. 3 and an SR latch of FIG. 4 connected.
8 is a diagram for describing a demultiplexer according to another embodiment of the disclosed technology.
9 illustrates an emitter follower according to an embodiment of the disclosed technology.
FIG. 10 illustrates a demultiplexer according to another embodiment of the disclosed technology.

The description of the disclosed technique is merely an example for structural or functional explanation and the scope of the disclosed technology should not be construed as being limited by the embodiments described in the text. That is, the embodiments may be variously modified and may have various forms, and thus the scope of the disclosed technology should be understood to include equivalents capable of realizing the technical idea.

On the other hand, the meaning of the terms described in the present application should be understood as follows.

The terms " first ", " second ", and the like are used to distinguish one element from another and should not be limited by these terms. For example, the first component may be named a second component, and similarly, the second component may also be named a first component.

The term “and / or” should be understood to include all combinations that can be suggested from one or more related items. For example, the meaning of “first item, second item and / or third item” may be given from two or more of the first, second or third items as well as the first, second or third items. Any combination of the possible items.

When a component is referred to as being "connected" to another component, it should be understood that there may be other components in between, although it may be directly connected to the other component. On the other hand, when an element is referred to as being "directly connected" to another element, it should be understood that there are no other elements in between. On the other hand, other expressions describing the relationship between the components, such as "between" and "immediately between" or "neighboring to" and "directly neighboring to", should be interpreted as well.

Singular expressions should be understood to include plural expressions unless the context clearly indicates otherwise, and terms such as "include" or "have" refer to features, numbers, steps, operations, components, parts, or parts thereof described. It is to be understood that the combination is intended to be present, but not to exclude in advance the possibility of the presence or addition of one or more other features or numbers, steps, operations, components, parts or combinations thereof.

For each step, the identifiers (e.g., a, b, c, ...) are used for convenience of description, and the identifiers do not describe the order of the steps, and each step is clearly contextual. Unless stated in a specific order, it may occur differently from the stated order. That is, each step may occur in the same order as specified, may be performed substantially simultaneously, or may be performed in the reverse order.

All terms used herein have the same meaning as commonly understood by one of ordinary skill in the art unless otherwise defined. Terms defined in commonly used dictionaries should be interpreted to be consistent with meaning in the context of the relevant art and can not be construed as having ideal or overly formal meaning unless expressly defined in the present application.

The disclosed technique can be applied to all three-terminal transistors, including BJT, HBT and FETs, and to all diodes with negative differential resistance characteristics. Hereinafter, a description will be made based on an InP-based Resonant Tunneling Diode (RTD) having a low peak voltage and a high peak-to-valley current ratio (PVCR) even at room temperature and BJT.

1 is a diagram illustrating a DC I-V curve of an RTD.

In FIG. 1, a Resonant Tunneling Diode (RTD) is a diode having a negative differential resistance (NDR) characteristic at a low voltage. RTD increases with increasing voltage applied to RTD based on 0V. However, when the voltage applied to the RTD increases above the peak voltage Vp, the current decreases. That is, RTD has the characteristic of negative resistance.

The DC I-V curve of the RTD is expressed symmetrically about the origin. The right side shows the DC I-V curve when the positive voltage is applied to the RTD. The left side shows the DC I-V curve when the negative voltage is applied to the RTD. The RTDs have a negative differential resistance (NDR) region respectively for positive and negative voltages, and peak voltage (Vp) points 101 and 102 where peak currents appear before the negative differential resistance region, respectively. This exists. In addition, the RTD has valley voltage points 103 and 104 where a valley current appears after the negative differential resistance region, respectively.

2 illustrates a demultiplexer according to an embodiment of the disclosed technology.

Referring to FIG. 2, the demultiplexer 200 includes a Non-Return-to-Zero (NZZ) de- flip-flop 210. 220 and a set / reset (SR) latch 230.

The demultiplexer 200 demultiplexes the input signal based on the received input signal and the clock signal to generate two output signals. The demultiplexer 200 may include a first NRZ de flip-flop 210a for generating a first NRZ output signal and a second NRZ de flip-flop 210b for generating a second NRZ output signal. The frequency of the clock signal received at the demultiplexer 200 may correspond to half of the frequency of the input signal.

The first NRZ de flip-flop 210a generates a first NRZ output signal based on the input signal and the first clock signal, and the second NRZ de flip-flop 210b is based on the input signal and the second clock signal. Generates 2 NRZ output signals. The first clock signal corresponds to the clock signal received by the demultiplexer 200, and the second clock signal corresponds to the inverted signal of the first clock signal.

Each of the first NRZ de flip-flop 210a and the second NRZ de flip-flop 210b includes an RZ de-flop flop 220 and an SR latch 230. The RZ de flip-flop 220 generates an output signal corresponding to the input signal, and generates the RZ output signal by sampling the generated output signal based on a clock signal input to the corresponding de flip-flop. The SR latch 230 receives the RZ output signal from the RZ de flip-flop 220 and generates an NRZ output signal.

FIG. 3 is a diagram for describing an RZ de flip-flop of FIG. 2.

Referring to FIG. 3, the RZ de flip-flop 220 includes an input / output unit 310 and an RTD network unit 320. In one embodiment, the RZ de flip-flop 220 may further include a first DC bias unit 330.

The input / output unit 310 includes an output node 350 for generating an output signal and a first transistor unit 340 for controlling a current flowing in the output node 350 according to the input signal. The first transistor unit 340 sends the current of the output node 350 to the RTD network unit 320 or the current of the output node 350 to the first DC bias unit 330 based on the input signal.

In an embodiment, the first transistor unit 340 includes a first transistor 342 that receives a first input signal and a second transistor 344 that receives a second input signal, and the first transistor 342. Each of the and second transistors 344 may be connected in series with the first DC bias unit 330 to form a current mode logic (CML). In one embodiment, the first input signal may correspond to an input signal received at the demultiplexer 200, and the second input signal may correspond to an inverted signal of the first input signal.

In one embodiment, the output node 350 includes a first output node 352 and a second output node 354, where the first output node 352 can be located at one end of the first transistor 342. The second output node 354 may be located at one end of the second transistor 344. For example, the first output node 352 can be located in the collector of the first transistor 342, and the second output node 354 can be located in the collector of the second transistor 344.

The RTD network unit 320 performs a sampling operation on the output signal of the output node 350 at the first edge of the clock signal based on the clock signal input to the corresponding flip-flop. In one embodiment, the RTD network unit 320 is a first RTD 322 that receives a clock signal, a second RTD 324 connected to a power source or ground and between the first RTD 322 and the second RTD 324 A first MOBILE (MOnostable BIstable transition Logic Element) unit including a first RTD node 323 in the third RTD 326 receiving a clock signal, a fourth RTD 328 connected to a power source or ground, and a third RTD 328 And a second MOBILE portion comprising a second RTD node 327 between the RTD 326 and the fourth RTD 328. In one embodiment, the first MOBILE unit and the second MOBILE unit may be connected in parallel, the first RTD node 323 is connected with the first output node 352 and the second RTD node 327 is the second output node. 354 may be connected.

The first DC bias unit 330 lowers the DC voltage of the RZ de flip-flop 220. In one embodiment, the first DC bias unit 330 may correspond to a current mirror that maintains a constant output current by mirroring the current at the input terminal regardless of the connected load. In one embodiment, the current mirror may include a third transistor 332, a load 334, and a fourth transistor 336. In one embodiment, the third transistor 332 may correspond to a diode connected transistor, and the base of the third transistor 332 and the base of the fourth transistor 336 may be connected. The load 334 may be connected to an input terminal of the current mirror, and the current mirror may output an output current corresponding to the current through the output terminal based on the current of the input terminal. In one embodiment, the input terminal may correspond to the collector of the third transistor 332 and the output terminal may correspond to the collector of the fourth transistor 336.

4 is a view for explaining the SR latch of FIG.

Referring to FIG. 4, the SR latch 230 may include a second transistor unit 410 that receives an RZ output signal, a first RTD unit 420 and a second transistor unit connected in series with the second transistor unit 410. And an output node 430 for generating an NRZ output signal between the 410 and the first RTD unit 420. In an embodiment, the SR latch 230 may further include a second DC bias unit 440 connected in series with the second transistor unit 410. The second DC bias unit 440 lowers the DC voltage of the first SR latch 400.

The SR latch 400 receives the RZ output signal and generates an NRZ output signal. The second transistor unit 410 includes a third transistor 412 and a fourth transistor 414, and the first RTD unit 420 includes a fifth RTD 422 and a sixth RTD 424. The fifth RTD 422 and the third transistor 412 are connected in series, and the sixth RTD 424 and the fourth transistor 414 are connected in series. The third output node 432 generates the NRZ output signal between the fifth RTD 422 and the third transistor 412 and the fourth output node 434 is the sixth RTD 424 and the fourth transistor 414. To generate an NRZ output signal.

The third transistor 412 and the fourth transistor 414 are connected to the second DC bias unit 440 in series. In one embodiment, the valley (Valley) of the second DC bias unit current (I _EE) a value obtained by dividing by two _{(440) (I EE / 2} ) is the 5 RTD (422) and a 6 RTD (424) The current value I _EE of the second DC bias unit 440 may be set smaller than the current and greater than the peak current Ip of the fifth RTD 422 and the sixth RTD 424.

FIG. 5 is a diagram illustrating a load diagram of a voltage of an output node, a current flowing through an RTD and a transistor in the SR latch of FIG. 4.

Referring to FIG. 5, FIG. 5A illustrates an output signal (or voltage) generated at the third output node 432 between the fifth RTD 422 and the third transistor 412, and the fifth RTD 422 and the fifth signal. A diagram showing a load diagram of the current I _SET flowing through the three transistors 412, and FIG. 5B illustrates an output signal generated at the fourth output node 434 between the sixth RTD 424 and the fourth transistor 414. (Or voltage) and a load diagram of the current I _RESET flowing through the sixth RTD 424 and the fourth transistor 414.

The first input signal SET input to the third transistor 412 of the SR latch 230 and the second input signal RESET input to the fourth transistor 414 are RZ signals and the first input signal SET. ) And the second input signal RESET have one of three states: (SET, RESET) = {(LOW, LOW), (LOW, HIGH), (HIGH, LOW)}. Since the second transistor unit 410 is connected in series with the second DC bias unit 440 to form a CML, the current I _SET flowing through the third transistor 412 and the current flowing through the fourth transistor 414 ( The sum of I _RESET ) must be equal to the current value I _EE of the second DC bias unit 440. Table 1 summarizes the values of I _SET and I _RESET according to the states of the first input signal SET and the second input signal RESET.

Referring to Table 1, when (SET, RESET) = (HIGH, LOW), I _SET = I _EE , I _RESET = 0. Thus, referring to FIGS. 5A and 5B, when (SET, RESET) = (HIGH, LOW) corresponds to the state of '1', the output signal (or voltage) of the third output node 432 ( / Output) may correspond to Logic '0' (or LOW), and the output signal (or voltage) Output of the fourth output node 434 may correspond to Logic '1' (or HIGH). Can be.

If the state changes to (SET, RESET) = (LOW, LOW), then I _SET = I _RESET = I _EE / 2. Therefore, referring to FIGS. 5A and 5B, when the state is changed to (SET, RESET) = (LOW, LOW), the state is changed to the state of '2', so that the output signal of the third output node 432 ( Alternatively, the voltage (/ Output) and the output signal (or voltage) Output of the fourth output node 434 maintain the previous state. That is, the output signal (or voltage) / Output of the third output node 432 and the output signal (or voltage) Output of the fourth output node 434 do not return to zero.

If the status changes to (SET, RESET) = (LOW, HIGH), I _SET = 0, I _RESET = I _EE . Therefore, referring to FIGS. 5A and 5B, when the state is changed to (SET, RESET) = (LOW, HIGH), the state is changed to the state of '3', so that the output signal of the third output node 432 ( Alternatively, the voltage (/ Output) may correspond to Logic '1' (or HIGH), and the output signal (or voltage) Output of the fourth output node 434 may be Logic '0' (or, LOW).

FIG. 6 is a timing diagram for describing an operation of the SR latch of FIG. 4.

Referring to FIG. 6, when the RZ type first input signal SET = 1011 and the second input signal RESET = 0100 are input to the SR latch 230, the output signal of the third output node 432 ( Alternatively, it can be confirmed that the voltage (/ Output) is '0100' in the NRZ form, and the output signal (or voltage) Output of the fourth output node 434 is '1011' in the NRZ form.

FIG. 7 is a diagram illustrating an RZ de flip-flop of FIG. 3 and an SR latch of FIG. 4 connected.

In FIG. 7, the third transistor of the SR latch 230 receives an output signal generated at the first output node of the RZ de flip-flop 220, and the fourth transistor of the SR latch 230 receives the RZ de flip-flop ( The output signal generated by the second output node 220 is received.

8 is a diagram for describing a demultiplexer according to another embodiment of the disclosed technology.

Referring to FIG. 8, the demultiplexer 800 includes an NRZ de flip-flop 810, and the NRZ de flip-flop 810 includes an RZ de flip-flop 820, an emitter follower 830, and an SR latch 840. ).

Since the descriptions of the RZ de flip-flop 820 and the SR latch 840 are substantially the same as those of the demultiplexer of FIG. 2, a description thereof will be omitted. The emitter follower 830 receives the RZ output signal from the RZ de flip-flop 820, generates an RZ output signal having the same phase as the input RZ output signal, and maintains a constant voltage gain regardless of the connected load. The NRZ de flip-flop 810 may stably provide the RZ output signal of the RZ de flip-flop 820 to the SR latch 840 through the emitter follower 830.

9 illustrates an emitter follower according to an embodiment of the disclosed technology.

Referring to FIG. 9, the emitter follower 830 includes a third transistor unit 910, a first load unit 920, and an output node 930.

The third transistor unit 910 receives the RZ output signal from the RZ de flip-flop 820 and controls the current flowing to the output node 930 based on the input signal. The third transistor unit 910 is connected in series with the first load unit 920, and the output node 930 generates an output signal between the third transistor unit 910 and the first load unit 920.

In an embodiment, the third transistor unit 910 may include a fifth transistor 912 and a sixth transistor 914, and the first load unit 920 may include the first load 922 and the second load ( 924). The fifth transistor 912 may be connected in series with the first load 922, and the sixth transistor 914 may be connected in series with the second load 924.

The fifth output node 932 generates an output signal between the first load 922 and the fifth transistor 912 and the sixth output node 934 is between the second load 924 and the sixth transistor 914. Generates an output signal. In one embodiment, the fifth transistor 912 and the sixth transistor 914 may correspond to an n-type transistor.

FIG. 10 illustrates a demultiplexer according to another embodiment of the disclosed technology.

Referring to FIG. 10, the demultiplexer 1020 includes a plurality of NRZ de flip-flops 1030, and each of the plurality of NRZ de flip-flops 1039 each includes an RZ de flip-flop 1040 and an SR latch 1050. Include. In one embodiment, each of the plurality of NRZ de flip-flops 1030 may further include an emitter follower and the emitter follower may be located between the RZ de flip-flop 1040 and the SR latch 1050. have.

The demultiplexer 1020 demultiplexes an input signal into a plurality of output signals based on the received input signal and the multiphase clock signal received from the multiphase clock signal generator 1010. do. For example, the demultiplexer 1020 may demultiplex the received input signal into N (N is an integer greater than 1) output signals.

The demultiplexer 1020 includes a plurality of NRZ de flip-flops 1030 for generating an NRZ output signal based on a clock signal and an input signal of a specific phase of the multiphase clock signal. For example, the demultiplexer 1020 that demultiplexes the received input signal into N output signals may include N NRZ de flip-flops 1030. The frequency of the clock signal may correspond to half of the frequency of the input signal. Each of the plurality of NRZ de flip-flops 1039 includes an RZ de flip-flop 1040 and an SR latch 1050. Since the descriptions of the RZ de flip-flop 1040 and the SR latch 1050 are substantially the same as those of the demultiplexer of FIG. 2, the description thereof will be omitted.

The disclosed technique may have the following effects. It is to be understood, however, that the scope of the disclosed technology is not to be construed as limited thereby, as it is not meant to imply that a particular embodiment should include all of the following effects or only the following effects.

The demultiplexer according to an embodiment may operate at a high speed to improve processing speed. Since the demultiplexer does not use a feedback loop, it can operate at high speeds and can be used in high performance data processing systems such as high speed optical communication systems.

The demultiplexer according to an embodiment may efficiently use resources. Demultiplexers can be implemented with fewer devices and consume less power, resulting in higher performance at lower cost.

Although described above with reference to preferred embodiments of the disclosed technology, those skilled in the art will be able to variously modify and change the disclosed technology without departing from the spirit and scope of the technology described in the claims below. It will be appreciated.

Claims (16)

A first NRZ de flip-flop that generates a first Non-Return-to-Zero (NRZ) output signal based on an input signal and a first clock signal—the frequency of the first clock signal is half of the frequency of the input signal. Corresponding to; And
A second NRZ de flip-flop that generates a second NRZ output signal based on the input signal and a second clock signal, the second clock signal corresponding to an inverted signal of the first clock signal;
Each of the first NRZ di flip-flop and the second NRZ di flip-flop
An RZ de- flip-flop for generating an output signal corresponding to the input signal and sampling the generated output signal based on a clock signal input to the corresponding de- flip-flop to generate a Return-to-Zero (RZ) output signal; And
And an SR latch configured to receive the RZ output signal and generate an NRZ output signal. The method of claim 1, wherein the RZ di flip-flop
An input / output unit including an output node generating an output signal and a first transistor unit controlling a current flowing through the output node according to the input signal; And
And a Resonant Tunneling Diode (RTD) network unit that performs a sampling operation on the output signal at the first edge of the clock signal based on the clock signal input to the de-flop. The method of claim 2, wherein the RZ de flip-flop
And a first DC bias unit connected in series with the transistor unit. The method of claim 3, wherein the first DC bias unit
A demultiplexer, characterized in that it corresponds to a current mirror that maintains a constant output current by mirroring the current at the input stage regardless of the connected load. The method of claim 3, wherein the first transistor unit
A current of the output node to the RTD network part or a current of the output node to the first DC bias part based on the input signal. The method of claim 3, wherein the first transistor unit
A first transistor receiving a first input signal and a second transistor receiving a second input signal;
And each of the first transistor and the second transistor is connected in series with the first DC bias unit to form a CML. The method of claim 2, wherein the RTD network unit
A first MOBILE (MOnostable BIstable transition Logic Element) unit including a first RTD receiving the clock signal, a second RTD connected to a power source or ground, and a first RTD node between the first RTD and the second RTD; And
And a second MOBILE unit including a third RTD receiving the clock signal, a fourth RTD connected to a power source or a ground, and a second RTD node between the third RTD and the fourth RTD. The method of claim 7, wherein
The output node includes a first output node and a second output node
And wherein the first RTD node is connected with the first output node and the second RTD node is connected with the second output node. The method of claim 1, wherein the SR latch is
And a second transistor unit receiving the RZ output signal, an RTD unit connected in series with the second transistor unit, and an output node generating the NRZ output signal between the second transistor unit and the RTD unit. Demultiplexer. The method of claim 9, wherein the SR latch is
And a second DC bias unit connected in series with the second transistor unit. The method of claim 10, wherein the second DC bias unit
A demultiplexer characterized in that it corresponds to a current mirror that maintains a constant output current by mirroring the current at the input stage regardless of the connected load. delete delete delete delete A demultiplexer for demultiplexing an input signal into a plurality of output signals based on an input signal and a multiphase clock signal,
The demultiplexer includes a plurality of NRZ de- flip-flops that generate a non-return-to-zero (NRZ) output signal based on a clock signal of a particular phase of the multiphase clock signal and the input signal; The frequency corresponds to half of the frequency of the input signal,
Each of the plurality of NRZ de flip-flops
An RZ de- flip-flop for generating an output signal corresponding to the input signal and sampling the generated output signal based on a clock signal input to the corresponding de- flip-flop to generate a Return-to-Zero (RZ) output signal; And
And an SR latch configured to receive the RZ output signal and generate an NRZ output signal.

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