JP4002471B2 - Test equipment - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a test method and a test apparatus for a semiconductor device, and more particularly to a test method and a test apparatus for a semiconductor device for performing an operation test on a semiconductor device such as a semiconductor memory device.
[0002]
[Prior art]
Whether a semiconductor device such as an IC or a memory has a desired performance is tested by a semiconductor device testing apparatus. The test apparatus inputs a test signal of a predetermined pattern to the semiconductor device to be tested via a pin, and checks whether the output from the semiconductor device is a desired signal based on the input test signal. Then, it is determined whether or not the semiconductor device is a non-defective product.
[0003]
FIG. 5 is a block diagram showing a configuration of a conventional semiconductor device testing apparatus. The test apparatus 10 includes the output variable delay circuit 12, the comparison variable delay circuit 13, the output circuit 14, and the comparison circuit 15 as many as the number (n) of pins of the semiconductor device to be tested, and further includes a signal generation circuit. 11, a determination circuit 21, and an adjustment circuit 25. The n pins of the semiconductor device 30 to be tested are connected to the corresponding output circuit 14 and comparison circuit 15.
[0004]
The signal generation circuit 11 generates a test signal and a strobe signal based on a predetermined pattern. The test signal generated by the signal generation circuit 11 is delayed by the output variable delay circuit 12 and input to the semiconductor device 30 via the output circuit 14 such as a driver. The output of the semiconductor device 30 based on the test signal is binarized by the comparison circuit 15 such as a comparator at the timing of the strobe signal delayed by the comparison variable delay circuit 13 and input to the determination circuit 21. The determination circuit 21 determines whether or not the input from the comparison circuit 15 is the same as a predetermined expected value determined by the test signal pattern.
[0005]
FIG. 6 shows the waveform of the signal at each pin, (a) shows the waveform before timing adjustment, and (b) shows the waveform after timing adjustment. In general, when the delay amounts of the output variable delay circuit 12 and the comparison variable delay circuit 13 are not adjusted, the timing at which the test signal is input to the semiconductor device 30 and the timing at which the strobe signal is input to the comparison circuit 15 are the wiring length. Due to the influence of noise and the like, the timing differs for each pin, and skew occurs as shown in FIG. The output variable delay circuit 12 and the comparison variable delay circuit 13 have their delay amounts controlled by the adjustment circuit 25 to adjust the skew of the test signal and the strobe signal. As shown in FIG. 5B, the adjusted test signal is supplied to each pin of the semiconductor device 30 at the same timing, and the adjusted strobe signal is supplied to each comparison circuit 15 at the same timing. When there is variation in wiring delay between signal paths from each input / output pin to each comparison circuit 15 of the semiconductor device 30, a variable delay circuit is provided in the signal path in this section to skew the output signal of the semiconductor device 30. Adjustments can also be made.
[0006]
[Problems to be solved by the invention]
By the way, in the test of the semiconductor device 30, test signals and strobe signals having high frequencies such as thousands and tens of thousands of cycles are used. Therefore, the test signals and strobe signals depend not only on delay elements but also on heat and test patterns. There is jitter with a certain distribution. In addition, the jitter distribution width is not constant, and is often different for each pin. For this reason, even when the adjustment circuit 25 adjusts the output variable delay circuit 12 and the comparison variable delay circuit 13 and the timing at which the test signal and the strobe signal are input is adjusted to the same timing for all pins, the jitter It is not possible to adjust the timing deviation due to fluctuations.
[0007]
FIG. 7 is a timing chart showing a setup test of address / data pins with respect to the clock signal (CLK) of the semiconductor device. In the semiconductor device 30, the data of the address / data pin is latched at the latch timing indicated by the dotted line in FIG. Each test signal input to the address / data pin has jitter with a certain distribution width as shown in FIG.
[0008]
In FIG. 7, the test result of the semiconductor device 30 becomes the worst condition when the test signal is the most delayed cycle, that is, the cycle located at the right end of the jitter distribution width shown in FIG. In this case, in order to determine that the semiconductor device 30 is a non-defective product, it is necessary to complete the setup within a time period from the right end time of the jitter at which the test signal is input to the latch timing time. For this reason, even if the time required for the semiconductor device 30 to be set up is within a predetermined specified time, there is a problem that the possibility of being judged as a defective product increases due to the delay of the input test signal.
[0009]
If the jitter distribution width of the test signal is different for each pin, the pin that inputs the test signal with the narrowest distribution width is tested most loosely, and the pin that inputs the test signal with the widest distribution width is It will be the most severely tested. In order to guarantee the quality of the semiconductor device 30, a test standard must be determined so as to satisfy the required specification of the semiconductor device even with a pin that is loosely tested. As a result, the semiconductor device itself is judged as a defective product even when it is a non-defective product, which causes a problem that the yield of the semiconductor device is reduced.
[0010]
The present invention solves the above-described problems and reduces the influence of jitter of test signals and strobe signals having different distribution widths for each pin generated in the signal path of the test apparatus of the semiconductor device on the test results of the semiconductor device. It is an object to provide a test method and a test apparatus for an apparatus.
[0011]
[Means for Solving the Problems]
In order to achieve the above object, a semiconductor device test apparatus according to the present invention includes a signal generation circuit that generates a plurality of test signals based on a predetermined pattern, and performs skew adjustment between the plurality of test signals. In the test apparatus for testing the semiconductor device under test, the first skew adjustment based on the test signal that rises earliest in the jitter distribution is performed by sampling a plurality of cycles of the test signal to measure the jitter distribution width. Calibration data acquisition circuit for acquiring calibration data for calibration and second calibration data for skew adjustment based on a test signal that rises the latest in the jitter distribution, and latch timing based on a reference signal in the semiconductor device under test And input / output signals input / output from the input / output pins of the semiconductor device under test A time difference between the first timing at which data is inverted immediately before the latch timing is defined as a first time difference, and the latch timing and a second timing at which data of the input / output signal is inverted immediately after the latch timing. The second time difference is a second time difference. When the first time difference is smaller than the second time difference, the first skew adjustment calibration data is selected, and the second time difference is the first time difference. And a calibration data selection circuit for selecting the second skew adjustment calibration data when the time difference is smaller than.
[0012]
In the test apparatus of the present invention, the first skew adjustment calibration data is acquired at a timing at which the test signal rising fastest in the jitter distribution becomes an intermediate level between the level before rising and the level after rising. Configuration can be used. The second skew adjustment calibration data may employ a configuration in which the test signal that rises the latest in the jitter distribution is acquired at a timing that is an intermediate level between the level before rising and the level after rising.
[0013]
In the test apparatus of the present invention, the calibration data acquisition circuit includes a third skew adjustment based on a timing that is the center of the jitter distribution at an intermediate level between the level before the rise of the test signal and the level after the rise. It is possible to adopt a configuration for acquiring calibration data for the printer.
[0014]
In the test apparatus of the present invention, the test signal may be a test signal input to the semiconductor device under test. The test signal may be a strobe signal that determines the binarization timing of the signal output from the semiconductor device under test.
[0022]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, with reference to the drawings, the present invention will be described in more detail based on exemplary embodiments of the present invention. FIG. 1 is a block diagram showing the configuration of a semiconductor device test apparatus according to an embodiment of the present invention. The semiconductor device test apparatus 10 includes an output variable delay circuit 12, a comparison variable delay circuit 13, an output circuit 14, a comparison circuit 15, a relay 22, a relay 23, and a relay 24, the number of pins (n ), And further includes a signal generation circuit 11, a determination circuit 21, a calibration data selection circuit 16, a calibration data storage device 17, a calibration data acquisition circuit 18, and a reference output circuit 20. . The n input / output pins of the semiconductor device 30 to be tested are connected to the corresponding output circuit 14 and comparison circuit 15.
[0023]
The signal generation circuit 11 generates a test signal and a strobe signal based on a predetermined pattern. The test signal generated by the signal generation circuit 11 is delayed by the output variable delay circuit 13 and input to the semiconductor device 30 via the output circuit 14 such as a driver. The output of the semiconductor device 30 based on the test signal is binarized at the timing of the strobe signal delayed by the comparison variable delay circuit 13 in the comparison circuit 15 such as a comparator, and is input to the determination circuit 21. The determination circuit 21 determines whether or not the signal input from the comparison circuit 15 is the same as a predetermined expected value determined by the test signal pattern.
[0024]
The measuring instrument 19 observes the waveform of the test signal input to the semiconductor device 30 and the waveform of the pulse signal having a predetermined cycle output from the reference output circuit 20 with an oscilloscope or the like. The calibration data acquisition circuit 18 grasps the jitter and skew of the test signal and the strobe signal based on the measurement result of the measuring device 19 and the determination result of the output of the comparison circuit 15 in the determination device 21. The calibration data acquisition circuit 18 controls the delay amounts of the output variable delay circuit 12 and the comparison variable delay circuit 13 based on the grasped jitter and skew of the test signal and the strobe signal, and calibrates these delay amounts. To obtain as action data.
[0025]
The calibration data acquired by the calibration acquisition circuit 18 includes the following three data for each of the test signal and the strobe signal. Each calibration data is stored in the calibration data storage device 17. The calibration data selection circuit 16 selects any one of the three calibration data stored in the calibration data storage device 17 when the semiconductor device 30 is tested, and the comparison variable delay circuit 12 and the comparison variable delay. The delay amount of the circuit 13 is controlled.
[0026]
FIG. 2 shows an example of a waveform observed by the measuring instrument 19, where (a) shows a waveform before timing adjustment, and (b), (c), and (d) show waveforms after timing adjustment, respectively. . Hereinafter, the three calibration data described above will be described with reference to FIGS. 1 and 2. When acquiring calibration data for a test signal, each relay 24 in FIG. 1 is turned on, and the measuring instrument 19 observes the test signal at each pin of the semiconductor device 30. As shown in FIG. 2A, the observed waveform of the test signal has jitter and skew for each pin. The measuring device 19 samples the test signal a plurality of times, measures the skew amount and the jitter distribution width at each pin, and inputs the measurement results to the calibration data acquisition circuit 18.
[0027]
The calibration data acquisition circuit 18 has a predetermined point (predetermined ratio position in the jitter width) of the test signal at the same reference timing as the reference based on the input jitter distribution width and skew amount. As described above, skew adjustment is performed by controlling the delay amount of each variable delay circuit 12. The predetermined points include the following three points. The first point is an intermediate point (50%) between the rise (L level) and the rise (H level) of the test signal in the cycle in which the test signal rises earliest, and the second point is The third point is an intermediate point between the L level and the H level in the cycle in which the test signal rises most slowly. The reference timing is generated using a reference periodic signal that is a periodic pulse signal output from the reference output circuit 20.
[0028]
When the skew is adjusted at the first point, as shown in FIG. 2B, the cycle in which the test signal at each pin rises earliest (the left end toward the paper surface, hereinafter simply the left end) has the same timing. Similarly, when the skew is adjusted at the second point, as shown in FIG. 2C, the center of the jitter distribution width of the test signal has the same timing, and when the skew is adjusted at the third point, As shown in FIG. 4D, the test signal has the same timing in the cycle in which it rises the latest (the right end toward the paper surface, hereinafter simply the right end). The delay amount of each comparison variable delay circuit 13 adjusted by the skew adjustment is divided into three points and stored in the calibration data storage device 17 as calibration data of the test signal.
[0029]
When acquiring the calibration data for the strobe signal, each relay 23 in FIG. 1 is turned ON, and the reference periodicity signal output from the reference output circuit 20 is input to the comparison circuit 15. The comparison variable delay circuit 13 changes the delay amount given to the strobe signal at a minute time interval, and supplies the strobe signal whose timing is changed to the comparison circuit 15. The determination circuit 21 receives the periodic signal binarized at the timing of the strobe signal, and performs time comparison between the signal change point of the binarized signal and the signal change point of the reference periodic signal a plurality of times. Thus, the skew and jitter of the strobe signal are grasped.
[0030]
Based on the jitter distribution width and the amount of skew grasped by the determination circuit 21, the calibration data acquisition circuit 18 makes each comparison variable so that the above three points similar to the test signal have the same timing. The delay amount of the delay circuit 13 is acquired. The obtained delay amount of each comparison variable delay circuit 13 is divided into three points and stored in the calibration data storage device 17 as calibration data for the strobe signal.
[0031]
FIG. 3 is a flowchart showing an operation procedure of the test apparatus for the semiconductor device of FIG. Hereinafter, a method for testing a semiconductor device according to an embodiment of the present invention will be described with reference to FIGS. When testing the semiconductor device, the calibration data acquisition circuit 18 matches the calibration data that matches the right end (FIG. 2B) and the center (FIG. 2C) of the jitter distribution width of the strobe signal at each pin. The calibration data and the calibration data for matching the left end (FIG. 2D) are acquired, and each of them is stored in the calibration data storage device 17 (step S1 in FIG. 3). Similarly, for the test signal, the calibration data acquisition circuit 18 acquires calibration data that matches the right end, the center, and the left end of the jitter distribution width at each pin, and stores each of them in the calibration data storage device 17. (Step S2).
[0032]
The operator of the test apparatus 10 sets a condition setting file, a switch, or the like according to test conditions such as a test program that defines a test signal pattern, and from among the acquired calibration data for each of the test signal and the strobe signal. Then, calibration data used for the test is selected (step S3). The output variable delay circuit 12 and the comparison variable delay circuit 13 control the delay amount according to the calibration data selected by the calibration data selection circuit 16 to match any of the right end, the center, or the left end (step S4). The test target semiconductor device 30 is tested by a test signal and a strobe signal controlled by an appropriate delay amount (step S5).
[0033]
In the present embodiment example, each signal generated in the signal path for inputting the test signal of the test apparatus 10 of the semiconductor device to the output circuit 14 or the signal path for inputting the strobe signal to the comparison circuit 15 is not constant for each pin. The jitter having a non-distributed width is adjusted so that any one of the right end, center, and left end of the distribution width has the same timing. For this reason, in a test of a semiconductor device that requires high timing accuracy, a highly accurate test can be performed, and the influence of jitter on the test result of the semiconductor device can be reduced. In addition, since it is not necessary to tighten the standard value that is a non-defective product in consideration of poor timing accuracy, the yield of the semiconductor device to be tested is improved.
[0034]
In the above-described embodiment, the example in which the operator of the test apparatus 10 selects the calibration data to be used has been described. However, the calibration data is automatically recognized by the test apparatus 10 as to the waveform mode (modulation) of the test signal, Calibration data set in advance in association with the waveform mode may be selected. In addition, the test apparatus 10 tests each of the three calibration data at the right end, the center, and the left end, and automatically evaluates data having the best characteristics such as yield and derivation among the three, and evaluates the evaluation. Calibration data can also be selected based on the results.
[0035]
Of the three, the selection of which calibration data to use can be made by the timing difference between the latch timing for latching the data of the address / data pin and the inversion timing of the data at the address / data pin. FIG. 4 is a timing chart showing an address / data pin setup test with respect to the clock signal (CLK) of the semiconductor device. The latch timing indicated by a dotted line in the figure is determined with reference to a pin to which CLK or the like is input. In the example shown in the figure, the latch timing is a timing at which the falling edge of the clock signal becomes 50%.
[0036]
In the address / data pin, the time a is the difference between the latch timing and the timing A in FIG. 4 which is the timing at which data is inverted immediately before the latch timing when there is no jitter. The difference between the latch timing and the timing B shown in the figure, which is the timing at which data is inverted immediately after the latch timing when there is no jitter, is defined as time b. When testing the semiconductor device 30, the time a determined based on the test program is compared with the time b, and calibration data to be used for the test signal and the strobe signal is selected according to the following conditions.
When a <b: Calibration data for matching the right end When a = b: Calibration data for aligning the center When a> b: Calibration data for matching the left end By selecting the calibration data to be performed, a highly accurate test can be performed.
[0037]
The above-mentioned calibration data may be selected by adjusting the right end, the center, or the left end of the jitter distribution width for all pins to the reference timing. The left end may be adjusted to the reference timing. In the above example, the calibration data to be used is selected by comparing the time a and the time b determined based on the test program, but instead of this, the address / The time difference up to the timing of the change point at which the data pin data inversion is most advanced (the right end of jitter) is time a ′, and the inversion of the address / data pin data is the most immediately after the latch timing and the latch timing. Measure time a ′ and time b ′ for each pin, with the time difference as the time b ′ until the timing of the change point that becomes the delayed cycle (the left end of jitter), and the right end for each pin based on the magnitude relationship of the time In addition, it is possible to select calibration data in which the center or the left end is matched with the same timing. In addition, the example in which the jitter distribution width and the signal change point are determined by using an intermediate value (50%) between the H level and the L level has been described. The value of can also be adopted.
[0038]
Although the present invention has been described based on the preferred embodiments thereof, the semiconductor device test method and test apparatus of the present invention are not limited to the above embodiments, and the configuration of the above embodiments. A test method and a test method for a semiconductor device subjected to various modifications and changes are included in the scope of the present invention. For example, the measuring device 19 may be a comparator in a semiconductor device test apparatus in addition to an oscilloscope.
[0039]
【The invention's effect】
As described above, in the semiconductor device test method and test apparatus according to the present invention, the skew of the test signal or the strobe signal is adjusted so that the predetermined ratio position of the jitter distribution width has the same timing. For this reason, the influence of the jitter of the test signal or strobe signal on the test result of the semiconductor device to be tested can be reduced, and when the test signal or strobe signal is supplied at the most advanced timing due to the jitter, or the most delayed Improves accuracy of test items that are critical when supplied at the timing.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a configuration of a test apparatus for a semiconductor device according to an embodiment of the present invention.
FIGS. 2A and 2B show (a) before adjustment, (b) when adjusting at the left end of jitter, and (c) when adjusting at the center of jitter in each pin of the semiconductor device to be tested. The timing chart which shows each signal waveform when adjusting at the right end of jitter.
FIG. 3 is a flowchart showing a procedure of a test method for a semiconductor device according to an embodiment of the present invention.
FIG. 4 is a timing chart showing signal waveforms of a reference pin and an address / data pin.
FIG. 5 is a block diagram showing a configuration of a conventional semiconductor device testing apparatus.
6A and 6B are timing charts showing signal waveforms before skew adjustment, and FIG. 6B after skew adjustment, at each pin of a semiconductor device to be tested, respectively.
FIG. 7 is a timing chart showing signal waveforms of a reference pin and an address / data pin.
[Explanation of symbols]
10: Semiconductor test apparatus 11: Signal generation circuit 12: Output variable delay circuit 13: Comparison variable delay circuit 14: Output circuit 15: Comparison circuit 16: Calibration data selection circuit 17: Calibration data storage device 18: Calibration data acquisition Circuit 19: Measuring instrument 20: Reference output circuit 21: Determination circuits 22, 23, 24: Relay 25: Adjustment circuit

Claims (6)

In a test apparatus that includes a signal generation circuit that generates a plurality of test signals based on a predetermined pattern, performs a skew adjustment between the plurality of test signals, and tests a semiconductor device under test .
Sampling for a plurality of cycles of the test signal to measure the jitter distribution width, and the first skew adjustment calibration data based on the test signal that rises earliest in the jitter distribution and the test that rises latest in the jitter distribution A calibration data acquisition circuit for acquiring second calibration data for skew adjustment based on the signal for use;
Between the latch timing based on the reference signal in the semiconductor device under test and the first timing at which the data of the input / output signal input / output from the input / output pin of the semiconductor device under test is inverted immediately before the latch timing. The time difference is the first time difference, the time difference between the latch timing and the second timing at which the data of the input / output signal is inverted immediately after the latch timing is the second time difference, and the first time difference is When the second time difference is smaller than the second time difference, the first skew adjustment calibration data is selected. When the second time difference is smaller than the first time difference, the second skew adjustment calibration data is selected. And a calibration data selection circuit for performing the test. The first skew adjustment calibration data is acquired at a timing at which the test signal rising fastest in the jitter distribution becomes an intermediate level between a level before rising and a level after rising. Item 2. The test apparatus according to Item 1. The second calibration data for skew adjustment is acquired at a timing at which the test signal rising most slowly in the jitter distribution becomes an intermediate level between a level before rising and a level after rising. Item 2. The test apparatus according to Item 1. The calibration data acquisition circuit acquires third skew adjustment calibration data based on a timing that is the center of the jitter distribution at an intermediate level between a level before rising and a level after rising of the test signal. The test apparatus according to claim 1, wherein: The test apparatus according to claim 1, wherein the test signal is a test signal input to the semiconductor device under test. 2. The test apparatus according to claim 1, wherein the test signal is a strobe signal that determines a binarization timing of a signal output from the semiconductor device under test.

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