JP3996765B2 - Thin film capacitor manufacturing method - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a thin film capacitor in which a dielectric layer is formed by a thin film technique, and more particularly to a method for manufacturing a low-capacity thin film capacitor having a high self-resonance frequency and low loss even at a high frequency.
[0002]
[Prior art]
One type of capacitor is a thin film capacitor in which an electrode layer and a dielectric layer, which are constituent elements of the capacitor, are formed of a thin film. In general, a thin film-like lower electrode layer, a dielectric layer, and an upper electrode layer are laminated in this order on an electrically insulating support substrate. In such a thin film capacitor, the lower electrode layer and the upper electrode layer are formed by sputtering, vacuum deposition, or the like, respectively, and the dielectric layer is also formed by sputtering, sol-gel method, or the like. In manufacturing such a thin film capacitor, a photolithography technique is usually used as follows. First, after forming a conductor layer to be a lower electrode layer on the entire surface of the insulating support substrate, only necessary portions are covered with a resist, and then unnecessary portions are removed by wet etching or dry etching to form a lower portion of a predetermined shape. An electrode layer is formed. Next, a dielectric layer to be a thin film dielectric layer is formed on the entire surface of the support substrate, and unnecessary portions are removed to form a thin film dielectric layer having a predetermined shape in the same manner as the lower electrode layer. Finally, a conductor layer to be an upper electrode layer is formed on the entire surface, and unnecessary portions are removed to form an upper electrode layer having a predetermined shape. Also, surface mounting is possible by forming a protective layer and solder bumps. In addition, as a material of the thin film dielectric layer, a dielectric material made of (Ba _x Sr _1-x ) _y Ti _1-y O ₃ is used, and a predetermined potential is applied between the upper electrode layer and the lower electrode layer. A tunable thin film capacitor that controls the capacitance by changing the dielectric constant of the dielectric layer has the same structure.
[0003]
In order to use a thin film capacitor as a capacitor in a high frequency circuit, for example, the self-resonant frequency needs to be located on the high frequency side from the frequency used. Such a thin film capacitor can be obtained by reducing the inductance in the lower electrode layer and the upper electrode layer. A thin film capacitor having a small inductance is disclosed in, for example, Japanese Patent Application Laid-Open No. 8-241830.
[0004]
[Problems to be solved by the invention]
As described above, in order to use a thin film capacitor as a capacitor in a high frequency circuit, the self-resonant frequency needs to be located on the high frequency side with respect to the frequency used, and it is necessary that the inductance is small. The loss of the layer and the upper electrode layer must also be low. This is because even if the resonance point is on the higher frequency side than the frequency at which the capacitor is used, the impedance due to the capacitor is small at the frequency near the resonance point, so that the resistance component is dominant in the capacitor having a large loss. Therefore, in order to reduce the loss due to the lower electrode layer and the upper electrode layer, it is necessary to use a metal having a low resistivity and to make the lower electrode layer and the upper electrode layer as thick as possible.
[0005]
In addition, by reducing the capacitance of the capacitor, the self-resonant frequency can be shifted to the higher frequency side, and the increase in loss due to the influence of resonance can be reduced. To reduce the capacitance of the capacitor, it is necessary to reduce the plane area of the capacitance generation region composed of the lower electrode layer and the thin film dielectric layer sandwiched between the upper electrode layer, but to reduce the capacitor plane area. As a result, a step that degrades the leakage characteristics is generated in the dielectric portion constituting the capacitor, and the reliability is lowered. In addition, the accuracy of alignment in the manufacturing process becomes strict, resulting in a decrease in yield.
[0006]
Further, increasing the thickness of the electrode layer in order to reduce the loss due to the electrode layer described above further increases the level difference.
[0007]
Also, in conventional thin film capacitors, even when a low melting point metal is used as an electrode or a high melting point metal is used, the microstructure is not taken into account, resulting in poor adhesion, resulting in reliability. It is supposed to be inferior in moisture resistance.
[0008]
The present invention has been devised in view of the above-mentioned problems, and its purpose is that the electrode loss of the lower electrode layer and the upper electrode is small, and the plane area of the capacitance generation region needs to be aligned accurately. An object of the present invention is to provide a thin film capacitor that can be formed with high accuracy without any problems, simplifies the process.
[0009]
It is another object of the present invention to provide a thin film capacitor that eliminates a step, improves reliability, improves adhesion between a substrate, an electrode, and a dielectric, and has improved moisture resistance.
[0010]
[Means for Solving the Problems]
In the method of manufacturing a thin film capacitor of the present invention, a lower electrode layer, a thin film dielectric layer, and an upper electrode layer are formed in the same batch on the entire surface of the support substrate, and then a resist layer having a predetermined shape is formed on the upper electrode layer. Using the resist layer, the upper electrode layer and a part of the thin film dielectric layer are sequentially etched by argon etching or the like so that the thin film dielectric layer and the upper electrode layer have the same plane area and shape. In the method of manufacturing a thin film capacitor to be formed, after the lower electrode layer is formed at a temperature lower than the film formation temperature of the thin film dielectric layer by 150 ° C. or more , the film is heated to the film formation temperature of the thin film dielectric layer, A flat lower electrode layer is obtained by annealing for a certain period of time until the thin film dielectric layer starts to be formed .
[0011]
Further, the lower electrode layer has a protrusion having the same shape and area as the upper electrode layer and the thin film dielectric layer immediately below the thin film dielectric layer.
[0012]
An insulating layer is disposed around the protrusion of the lower electrode layer, the thin film dielectric layer, and the upper electrode layer.
The thin film dielectric layer is made of a perovskite oxide crystal containing at least Ba, Sr, and Ti .
The thin film dielectric layer has a dielectric layer made of at least one of SiOx or SiNx interposed at the interface between the lower electrode and the upper electrode layer.
Further, the insulator layer is made of SiOx or SiNx.
Further, flat Pt or Pd is used as the lower electrode layer.
The lower electrode layer is made of any of Au, Ag, and Cu, and one layer of either Pt or Pd is interposed at the interface between the support substrate and the dielectric layer.
The lower electrode layer is made of either Pt or Pd and an Au alloy.
The upper electrode layer has a two-layer structure composed of either Pt or Pd and Au from the thin film dielectric layer side.
The upper electrode layer has a three-layer structure of either a Pt or Pd metal layer, a Cu or Ag metal layer, and a metal layer made of Au from the thin film dielectric side.
[0014]
In addition, after forming a metal layer comprising at least Pt or Pd out of the metal layer constituting the lower electrode layer or the upper electrode layer at a temperature lower than the film formation temperature of the thin film dielectric layer, the thin film dielectric thin layer is formed. A thin film capacitor manufacturing method characterized in that a flat electrode is obtained by heating to a temperature.
[0015]
In addition, after preparing the lower electrode layer, thin film dielectric layer, and upper electrode layer having a predetermined shape, an insulating layer is formed on the entire surface of the support substrate by sputtering or the like, and etched using a resist film having a window larger than the upper electrode. A method for manufacturing a thin film capacitor, characterized in that an insulating layer having a predetermined shape is obtained.
[0016]
The lower electrode layer of a predetermined shape, the thin-film dielectric layer was fabricated upper electrode layer, the entire surface of the substrate to the insulating layer is deposited by sputtering or the like, by performing the error etching to the upper electrode layer is exposed, the resist layer A thin film capacitor manufacturing method characterized by obtaining an insulating layer having a predetermined shape without using it. In addition, after the lower electrode layer, the thin film dielectric layer, and the upper electrode layer are formed, an insulating layer is formed on the entire surface of the support substrate by sputtering or the like, and etching is performed between the insulating layer on the upper electrode layer and the surrounding insulating layer. The method of manufacturing a thin film capacitor is characterized in that the insulating layer on the upper electrode layer is removed at the time when is divided.
[0017]
Thereby, the thickness of the upper electrode and the lower electrode can be increased, and the loss due to the electrodes can be reduced. Further, since the thin film dielectric layer exists only directly below the upper electrode layer, and the shape and the planar area of the thin film dielectric layer and the upper electrode layer are equal, the capacitance of the capacitor element can be accurately controlled.
[0018]
In addition, since the lower electrode layer has a protrusion having a shape and a planar area equal to those of the upper electrode layer and the thin film dielectric layer immediately below the thin film dielectric layer, the capacitance of the capacitor element can be controlled more accurately.
[0019]
Furthermore, in the above structure, after forming the lower electrode layer, the thin film dielectric layer, and the upper electrode layer on the entire surface of the support substrate, a resist layer having a predetermined shape is formed on the upper electrode layer, and the same resist layer is used. Then, the upper electrode layer and the thin film dielectric layer are physically etched sequentially by argon etching or the like to form the protrusions of the lower electrode layer, the thin film dielectric layer, and the upper electrode layer having the same flat area and shape. The lower electrode layer, the dielectric layer, and the upper electrode layer can be formed by sputtering in one batch. After forming the lower electrode, it is not necessary to expose to the atmosphere after forming the dielectric, so that adhesion of moisture, fats and oils will not occur on the film surface, and adhesion between the electrode and dielectric can be greatly improved, Since adhesion can be improved, moisture resistance is improved, and reliability as a capacitor element is also improved. Moreover, since the same resist can be used for one batch of sputtering and etching of the upper electrode layer and the thin film dielectric layer, the thin film capacitor manufacturing process is greatly simplified.
[0020]
In addition, since the insulator layer is disposed around the protrusion of the lower electrode layer, the thin film dielectric layer, and the upper electrode layer, the dielectric layer is directly surrounded by the insulator layer. As a result, the dielectric side surface is sealed with an insulating layer having good adhesion to the dielectric, so that the moisture resistance of the dielectric side surface is improved and the reliability as a capacitor element is improved.
[0021]
Such an insulating layer is a resist film having a lower electrode layer, a thin film dielectric layer, and an upper electrode layer having a predetermined shape, and then an insulating layer is formed on the entire surface of the substrate by sputtering or the like, and has a window larger than the upper electrode. It can be manufactured by performing etching using.
[0022]
Furthermore, after forming a lower electrode layer, a thin film dielectric layer, and an upper electrode layer having a predetermined shape, an insulating layer is formed on the entire surface of the substrate by sputtering or the like, and physically etched without using a resist layer. Fabrication is also possible by obtaining an insulating layer having a predetermined shape.
[0023]
Further, since the thin film dielectric layer is a thin film capacitor characterized by comprising a perovskite oxide crystal containing at least Ba, Sr, and Ti, the loss of the dielectric itself can be reduced. A tunable thin film capacitor whose dielectric constant can be changed by applying an external voltage can also be used. In particular, a DC bias is applied to the lower electrode layer and the upper electrode layer, but by increasing the thickness of the electrode in the capacity generation region, there is no bias bias and stable dielectric constant control is possible.
[0024]
When D1 is SiO _x or SiN _x and D2 is (Ba _x Sr _1-x ) _y Ti _1-y O ₃ , three layers of D1 / D2 / D1 are formed as the thin film dielectric layer from the lower electrode side. By using the structure, the upper and lower sides of (Ba _x Sr _1-x ) _y Ti _1-y O ₃ are sandwiched by an insulating layer such as SiO _x or SiN _x that has better adhesion than the metal layer. The moisture resistance is improved and the reliability as a capacitor element can be improved.
[0025]
Further, since the insulator layer is made of SiO _x or SiN _x , the moisture resistance of the thin film dielectric layer is improved, and furthermore, these low dielectric constant insulator layers are located on the side surfaces of the thin film dielectric layer. Therefore, the generation of stray capacitance can be reduced.
[0026]
Further, by using flat Pt or Pd as the lower electrode layer, the adhesion with the thin film dielectric layer is improved, and the unevenness of the thin film dielectric layer is reduced, so that the breakdown voltage is high and the leakage current is reduced. , Leading to improved reliability. In addition, since these metals have a high melting point, a thin film dielectric layer can be formed immediately after film formation at a high temperature, forming a thin film dielectric layer that is dense, has few oxygen defects, and has low loss. can do. Further, in the production of a tunable thin film capacitor, a thin film dielectric having a large change rate of dielectric constant can be formed.
[0027]
In addition, when Me1 is Pt or Pd and Me2 is either Au, Ag, or Cu, a three-layer structure of Me1 / Me2 / Me1 from the support substrate side is used as the lower electrode layer, and at least the thin film dielectric side The flat Me1 layer enables the formation of a thin film dielectric layer that is dense, has few oxygen defects, and has a small loss. In addition to being able to form a dielectric, it is possible to produce an electrode layer that has good adhesion to the support substrate and the thin film dielectric layer, is inexpensive, and has a low resistivity.
Also, when Me is Pt or Pd, by using a flat Me-Au alloy as the lower electrode layer, it is more stable and has good adhesion to the support substrate and the thin film dielectric layer. An electrode layer with a low rate can be manufactured.
[0028]
In addition, when Me is Pt or Pd, the upper electrode layer uses a two-layer structure of Me / Au from the thin film dielectric layer side, so that it has good adhesion to the thin film dielectric layer, and the insulator layer and Can produce an upper electrode layer with poor adhesion. When the insulating layer is manufactured by the above-described method, the insulating layer on the upper electrode having poor adhesion can be completely removed. Further, since the upper electrode layer having a low resistivity can be manufactured, the loss as a thin film capacitor can be reduced.
[0029]
In addition, when Me1 is Pt or Pd, Me2 is Cu, and Ag, the upper electrode layer is made of a three-layer structure of Me1 / Me2 / Au from the dielectric side as the upper electrode layer. I can do it.
[0030]
After forming at least the Pt and Pd layers of the metal layer constituting the electrode layer at a temperature lower than the film formation temperature of the thin film dielectric layer, the film is heated to the film formation temperature of the thin film dielectric layer to form the thin film dielectric layer Although a flat electrode can be obtained by holding for a certain period of time until the start of film formation , this method eliminates the need to remove the sample from the chamber and perform annealing after forming the metal layer once. Film formation and annealing can be performed in the same batch.
[0031]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, the thin film capacitor of the present invention will be described in detail with reference to the drawings.
[0032]
FIG. 1 shows a cross section of a thin film capacitor of the present invention. FIG. 2 is an enlarged cross-sectional view of the capacitance generation region portion of the circled portion in FIG. 1, and FIG. 3 is a plan view of the state where the protective film is omitted.
[0033]
In the figure, 1 is a support substrate, 2 is a lower electrode layer, 3 is a thin film dielectric layer, 4 is an upper electrode layer, 6 is an upper lead electrode, 7 is a protective layer, 8 , 9 are terminal portions. An insulator layer 5 is disposed around the thin film dielectric layer 3 and the upper electrode layer 4.
[0034]
The support substrate 1 is a ceramic substrate such as alumina, a single crystal substrate such as sapphire, or the like. A lower electrode layer 2 is formed on the surface of the support substrate 1. The lower electrode layer 2, the thin film dielectric layer 3, and the upper electrode layer 4 are formed in the same batch on the entire surface of the support substrate. After the sputtering of all layers, the thin film dielectric layer 3 and the upper electrode layer 4 are first formed into a predetermined shape. The resist layer is physically etched into the same shape, and then the lower electrode layer 2 is physically or chemically etched using a resist layer having a predetermined shape.
[0035]
The lower electrode layer 2 is made of Pt, which has a high melting point and is a noble metal because high temperature sputtering is required for forming the thin film dielectric layer 3. The lower electrode layer 2 is formed at a substrate temperature of 150 ° C. to 600 ° C., for example. Thereafter, the thin film dielectric layer 3 is heated to 700 to 900 ° C., which is the sputtering temperature, and is held for a certain time until the start of sputtering, thereby forming a flat thin film. In FIG. 1, reference numeral 21 denotes a terminal arrangement portion that extends a part of the lower electrode layer 2 to a portion where the terminal portion 9 is formed.
[0036]
The thickness of the lower electrode layer 2 includes the resistance component from the terminal portion 9 to the capacity generation region, the continuity of the lower electrode layer 2 (all of which are desirable to be thicker), and the adhesion to the support substrate 1 (thickness is relative). For example, the thickness is 0.1 to 10 μm. For example, when the thickness is smaller than 0.1 μm, the resistance of the electrode itself increases, and at the same time, the continuity of the electrode is lost and the reliability is deteriorated. On the other hand, if it is 10 μm or more, the adhesion reliability with the support substrate 1 is lowered.
[0037]
The metal material constituting the lower electrode layer 2 may have a three-layer structure in which Au, Ag, Cu, or the like is applied in addition to the high melting point noble metals Pt and Pd.
[0038]
The thin film dielectric layer 3 is a high dielectric constant dielectric layer made of perovskite oxide crystal particles containing at least Ba, Sr, and Ti. The thin film dielectric layer 3 is formed on the surface of the lower electrode layer 2 described above. For example, sputtering is performed using a dielectric from which perovskite-type oxide crystal particles are obtained as a target. For example, the substrate temperature is set to 800 ° C., and film formation is performed only for a time considering the thickness. By performing sputtering at a high temperature, a thin film dielectric layer having a high dielectric constant and low loss can be obtained without performing a heat treatment after sputtering.
[0039]
As the material of the upper electrode layer 4, Au having a low resistivity is desirable in order to reduce the resistance of the electrode. In addition, Ag, Cu, etc. can be used, but in order to improve the adhesion with the thin film dielectric layer, Pt, A high melting point noble metal such as Pd is desirable. The upper electrode layer 4 has a thickness of 0.1 to 10 μm. The lower limit of the thickness is set in consideration of the resistance of the electrode itself, similarly to the lower electrode layer 2. Further, the upper limit of the thickness is set in consideration of a decrease in adhesion. In FIG. 1, reference numerals 61 and 62 denote terminals in which a part of the upper electrode layer 4 extends or is formed in the same process, and extends to a portion where the terminal portions 8 and 9 are formed. Arrangement part.
In the thin film capacitor of the present invention, as described above, the lower electrode layer 2, the thin film dielectric layer 3, and the upper electrode layer 4 can be formed by sputtering in the same batch, and the upper electrode layer can be formed without being exposed to the atmosphere. Since there is no extra adhesion of oil and fat between the lower electrode layer and the thin film dielectric layer and between the thin film dielectric layer and the upper electrode layer, the adhesion is greatly improved, and the lower electrode layer and the thin film dielectric layer and the thin film dielectric Infiltration of moisture and the like between the body layer and the upper electrode layer can be prevented, and the moisture resistance can be greatly improved.
[0040]
The insulating layer 5 is formed around the protrusions of the lower electrode layer 2, the thin film dielectric layer 3, and the upper electrode layer 4, and the material is ceramics such as SiO ₂ and Si ₃ N ₄ .
Such an insulating layer 5 is formed on the lower electrode layer 2, the upper electrode layer 4, and the support substrate 1, for example, and unnecessary portions are removed by dry etching so that only the upper surface of the upper electrode layer 4 is exposed. The state of film formation and etching is shown in FIG. When the insulating layer 5 is formed by sputtering, since the target constituent material is released in various directions from a certain point of the target, the target constituent material flying from various directions is deposited on a certain point on the substrate. Will do. However, in dry etching, etching is performed by ions accelerated between electrodes of an etching apparatus placed in parallel, so that etching proceeds in a direction perpendicular to the film. In the present invention, Au having poor adhesion to the insulating layer is used for the uppermost surface of the upper electrode layer, and when the insulating layer on the upper electrode layer and the surrounding insulating layer are completely divided during etching. The insulating layer on the upper electrode layer can be automatically removed. If it cannot be removed for some reason, it can be completely removed by ultrasonic cleaning or heating at about 300 ° C. In such a method, the size and alignment accuracy of the resist layer are not important, and a resist layer having a window larger than that of the upper electrode may be used. The same processing can be performed without using any resist. The upper electrode layer and the insulating layer around the thin film dielectric layer are also etched during etching, which may cause stray capacitance, so it is desirable that the initial insulating layer is thicker.
[0041]
The insulating layer 5 is formed so as to expose at least the terminal arrangement portion where the terminal portions 8 and 9 are formed.
[0042]
The upper lead electrode layer 6 is formed to connect the upper electrode layer and the terminal arrangement portion. An inexpensive and low resistance metal such as Ag or Cu can be used for the upper extraction electrode. The size is determined in consideration of stray capacitance and resistance.
[0043]
Further, the protective film 7 is formed so as to expose the terminal arrangement portions 61 and 62. As the protective film, SiO ₂ , SiN, BCB (benzocyclobutene), polyimide and the like are suitable. Further, a multilayer structure of these materials may be used. The protective film 6 has a role of preventing deterioration due to humidity, chemical contamination, oxidation, and the like in addition to protection from external mechanical shocks.
[0044]
The terminal portions 8 and 9 can be exemplified by solder balls and metal bumps. Alternatively, bumps such as gold may be formed by performing first bonding of a metal wire and cutting it at a predetermined length.
[0045]
As described above, in the above-described thin film capacitor, the capacitance generation region is the thin film dielectric layer 3 portion sandwiched between the lower electrode layer 2 and the upper electrode layer 4, and the upper electrode layer using the same resist layer, It is formed by etching a thin film dielectric layer. At this time, only the lower electrode layer 2, the thin film dielectric layer 3, and the upper electrode layer 4 are formed on the entire surface of the support substrate 1, and the lower electrode layer 2 is accurately formed without any restrictions. The protrusion, the thin film dielectric layer 3 and the upper electrode layer 4 can be formed. Accordingly, it is easy to reduce the plane area of the capacitance generation region, and a capacitor used in a high frequency circuit can be easily achieved.
[0046]
Moreover, since the thin film dielectric layer 3 can be deposited on the flat surface of the lower electrode layer 2 without any step, a step breakage occurs in the thin film dielectric layer 3, and a step occurs in the upper electrode layer 4. There will be no cuts.
[0047]
Although the insulating layer 5 exists, an unnecessary capacitance component may be generated between the lower electrode layer 2 and the upper electrode layer 4, but the lower electrode layer 2 and the upper electrode layer in the capacitance generation region. Compared to the distance between the capacitor generation region 4 and the upper electrode 6, the distance between the lower electrode layer 2 and the upper extraction electrode 6 around the capacitance generation region is very wide. it can. In order to further reduce unnecessary capacitance generated around the capacitance generation region, the insulating layer may be thickened. For this purpose, the upper electrode layer also needs to be thickened.
[0048]
In particular, the direct current baice is applied between the lower electrode layer 2 and the upper electrode layer 4 such as (Ba _x Sr _1-x ) TiO ₃ to the thin film dielectric layer 3, and the dielectric of the thin film dielectric layer 3. In the tunable thin film capacitor whose capacitance characteristics can be adjusted by changing the rate, the resistance component in the upper electrode layer 4 and the lower electrode layer 2 can be reduced. Therefore, it is possible to prevent variations in voltage applied to the thin film dielectric layer 3 and to obtain stable tunability.
[0049]
【Example】
Pt as the lower electrode layer 2 was formed on the sapphire R substrate as the support substrate 1 by a sputtering method at a substrate temperature of 500 ° C. The thin film dielectric layer 3 was formed in the same batch using a target made of (Ba _0.5 Sr _0.5 ) TiO ₃ . This was performed at a substrate temperature of 800 ° C. and a film formation time of 15 minutes. Before the film formation was started, annealing was performed at 800 ° C. for 15 minutes as annealing for planarizing the Pt electrode. On top of that, Pt and Au electrode layers are formed as the upper electrode layer 4 in the same batch, and after removal, a 10 μmφ resist layer is formed. The upper electrode layer and the thin film dielectric layer are etched by the ECR apparatus, and again for the lower electrode. A resist layer was formed and etched by ECR to form a thin film capacitor. After the resist layer was peeled off, a SiO ₂ layer was formed by sputtering at 600 ° C., and after the resist layer was peeled off, it was etched by ECR for about 15 minutes to remove only the SiO ₂ layer on the upper electrode layer. The SiO ₂ layer on the upper electrode layer that was not partially removed was completely removed by ultrasonic cleaning in pure water. Finally, Au was sputtered as an upper extraction electrode, and unnecessary portions were removed by etching.
As a result of measurement with an impedance analyzer, the capacitance was about 1 pF, and as a result of measurement with a picoampere meter, a leakage current was on the order of 10 ⁻¹² A, and a thin film capacitor with small capacitance and good leakage characteristics was obtained.
[0050]
That is, it was confirmed that each electrode layer and the thin film dielectric layer had no step breakage, the loss of the electrode portion was reduced, and it could be used as a stable capacitive element even in a high frequency region.
[0051]
【The invention's effect】
In the method of manufacturing a thin film capacitor according to the present invention, a lower electrode layer, a thin film dielectric layer, and an upper electrode layer are formed in the same batch on the entire surface of a support substrate, and then a resist layer having a predetermined shape is formed on the upper electrode layer. A thin film capacitor in which a part of the upper electrode layer and the thin film dielectric layer are sequentially etched by argon etching or the like to form the thin film dielectric layer and the upper electrode layer in the same plane area and shape. In the manufacturing method, the lower electrode layer is formed at 150 ° C. or more at a temperature lower than the film formation temperature of the thin film dielectric layer, and then heated to the film formation temperature of the thin film dielectric layer, A flat lower electrode layer is obtained by annealing while holding for a certain period of time until the start of film formation. An insulating layer is formed so as to surround the thin film dielectric layer.
[0052]
As a result, the thin-film dielectric layer and the upper electrode layer are not stepped, and the thickness of the upper electrode layer and the lower electrode layer in the capacity generation region can be increased as much as possible, thereby effectively suppressing electrode loss. It becomes a thin film capacitor.
[0053]
In particular, since the capacitance of the capacitor is substantially determined by the plane area of the upper electrode layer, the alignment accuracy is not required at all in the photolithography process, and stable capacitance characteristics can be obtained with certainty.
[0054]
In particular, in a tunable thin film capacitor that changes the dielectric constant of the thin film dielectric layer by applying a direct current bias to the lower electrode layer and the upper electrode, potential variation can be suppressed within the electrode.
[Brief description of the drawings]
FIG. 1 is a cross-sectional view of a thin film capacitor produced by the method for producing a thin film capacitor of the present invention.
FIG. 2 is a cross-sectional view of a main part of a thin film capacitor manufactured by the method for manufacturing a thin film capacitor of the present invention.
FIG. 3 is a plan view of a thin film capacitor in a state where a protective film and a terminal portion are omitted , manufactured by the method for manufacturing a thin film capacitor of the present invention.
FIG. 4 is an explanatory diagram of an insulating layer deposition and etching process according to the present invention.

Claims (6)

After the lower electrode layer, the thin film dielectric layer, and the upper electrode layer are formed in the same batch on the entire surface of the support substrate, a resist layer having a predetermined shape is formed on the upper electrode layer, and the upper electrode layer is formed using the same resist layer. A method of manufacturing a thin film capacitor in which a part of the thin film dielectric layer is sequentially etched to form the thin film dielectric layer and the upper electrode layer in the same plane area and shape,
After the lower electrode layer is formed at a temperature of 150 ° C. or more and lower than the film formation temperature of the thin film dielectric layer, the film is heated to the film formation temperature of the thin film dielectric layer and constant until the film formation start of the thin film dielectric layer A method for producing a thin film capacitor, characterized in that a flat lower electrode layer is obtained by annealing for a period of time. 2. The method of manufacturing a thin film capacitor according to claim 1, wherein the metal layer constituting the lower electrode layer has a metal layer made of Pt or Pd .   3. The method of manufacturing a thin film capacitor according to claim 1, wherein the thin film dielectric layer is made of a perovskite oxide crystal containing at least Ba, Sr, and Ti. The lower electrode layer, the thin film dielectric layer was fabricated the upper electrode layer, the supporting substrate over the entire surface film insulation layer is etched using a resist film having a large window than the upper electrode layer 4. The method of manufacturing a thin film capacitor according to claim 1 , wherein the insulating layer is processed into a predetermined shape . The lower electrode layer, the thin film dielectric layer was fabricated the upper electrode layer, the supporting substrate whole surface insulating layer film, by performing et etching until the upper electrode layer is exposed, the resist layer 4. The method of manufacturing a thin film capacitor according to claim 1 , wherein the insulating layer is processed into a predetermined shape without being used.   The uppermost surface of the upper electrode layer is Au,
  After forming the lower electrode layer, the thin film dielectric layer, and the upper electrode layer, an insulating layer is formed on the entire surface of the support substrate, and etching is performed to form the insulating layer on the upper electrode layer and the insulating layer around the insulating layer. 6. The method for manufacturing a thin film capacitor according to claim 1, wherein the insulating layer on the upper electrode layer is removed when the layer is separated from the upper electrode layer.

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