JP3987203B2 - Decision feedback equalizer - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to divergence prevention of a decision feedback equalizer used in a read channel IC of a hard disk device or a high-speed data communication device.
[0002]
Recording data read from a hard disk such as a magnetic disk via a read head is read as an analog read signal. This read signal is converted into a digital signal by a waveform equalizer in the read channel IC, subjected to various digital processing, and output to a data reproduction processing unit composed of a DSP, a microcomputer, etc. . In the data reproduction processing unit, the original data is reproduced based on the input recording data.
[0003]
In recent years, in order to increase the speed of reproducing such recorded data, improvement in recording density on a recording medium and improvement in digital signal processing speed have been attempted. For this reason, the waveform equalizer is also required to have stable processing and high speed.
[0004]
[Prior art]
Conventionally, an analog signal read from a hard disk via a read head is input to a read channel IC constituting the hard disk device. In the read channel IC, an input analog signal is converted into a digital signal by a waveform equalizer, and a predetermined digital decoding process is performed on the digital signal. The digital decoded signal is converted from a serial signal to a parallel signal having a predetermined number of bits and output to a host computer or the like.
[0005]
With the recent increase in the speed of read operation of recorded data, a decision feedback equalizer (DFE: Decision Feedback Equalizer) is drawing attention instead of a PRML (partial response and maximum likelihood decoding) type waveform equalizer. . The PRML waveform equalizer requires a high-precision digital filter and an equalizer filter, which are obstacles to speeding up and circuit miniaturization. On the other hand, the decision feedback equalizer has a simple circuit configuration and is suitable for high-speed operation and miniaturization.
[0006]
FIG. 53 shows a first conventional example of a decision feedback equalizer.
The DFE 11 includes a pre-filter (feedforward filter) 12, an adder 13, a determiner 14, a shift register 15, and a feedback filter 16. The prefilter 12 outputs the filtered signal to the adder 13. The adder 13 adds the output signal of the prefilter 12 and the output signal of the feedback filter 16, and outputs the addition result to the determiner 14.
[0007]
The determiner 14 compares the output voltage of the adder 13 with a preset reference voltage, and outputs a determination signal S1 of “1” or “0” to the shift register 15 based on the comparison result. As a result, the determiner 14 converts the output signal of the adder 13 into a digital signal.
[0008]
The shift register 15 includes a number of registers 15 a (eight in FIG. 53) corresponding to the number of taps of the feedback filter 16. The shift register 15 samples the determination signal S1 output from the determiner 14 in synchronization with the clock signal CLK, and sequentially stores the sampling data in each register 15a. Thereby, the shift register 15 stores the sampled past data.
[0009]
The feedback filter 16 operates so as to remove intersymbol (symbol) interference included in the signal. The feedback filter 16 calculates a feedback response, that is, an analog amount (feedback amount) of a signal output to the adder 13 based on the data stored in the shift register 15.
[0010]
More specifically, the feedback filter 16 is composed of an FIR (Finite Impulse Response) filter, and includes a multiplier 17, an adder 18, and a digital-analog converter (DAC) 19 corresponding to the number of taps. The feedback filter 16 calculates 8-bit data input from the shift register 15 in each multiplier 17 and preset filter coefficients ω7 to ω0, and adds the calculation results in the adder 18. The feedback filter 16 converts the addition result of the adder 18 into an analog signal by the DAC 19 and outputs the analog signal to the adder 13.
[0011]
Therefore, the adder 13, the determiner 14, the shift register 15, and the feedback filter 16 form a feedback loop and constitute a determination circuit. The data stored in one register of the shift register 15 is output as a reproduction signal that is a digital signal. The DFE 11 configured as described above outputs a reproduction signal from which intersymbol interference is removed.
[0012]
By the way, as described above, the DFE 11 obtains the feedback response by calculating the feedback amount by the calculator 17 and the adder 18 of the feedback filter 16. Therefore, the read speed limits the read speed as the calculation speed of each calculator 17 and adder 18. That is, the reading speed cannot be made higher than the calculation speed of the calculator 17 and the adder 18.
[0013]
FIG. 54 shows a second conventional example of a decision feedback equalizer (DFE) that can be read at a higher speed than the DFE 11 described above. The same components as those of the DFE 11 of the first conventional example shown in FIG.
[0014]
The DFE 21 includes a prefilter 12, an adder 13, a determiner 14, a shift register 15, and a feedback filter 22. The feedback filter 22 includes a decoder 23, a memory (RAM) 24, and a DAC 25. By using the RAM 24, the DFE 21 may be called a RAM-DFE.
[0015]
The RAM 24 has a plurality of areas 24a, and each area 24a stores feedback response data corresponding to an 8-bit data pattern output from the shift register 15. These data are calculation results obtained by previously calculating data stored in the shift register 15 and predetermined filter coefficients ω7 to ω0.
[0016]
Based on the data output from the shift register 15, the decoder 23 outputs an address signal for selecting one of the areas 24 a corresponding to the data pattern to the RAM 24. The RAM 24 outputs the data stored in the area 24 a selected by the input address signal to the DAC 25. The DAC 25 converts input data into an analog signal, and outputs the analog signal to the adder 13 as a feedback response.
[0017]
The feedback filter 22 configured in this way only takes time for decoding in the decoder 23 and time for reading the feedback response from the RAM 24. This total time is shorter than the calculation time in the feedback filter 16 of the DFE 11 in FIG. As a result, the DFE 21 can increase the reading speed.
[0018]
[Problems to be solved by the invention]
However, in the hard disk device, the level of the read signal (Lorentz pulse) at the magnetic change point may be lowered in the state of the recording medium or the read head, or the level necessary for the determination may not be obtained due to the influence of noise. This causes a determination error of the determiner 14, and an incorrect value is stored in the shift register 15. The feedback loop diverges due to error propagation in which this erroneous value is fed back to the adder of the feedback loop.
[0019]
At this time, the DFE 21 is in a so-called fixed state in which a reproduction signal in one state (either “0” or “1”) is continuously output. The feedback loop is stabilized in the fixed state, and is difficult to return to a normal state in which “0” and “1” are output in accordance with the input signal.
[0020]
In such a case, it takes time for the feedback loop to become normal. Therefore, since the DFE 21 outputs a reproduction signal including an error, the hard disk device must repeatedly perform a read operation on the same area of the magnetic disk. This lengthens the data read time and hinders speeding up of the read operation.
[0021]
By the way, the hard disk device manages the recording surface of the magnetic disk by tracks divided concentrically in the radial direction and sectors divided radially. The hard disk device stores the same amount of data in each sector. Accordingly, the recording density of each sector becomes higher as the sector is closer to the center of the magnetic disk. The magnetic disk is driven to rotate at a constant speed.
[0022]
Accordingly, the symbol rate (the number of bits read per unit time) of the read signal for reading various information from the magnetic disk becomes higher as the read signal is read from the sector closer to the center. That is, the frequency characteristic of the read signal changes corresponding to the position (distance from the center) of the sector from which information is read.
[0023]
In order to accurately perform the equalization process on the read signal, it is necessary to change the filter response stored in the RAM 24 of the feedback filter 22 in a short time according to the change in the frequency characteristic of the read signal. However, it takes time to rewrite all filter responses in the RAM 24 from the outside. The rewriting time hinders the speeding up of the read operation.
[0024]
  The present inventionofAn object of the present invention is to provide a decision feedback equalizer that can prevent the feedback loop from diverging and increase the reading speed.
[0026]
[Means for Solving the Problems]
  In order to achieve the above object, the invention described in claim 1A prefilter that filters and outputs an input signal, an output signal of the prefilter and a feedback signal based on a determination result stored in a shift register are added, and a signal after the addition is determined according to a determination criterion, A decision feedback equalizer including a decision circuit that sequentially stores decision results in the shift register, wherein the decision circuit includes an adder that adds the output signal of the prefilter and the feedback signal; a reference level; And determining a magnitude of the output signal of the adder with respect to the output, calculating a feedback amount based on the determination result stored in the shift register, a determination unit outputting the determination result to the shift register, and according to the feedback amount A feedback filter that outputs a feedback signal, the feedback filter including a first signal level generation circuit that generates a plurality of signal levels, and the monitoring result as an input. A first selection circuit that selects one of the plurality of signal levels based on the monitoring result and outputs the selected signal level to the determination unit as a reference level; and generates a plurality of signal levels The second signal level generation circuit and the monitoring result are input, one of the plurality of signal levels and the feedback amount based on the determination result is selected based on the monitoring result, and the selected signal is output A second selection circuit; and a DA converter that converts an output signal of the selection circuit into an analog signal and outputs the analog signal as the feedback signal..
[0036]
  Claim2The invention described in claim 11In the decision feedback equalizer described in 1), the register length of the shift register is made to correspond to the sign rule of the input signal.
[0037]
  Claim3The invention described in claim 11 or claim 2The decision feedback equalizer according to claim 1, wherein the shift register includes a first register unit including a number of registers corresponding to the number of taps of the feedback filter, and a second register unit including a plurality of registers. It was done.
[0038]
  Claim4The invention described in claim 11In the decision feedback equalizer according to claim 1, when the judgment error based on the judgment criterion exists locally in the shift register, the monitoring circuit outputs a feedback signal based on the error. .
[0066]
  (Function)
Claim1According to the invention described in the above, based on the monitoring result of the monitoring circuit that monitors the contents of the shift register,One of the plurality of signal levels generated by the first signal level generation circuit is selected and output to the determiner as a reference level, and determined as the plurality of signal levels generated by the second signal level generation circuit Select one of the feedback amounts based on the result, convert the selected signal into an analog signal and output it as a feedback signalAs a result, the sticking is eliminated and the divergence of the feedback filter is stopped.
[0067]
  Claim2,3According to the invention described in (3), the register length of the shift register is made to correspond to the sign rule of the input signal, so that an increase in the configuration of the feedback filter can be suppressed.
[0068]
  Claim4According to the invention described in (1), the determination error existing locally in the shift register is corrected based on the code rule, and divergence is prevented.
[0078]
DETAILED DESCRIPTION OF THE INVENTION
(First embodiment)
Hereinafter, a first embodiment embodying the present invention will be described with reference to FIGS.
[0079]
For the convenience of explanation, the same reference numerals are given to the same components as those in the conventional art, and a part of the explanation is omitted.
FIG. 1 shows a schematic configuration of a hard disk device.
[0080]
The hard disk device 31 is connected to the host computer 32. In response to a write request from the host computer 32, the hard disk device 31 records recording data input from the host computer 32 on a magnetic disk 33 as a recording medium. Further, the hard disk device 31 reads the stored data recorded on the magnetic disk 33 in response to a read request from the host computer 32, and outputs it to the host computer 32.
[0081]
The hard disk device 31 includes a magnetic disk 33, first and second motors M1 and M2, a head device 34, a signal processing circuit 35, a servo circuit 36, a microprocessor (MPU) 37, a memory (RAM) 38, and a hard disk controller (HDC). 39, including an interface circuit 40. Each circuit 35 to 40 is connected to the bus 41.
[0082]
The magnetic disk 33 is rotationally driven at a constant rotational speed by the first motor M1. The head device 34 is position-controlled in the radial direction of the magnetic disk 33 by the second motor M2. The head device 34 reads the information recorded on the magnetic disk 33 and outputs it to the signal processing circuit 35 as a read signal RD.
[0083]
A signal processing circuit (referred to as a read / write channel IC) 35 samples the read signal RD in synchronization with the read signal RD and converts it into a digital signal. The signal processing circuit 35 performs a decoding process on the converted digital signal and outputs the processed signal.
[0084]
The servo circuit 36 receives the output signal of the signal processing circuit 35 via the bus 41. The servo circuit 36 controls the first motor M1 and rotates the magnetic disk 33 at a constant speed. The servo circuit 36 controls the second motor M2 based on the servo information included in the output signal, and causes the head device 34 to be on-track to the target track.
[0085]
The MPU 37 analyzes a command for writing / reading processing input from the host computer 32 based on the program data stored in the RAM 38 in advance, and outputs a control signal to the HDC 39 or the like via the bus 41. To do. The HDC 39 controls the signal processing circuit 35 and the servo circuit 36 based on the signal input from the MPU 37. The HDC 39 inputs the output signal of the signal processing circuit 35 via the bus 41.
[0086]
The HDC 39 assembles the input data into sectors each having a predetermined number of bytes, performs, for example, ECC (Error Correcting Code) error correction processing for each of the assembled sectors, and sends the processed data to the bus 41. Via the interface circuit 40. The interface circuit 40 converts the output data of the HDC 39 based on a predetermined communication method and outputs it as read data to the host computer 32.
[0087]
Write data is input to the HDC 39 from the host computer 32 via the interface circuit 40. The HDC 39 adds data for error correction to the write data and outputs it to the signal processing circuit 35 via the bus 41. The signal processing circuit 35 writes the output data of the HDC 39 to the magnetic disk 33 via the head device 34.
[0088]
Next, the configuration of the signal processing circuit 35 will be described with reference to FIG. 2 corresponding to the write operation and the read operation.
[Write operation]
Write data (write data) output from the MPU 37 in FIG. 1 is input to the scrambler 43 via the interface circuit 42. The scrambler 43 performs a process of changing the order in which the bits of the write data are arranged by a predetermined method, and outputs the processed data to the encoder 44.
[0089]
The encoder 44 encodes the output data of the scrambler 43 based on a predetermined RLL code (run-length limited code: specifically, RLL (1, 7) code). Furthermore, the encoder 44 adds control data such as preamble data for controlling the reading operation to the encoded data. The encoder 44 outputs the processed signal to the write pre-competition 45.
[0090]
The write pre-competition 45 performs timing correction for correcting the timing for writing data to the magnetic disk 33. This timing correction is performed to prevent the position of the information written on the magnetic disk 33 (the magnetic poles corresponding to “0” and “1”) from being shifted due to the influence of the adjacent magnetic poles. The write pre-competition 45 outputs the corrected data to the write flip-flop (write F / F) 46 in the NRZI format.
[0091]
The write F / F 46 outputs a write signal WD to the write head 34 a constituting the head device 34 based on the output signal of the write pre-competition 45. The write head 34a is made of a coil. The write F / F 46 supplies a current corresponding to recording data written to the magnetic disk 33. By forming a magnetic pole on the magnetic disk 33 by this current, data including data, preamble, and sync byte is recorded on the magnetic disk 33.
[0092]
[Read operation]
The read head 34b constituting the head device 34 is composed of an MR (Magneto Resistive) head. The read head 34 b outputs a read signal RD having a value corresponding to the change of the magnetic pole of the magnetic disk 33 to the variable gain amplifier (VGA) 47. The VGA 47 includes an auto gain controller (AGC) 47a. The VGA 47 amplifies the read signal RD and outputs the amplified signal to a decision feedback equalizer (DFE) 48. The AGC 47a controls the gain of the VGA 47 so that the amplitude of the output signal of the VGA 47 becomes a predetermined amplitude. Therefore, the VGA 47 and the AGC 47a constitute a control loop that controls the amplitude of the signal.
[0093]
A timing clock recovery PLL circuit 49 is connected to the DFE 48. The PLL circuit 49 generates a clock signal SCK that is synchronously drawn into the read signal RD based on the output signal of the DFE 48. Based on the clock signal SCK, the DFE 48 performs waveform equalization processing on the output signal of the VGA 47 to convert it into a digital signal, and outputs the signal to the decoder 50.
[0094]
The decoder 50 decodes the output signal of the DFE 48 based on the RLL code, and outputs the decoded data to the descrambler 51. The descrambler 51 rearranges the bits of the output data of the decoder 50 by a predetermined method and generates read data. The read data is output to the MPU 37 in FIG.
[0095]
The DFE 48 outputs the processed signal to the control data detection circuit 53. The control data detection circuit 53 detects control data (preamble and sync byte) for controlling the read operation of the recording data and servo information (servo mark), and sequences a detection signal according to the detected information. The data is output to the control circuit 54 and the MPU 37.
[0096]
The sequence control circuit 54 receives the detection signal and a control signal for controlling writing / reading from the MPU 37. The sequence control circuit 54 controls the circuits 42 to 53 according to a predetermined write / read sequence based on the detection signal and the control signal.
[0097]
The MPU 37 instructs the signal processing circuit 35 to start the reading operation. After that, when receiving the sync byte detection signal, the MPU 37 responds to the sync byte detection signal, treats the read data following the sync byte as recording data (data), and performs processing on the recording data.
[0098]
Next, the configuration of the DFE 48 will be described in detail with reference to FIG. The same components as those in the conventional example of FIG.
The DFE 48 includes a prefilter 12, an adder 13, a determiner 14, a shift register 61, and a feedback filter (FB filter) 65. The adder 13, the determiner 14, the shift register 61, and the FB filter 65 constitute a determination circuit.
[0099]
The prefilter 12 receives the output signal of the VGA 47 of FIG. The prefilter 12 generates a signal having a waveform that maximizes the S / N ratio of the input signal. Thereby, the pre-filter 12 outputs the filtered signal S1 to the adder 13. The adder 13 adds the output signal S1 of the prefilter 12 and the feedback signal S2 output from the FB filter 65, and outputs the calculated signal S3 to the determiner 14.
[0100]
A reference voltage Ref is input to the determiner 14. The determiner 14 compares the voltage of the signal S3 with the reference voltage Ref, and outputs a determination signal S4 of “1” or “0” to the shift register 61 based on the comparison result. Thereby, the determiner 14 converts the output signal S3 of the adder 13 into a digital signal.
[0101]
The shift register 61 includes a first register unit 62 and a second register unit 63. The first and second register units 62 and 63 each include a plurality of registers 64. Each register 64 sequentially stores sampling data. The number of data stored in the shift register 61, that is, the total number of registers 64 included in the shift register 61 corresponds to the transfer code rule used in the encoder 44 and decoder 50 of FIG.
[0102]
In the present embodiment, the first register unit 62 includes the number of registers 64 (eight in FIG. 3) corresponding to the number of taps of the FB filter 65, similarly to the conventional shift register 15 (see FIG. 54). The second register unit 63 includes four registers 64 in the present embodiment.
[0103]
Therefore, the shift register 61 includes 12 registers 64. Thereby, the shift register 61 stores the past 12-bit data sampled. The shift register 61 outputs the stored data to the FB filter 65.
[0104]
The FB filter 65 includes an address conversion unit 66, a memory (RAM) 24, a digital-analog converter (DAC) 25, a divergence monitoring circuit 67, a selection circuit 68, and a signal level generation circuit 69.
[0105]
The address conversion unit 66 decodes 8-bit data input from the first register unit 62 of the shift register 61 and outputs the result to the RAM 24 as an address signal.
[0106]
Since the RAM 24 has the same configuration as the conventional example shown in FIG. 54, its configuration will be described in detail with reference to FIG. That is, the RAM 24 has a plurality of areas 24a, and each area 24a stores a feedback response corresponding to an 8-bit data pattern output from the shift register 61. In these feedback responses, data stored in the shift register 61 and calculation results obtained by previously calculating predetermined filter coefficients ω7 to ω0 are stored.
[0107]
The RAM 24 in FIG. 3 selects one area based on the address signal input from the address conversion unit 66. Then, the RAM 24 outputs data read from the selected area to the DAC 25.
[0108]
The DAC 25 converts the input data into an analog signal, and outputs the analog signal to the adder 13 as a feedback response (feedback signal S2). Therefore, the adder 13, the determiner 14, the shift register 61, the address conversion unit 66, the RAM 24, and the DAC 25 constitute a feedback loop (FB loop).
[0109]
The address conversion unit 66 outputs data input from the first and second register units 62 and 63 to the divergence monitoring circuit 67. The divergence monitoring circuit 67 determines whether or not the FB loop diverges based on the input data.
[0110]
More specifically, the shift register 61 includes 12 registers 64 corresponding to the transfer code rules generated by the encoder 44 of FIG. The encoder 44 generates a bit string obtained by encoding input data based on the RLL (1, 7) code. The encoded data can take values (101) to (100000001). That is, the encoded data includes 1 to 7 “0” s in succession. For this reason, when data of a bit string in which eight or more “0s” continue is stored in the shift register 61, the data includes an error. Therefore, when a bit string that is not generated by the encoding of the encoder 44 is stored in the shift register 61, the bit string includes error data.
[0111]
Therefore, the divergence monitoring circuit 67 monitors whether or not the data input from the address conversion unit 66 includes a bit string that does not correspond to the transfer code rule, and the FB loop diverges based on the monitoring result. Determine whether or not. The divergence monitoring circuit 67 outputs a selection signal SEL having a value based on the determination result, that is, the state of the FB loop and the state of the fixed determination signal S4 output from the determiner 14 when the FB loop diverges.
[0112]
For example, the divergence monitoring circuit 67 outputs a selection signal SEL having a value “0” when it is determined that the FB loop is not diverging. The divergence monitoring circuit 67 outputs a selection signal SEL having a value “1” when the FB loop diverges and the determination signal S4 is fixed to the value “1”. The divergence monitoring circuit 67 outputs a selection signal SEL having a value “2” when the FB loop diverges and the determination signal S4 is fixed to the value “0”.
[0113]
A signal level generation circuit 69 is connected to the selection circuit 68. The signal level generation circuit 69 has a function of generating a plurality of signal levels corresponding to the reference level of the determiner 14. The determiner 14 uses the reference voltage as a reference level. Therefore, the signal level generation circuit 69 generates a plurality of reference voltages Ref1, Ref2, Ref3 as a plurality of signal levels. When the determiner 14 uses the current as the reference level, the signal level generation circuit is configured to generate a plurality of values of current as the signal level.
[0114]
The signal level generation circuit 69 sets the value of the first reference voltage Ref1 as the intermediate voltage (= (highest voltage + lowest voltage) / 2) of the input signal of the determiner 14. Then, the signal level generation circuit 69 generates the values of the second and third reference voltages Ref2 and Ref3 such that (third reference voltage Ref3 <first reference voltage Ref1 <second reference voltage Ref2). Then, the signal level generation circuit 69 outputs the generated reference voltages Ref1 to Ref3 to the selection circuit 68.
[0115]
The selection circuit 68 selects one of the reference voltages Ref1 to Ref3 based on the value of the selection signal SEL. Specifically, the selection circuit 68 generates the first reference voltage Ref1 in response to the selection signal SEL having the value “0”, the second reference voltage Ref2 in response to the selection signal SEL having the value “1”, and the value “ The third reference voltage Ref3 is selected in response to the selection signal SEL of “2”. Then, the selection circuit 68 outputs the selected voltage to the determiner 14 as the reference voltage Ref.
[0116]
The determiner 14 determines whether the voltage of the input signal S3 is higher or lower than the reference voltage Ref based on the input reference voltage Ref, and determines “1” or “0” based on the determination result. The signal S4 is output. That is, the reference voltage Ref is a determination reference of the determination unit 14. The value of the reference voltage Ref is changed according to the selection signal SEL, that is, the state of the FB loop. That is, the FB filter 65 monitors the state of the FB loop and changes the determination criterion of the determiner 14 based on the monitoring result.
[0117]
Next, the operation of the DFE 48 configured as described above will be described with reference to FIGS.
First, the state of divergence of the FB loop will be described with reference to FIG.
[0118]
FIG. 4 shows a write current for writing data to the magnetic disk 33 at the sampling points a (k-3) to a (k + 2) at times (k-3) to (k + 2), and a read signal RD by the read head 34b. , And the waveform of the output signal S3 of the adder 13 based on the read signal RD.
[0119]
The read signal RD is a Lorentz pulse having a maximum value at the change point of the write signal (between the sampling points a (k−1) and a (k)). The prefilter 12 of FIG. 3 generates a signal S1 having a waveform that maximizes the S / N ratio based on the read signal RD. The adder 13 outputs a signal S3 obtained by adding the feedback signal S2 output from the FB filter 65 to the signal S1. The determination unit 14 compares the voltage of the signal S3 with the reference voltage Ref at each sampling point a (k-3) to a (k + 2), and outputs the comparison result as the determination signal S4.
[0120]
When an error is propagated to the FB loop, the output signal S3 of the adder 13 decreases as shown by a one-dot chain line in FIG. The signal S3 is stabilized at a voltage lower than the reference voltage Ref at the sampling points a (k + 1) and a (k + 2). Therefore, the determiner 14 outputs a determination signal S4 of “0” at the sampling points a (k + 1) and a (k + 2). When the determination signal S4 is propagated to the FB loop and the FB loop diverges, the determination signal S4 output from the determination unit 14 is fixed to one value.
[0121]
Next, the state transition of the DFE 48 will be described with reference to FIG.
The DFE 48 takes states 1 to 6. The DFE 48 changes the state based on the value of the input signal S3 of the determiner 14. In the above description of each state 1 to 6, “+ q”, “+ r”, “−r”, “−q” indicate the theoretical values of the input signal in each state 1 to 6, and “0”, “ “1” indicates the result of the exclusive OR operation (EOR operation) of the operation result of the “1 + D” operation by the FB filter 65 with respect to the determination signal S4 output from the determiner 14 as the determination result. This calculation result is in NRZI format and is the output of DFE48. The “1 + D” operation is an operation for adding the determination result at that time and the next determination result.
[0122]
That is, the DFE 48 is in the state 4 when the value of the input signal S3 is the lowest (Ref-q or its vicinity). At this time, the determiner 14 outputs “0” as the determination signal S4 based on the input signal S3.
[0123]
Next, when the value of the input signal S3 becomes high (Ref-r), the DFE 48 transitions from the state 4 to the state 5. At this time, the determiner 14 outputs a determination signal S4 having a value “0” in the state 4. Accordingly, in state 4, DFE 48 outputs “0” as a result of EORing the value “0” of determination signal S 4 in state 4 and the value “0” of determination signal S 4 in state 5.
[0124]
When the value of the input signal S3 becomes higher than the reference voltage Ref (Ref + r), the DFE 48 transitions from the state 5 to the state 6 as shown in FIG. At this time, the determiner 14 outputs a determination signal S4 having a value “1”. Accordingly, the DFE 48 outputs “1” as a result of performing an EOR operation on the value “0” of the determination signal S4 in the state 5 and the value “1” of the determination signal S4 in the state 6.
[0125]
When the value of the input signal S3 becomes higher (Ref + q), the DFE 48 transitions from state 6 to state 1. At this time, the determiner 14 outputs a determination signal S4 of “1”. Accordingly, the DFE 48 outputs “0” as a result of performing an EOR operation on the value “1” of the determination signal S4 in the state 6 and the value “1” of the determination signal S4 in the state 1.
[0126]
Similarly, the case where the value of the input signal S3 becomes low will be described. When the value of the input signal S3 becomes low (Ref + r), the DFE 48 changes from state 1 to state 2. At this time, the determiner 14 outputs a determination signal S4 of “1”. Accordingly, the DFE 48 outputs “0” as a result of calculating the value “1” of the determination signal S4 in state 1 and the value “1” of the determination signal S4 in state 2.
[0127]
Next, when the value of the input signal S3 becomes lower than the reference voltage Ref (Ref-r), the DFE 48 transitions from the state 2 to the state 3 (see FIG. 6). At this time, the determiner 14 outputs a determination signal S4 of “0”. Therefore, the DFE 48 outputs “1” as a result of performing an EOR operation on the value “1” of the determination signal S4 in the state 2 and the value “0” of the determination signal S4 in the state 3.
[0128]
When the value of the input signal S3 further decreases (Ref-q), the DFE 48 transitions from state 3 to state 4. At this time, the determiner 14 outputs a determination signal S4 of “0”. Therefore, the DFE 48 outputs “0” as a result of performing an EOR operation on the value “1” of the determination signal S4 in the state 3 and the value “0” of the determination signal S4 in the state 4.
[0129]
If the level of the input signal S3 does not change when in the state 6, that is, if the value of the next input signal S3 is (Ref + r), the DFE 48 transitions from the state 6 to the state 2. When the level of the input signal S3 does not change when in the state 3, that is, when the value of the next input signal S3 is (Ref-r), the DFE 48 transitions from the state 3 to the state 5.
[0130]
When error propagation occurs, the change in the value of the input signal S3 of the determiner 14 becomes small. As a result, the DFE 48 cannot transition from the state 2 to the state 3 and stays in the state 1. At this time, the determiner 14 continuously outputs the determination signal S4 having the value “1”. Further, the DFE 48 cannot transition from the state 5 to the state 6 and stays in the state 4. At this time, the determiner 14 continuously outputs a determination signal S4 having a value “0”.
[0131]
The divergence monitoring circuit 67 in FIG. 3 detects the divergence of the FB loop based on the continuous determination signal S4 having the value “1”, and outputs the selection signal SEL having the value “1”. In response to the selection signal SEL, the selection circuit 68 selects the second reference voltage Ref2, and outputs it to the determination unit 14 as the reference voltage Ref. That is, the determination criterion of the determiner 14 is increased.
[0132]
Thereby, as shown in FIG. 7, the threshold value at which the state transitions shifts to the state 2 side. Then, as shown in FIG. 8, even if the output signal S1 of the prefilter 12 is a positive value, the determiner 14 determines that the output is negative if it is equal to or lower than the second reference voltage Ref2, and determines “0”. The signal S4 is output. That is, the determiner 14 can easily output the determination signal S4 of “0”. As a result, the divergence monitoring circuit 67 increases the sensitivity of the determiner 14 for negative signals. The DFE 48 can easily capture the negative read signal RD.
[0133]
Therefore, the DFE 48 has a higher degree of transition from state 2 to state 3. Thereby, the DFE 48 prevents the determination signal S4 from sticking and prevents the FB loop from diverging.
[0134]
As another example, when error propagation occurs, the DFE 48 cannot transition from the state 5 to the state 6, and cycles through the states 5, 3, and 4. At this time, the determiner 14 continuously outputs the determination signal S4 having the value “0”.
[0135]
The divergence monitoring circuit 67 in FIG. 3 detects the divergence of the FB loop based on the continuous determination signal S4 having a value “0” and outputs a selection signal SEL having a value “2”. In response to the selection signal SEL, the selection circuit 68 selects the third reference voltage Ref3 and outputs it to the determiner 14 as the reference voltage Ref. That is, the determination criterion of the determiner 14 is lowered.
[0136]
As a result, as shown in FIG. 9, the threshold value at which the state transitions shifts to the state 5 side. Then, as shown in FIG. 10, even if the output signal S1 of the prefilter 12 is a negative value, the determiner 14 determines that it is positive if it is equal to or higher than the third reference voltage Ref3, and determines “1”. The signal S4 is output. That is, the determiner 14 can easily output a determination signal of “1”. Thereby, the divergence monitoring circuit 67 increases the sensitivity of the determiner 14 for positive signals. The DFE 48 can easily capture the positive read signal RD.
[0137]
Therefore, the degree of transition of the DFE 48 from the state 5 to the state 6 increases. Thereby, the DFE 48 prevents the determination signal S4 from sticking and prevents the FB loop from diverging.
[0138]
As described above, according to the present embodiment, the following effects can be obtained.
(1) The determination result stored in the shift register 61 is monitored by the divergence monitoring circuit 67. When the determination result is fixed to one value, the determination criterion of the determination circuit is changed. This makes it easy to detect an input signal having a different sign from the fixed determination result, and makes it difficult to detect an input signal having the same sign as the fixed determination result. As a result, the sticking of the criterion is eliminated, and the divergence of the feedback filter is stopped. As a result, errors in the read signal are reduced, so that the data read time can be shortened.
[0139]
(2) A signal level generation circuit 69 that generates a plurality of reference voltages Ref1 to Ref3 is provided. Based on the determination result of the divergence monitoring circuit 67, the selection circuit 68 selects one of the plurality of reference voltages, The selected reference voltage is set as the reference voltage Ref of the determiner 14. As a result, the determination criterion of the determination circuit can be easily changed based on the monitoring result.
[0140]
(Second embodiment)
Hereinafter, a second embodiment of the present invention will be described with reference to FIG.
FIG. 11 is a block circuit diagram of a decision feedback equalizer (DFE) 70 according to this embodiment. For the sake of convenience of explanation, the same components as those in the first embodiment shown in FIG.
[0141]
The DFE 70 includes a pre-filter 12, an adder 13, a determiner 14, a shift register 61, and a feedback filter (FB filter) 71.
The FB filter 71 includes an address conversion unit 66, a memory (RAM) 24, a digital-analog converter (DAC) 25, a divergence monitoring circuit 67, a selection circuit 68, a signal level generation circuit 72, and an adder 73.
[0142]
The address conversion unit 66 decodes 8-bit data input from the first register unit 62 of the shift register 61 and outputs the result to the RAM 24 as an address signal.
[0143]
The RAM 24 has a plurality of areas, and a feedback response corresponding to an 8-bit data pattern output from the shift register 61 is stored in each area. The RAM 24 selects one area by the address signal input from the address conversion unit 66. Then, the RAM 24 outputs data read from the selected area to the DAC 25. The DAC 25 converts the input data into an analog signal, and outputs the analog signal to the adder 13 as a feedback response (feedback signal S2).
[0144]
The address conversion unit 66 outputs data input from the first and second register units 62 and 63 to the divergence monitoring circuit 67.
The divergence monitoring circuit 67 monitors whether or not the 12-bit data input from the address conversion unit 66 includes a bit string that does not correspond to the transfer code rule, and the FB loop diverges based on the monitoring result. Judge whether or not. The divergence monitoring circuit 67 supplies the selection circuit 68 with a selection signal SEL having a value based on the determination result, that is, the state of the FB loop and the state of the fixed determination signal S4 output from the determination unit 14 when the FB loop is diverging. Output.
[0145]
For example, the divergence monitoring circuit 67 outputs a selection signal SEL having a value “0” when it is determined that the FB loop is not diverging. The divergence monitoring circuit 67 outputs a selection signal SEL having a value “1” when the FB loop diverges and the determination signal S4 is fixed to the value “1”. The divergence monitoring circuit 67 outputs a selection signal SEL having a value “2” when the FB loop diverges and the determination signal S4 is fixed to the value “0”. Note that the value of the selection signal SEL may be changed as appropriate.
[0146]
A signal level generation circuit 72 is connected to the selection circuit 68. The signal level generation circuit 72 generates a plurality of offset signals Off1, Off2, Off3 as a plurality of signal levels. When the determination unit 14 sets the current as the reference level, the signal level generation circuit 72 may generate a plurality of values of current as the signal level.
[0147]
The signal level generation circuit 72 sets the value of the first offset signal Off1 to “0”. Then, the signal level generation circuit 72 generates the values of the second and third offset signals Off2 and Off3 such that (third offset signal Off3> first offset signal Off1> second offset signal Off2). Since the value of the first offset signal Off1 is “0”, the second offset signal Off2 is a negative value. The absolute values of the second and third offset signals Off2 and Off3 are the same. Then, the signal level generation circuit 72 outputs the generated offset signals Off1 to Off3 to the selection circuit 68.
[0148]
The selection circuit 68 selects one of the offset signals Off1 to Off3 based on the value of the selection signal SEL. Specifically, the selection circuit 68 outputs the first offset signal Off1 in response to the selection signal SEL having the value “0”, the second offset signal Off2 in response to the selection signal SEL having the value “1”, and the value “ The third offset signal Off3 is selected in response to the selection signal SEL of “2”. Then, the selection circuit 68 outputs the selected voltage to the adder 73 as the offset signal Off.
[0149]
The output signal of the RAM 24 is input to the adder 73. The adder 73 adds the output signal of the RAM 24 and the offset signal Off, and outputs the addition result to the DAC 25. As a result, a feedback response (feedback signal S2) in which any one of the first to third offset signals Off1 to Off3 is added based on the selection signal SEL is fed back to the adder 13.
[0150]
When the FB loop does not diverge, the divergence monitoring circuit 67 outputs a selection signal SEL having a value “0”. As a result, the first offset signal Off1 is selected and added to the output signal of the RAM 24. The value of the first offset signal Off1 is “0”. Therefore, when the FB loop does not diverge, the output signal of the RAM 24 is fed back to the adder 13 as a feedback response.
[0151]
When the FB loop is fixed to “1”, the divergence monitoring circuit 67 outputs a selection signal SEL having a value “1”. As a result, the second offset signal Off2 is selected and added to the output signal of the RAM 24. The second offset signal Off2 is a negative value. Therefore, a feedback response having a value smaller than the output signal of the RAM 24 by the second offset signal Off2 is fed back to the adder 13.
[0152]
That is, the FB filter 71 offsets the analog signal for the output data of the RAM 24 in the negative direction. This is equivalent to increasing the reference voltage of the determiner 14 in the first embodiment. This makes it easier for the determiner 14 to output a determination signal S4 of “0”. That is, the divergence monitoring circuit 67 increases the sensitivity of the determiner 14 for negative signals. Thereby, as in the first embodiment, the DFE 70 prevents the determination signal S4 from sticking and prevents the FB loop from diverging.
[0153]
When the FB loop is fixed to “0”, the divergence monitoring circuit 67 outputs a selection signal SEL having a value “2”. As a result, the third offset signal Off3 is selected and added to the output signal of the RAM 24. The third offset signal Off3 is a positive value. Therefore, a feedback response having a value larger than the output signal of the RAM 24 by the third offset signal Off3 is fed back to the adder 13.
[0154]
That is, the FB filter 71 offsets the analog signal for the output data of the RAM 24 in the positive direction. This is equivalent to lowering the reference voltage of the determiner 14 in the first embodiment. This makes it easier for the determiner 14 to output the determination signal S4 of “1”. That is, the divergence monitoring circuit 67 increases the sensitivity of the determiner 14 for positive signals. Thereby, as in the first embodiment, the DFE 70 prevents the determination signal S4 from sticking and prevents the FB loop from diverging.
[0155]
As described above, according to the present embodiment, the following effects can be obtained.
(1) First fruit
The same effect as (1) of embodiment is produced.
[0156]
(2) Based on the determination result of the divergence monitoring circuit 67, the feedback amount is offset by the DAC 25. Thereby, the determination criterion of the determination circuit can be easily changed with a simple configuration.
[0157]
In the above embodiment, the following modifications may be made.
In the second embodiment, the DAC 25 may fix the value of the feedback signal to be output, that is, the feedback amount, to a constant value based on the monitoring result of the divergence monitoring circuit 67. In this case, if a feedback signal is output based on the output signal of the RAM 24 including an error, the error in the determination result of the determiner 14 may be increased. Therefore, by feeding back a constant feedback amount to the adder 13 as a feedback signal, errors included in the determination result can be reduced, and as a result, the divergence of the FB loop can be quickly eliminated.
[0158]
In the second embodiment, the divergence monitoring circuit 67, when the error data by the determiner 14 is present locally in the determination result stored in the shift register 61, is based on the transmission code rule. It corrects and outputs to RAM24. The RAM 24 reads the feedback response stored in the area based on the data input from the diverging circuit 73 and outputs the response to the DAC 25. The DAC 25 converts the output signal of the RAM 24 into an analog signal, and outputs the converted signal to the adder 13 as a feedback signal S2. When configured in this way, locally existing errors are not propagated, and divergence of the FB loop can be prevented.
[0159]
(Third embodiment)
Hereinafter, a third embodiment of the present invention will be described with reference to FIGS. For convenience of explanation, the same reference numerals are given to the same configurations as those of the first embodiment of FIG. 3 and the second embodiment of FIG. 11, and a part of the explanation is omitted.
[0160]
FIG. 12 is a block circuit diagram of a decision feedback equalizer (DFE) 201 according to this embodiment.
The DFE 201 includes a pre-filter 12, an adder 13, a determiner 14, a shift register 61, and a feedback filter (FB filter) 202.
[0161]
The shift register 61 includes a first register unit 62 and a second register unit 63. The first and second register units 62 and 63 each include a plurality of registers 64. Each register 64 sequentially stores sampling data.
[0162]
In the present embodiment, the first register unit 62 includes six registers 64 corresponding to the number of taps of the FB filter 202. The second register unit 63 includes three registers 64. Therefore, the shift register 61 includes nine registers 64. As a result, the shift register 61 stores the sampled past 9-bit data d0 to d8. The shift register 61 outputs the stored data d0 to d8 to the FB filter 202.
[0163]
The FB filter 202 includes a memory (RAM) 24, a digital-analog converter (DAC) 25, a divergence monitoring circuit 67, a first selection circuit 68, a first signal level generation circuit (hereinafter referred to as a first generation circuit) 69, 2 selection circuit 203, second signal level generation circuit (hereinafter referred to as second generation circuit) 204, decoder 205, error detection circuit 206, state machine (STM) 207, and latches 208a to 208c.
[0164]
The RAM 24 receives 6-bit data d0 to d5 stored in the first register unit 62. The RAM 24 has a plurality of areas, and in each area, feedback responses corresponding to the patterns of 6-bit data d0 to d5 output from the shift register 61 are stored. The RAM 24 selects one area by the address signal input from the address conversion unit 66. Then, the RAM 24 outputs the data read from the selected area to the DAC 25 via the latch 208a. The DAC 25 converts the input data into an analog signal, and outputs the analog signal to the adder 13 as a feedback response (feedback signal S2).
[0165]
The 9-bit data d0 to d8 stored in the shift register 61 is output to the divergence monitoring circuit 67. The divergence monitoring circuit 67 determines whether or not the FB loop diverges based on the input data d0 to d8, as in the first and second embodiments. That is, the divergence monitoring circuit 67 monitors whether or not the input data d0 to d8 includes a bit string that does not correspond to the transfer code rule, and whether or not the FB loop diverges based on the monitoring result. Determine whether. The divergence monitoring circuit 67 outputs a signal S71 having a value based on the determination result, that is, the state of the FB loop and the state of the fixed determination signal S4 output from the determiner 14 when the FB loop is diverging through the latch 208c. Output to STM207.
[0166]
For example, the divergence monitoring circuit 67 outputs a signal S71 having a value “0” when it is determined that the FB loop is not diverging. The divergence monitoring circuit 67 outputs a signal S71 having a value “1” when the FB loop diverges and the determination signal S4 is fixed to the value “1”. The divergence monitoring circuit 67 outputs a signal S71 having a value “2” when the FB loop diverges and the determination signal S4 is fixed to the value “0”.
[0167]
The 9-bit data d0 to d8 stored in the shift register 61 is output to the decoder 205. The decoder 205 is a 1 + D decoder that performs 1 + D operation, and includes eight exclusive OR circuits (EOR circuits) 205a as shown in FIG.
[0168]
Each EOR circuit 205a receives 2-bit data that is temporally continuous. For example, 2-bit data d0 and d1 are input to the first-stage EOR circuit 205a, and 2-bit data d7 and d8 are input to the final-stage EOR circuit 205a. Each EOR circuit 205a performs an exclusive OR operation on the 2-bit data and outputs the operation result to the error detection circuit 206 as signals Ad0 to Ad7.
[0169]
As shown in FIGS. 15 to 18, the error detection circuit 206 decodes the input signals Ad0 to Ad7 based on an RLL code (run-length limited code: specifically, RLL (1, 7) code). At that time, the error detection circuit 206 detects error data included in the input signal, and outputs a signal S72 to the STM 207 via the latch 208b based on the detection result.
[0170]
As described in the state transition of the DFE 48 in the first embodiment (see FIG. 5), the DFE 201 outputs the determination signal S4 of “1” when the input signal S3 of the determiner 14 exceeds the reference level Ref. . This means that when the DFE operation is normal, the determination signal S4 in which “1” continues is not output. Therefore, as shown in FIG. 15, when the signals Ad0 to Ad7 include “1” in which two or more bits are continuous, the continuous “1” is a locally existing error.
[0171]
Further, the data d0 to d8 of the shift register 61 in which the determination signal S4 is sequentially stored means that only values (101) to (100000001) are taken. Therefore, as shown in FIG. 15, when all of the signals Ad0 to Ad7 are “0” or “1”, the signals Ad0 to Ad7 are errors and further errors are propagated (fixed). Become.
[0172]
Therefore, the error detection circuit 206 detects whether the input signals Ad0 to Ad7 contain errors or has error propagation, and outputs a signal S72 to the STM 207 based on the detection result. For example, when detecting a local error, the error detection circuit 206 outputs a signal S72 having a value “2” (binary 10). Further, when error propagation is detected, the error detection circuit 206 outputs a signal S72 having a value “3” (binary 11) to the STM 207.
[0173]
The signal d0 output from the shift register 61 is input to the STM 207. This signal d0 is an output signal of the DFE 201. The STM 207 changes its operation state (state) based on the signals d0, S71, and S72.
[0174]
As shown in FIG. 13, the STM 207 can take states Z1 to Z4. The STM 207 takes the state Z1 when the FB loop is not fixed and the DFE 201 is operating normally.
[0175]
At this time, the STM 207 outputs the first and second selection signals SEL1, SEL2 based on the signals S71, S72. Specifically, when the DFE 201 is normal, the STM 207 outputs selection signals SEL1 and SEL2 having a value “0” to the first and second selection circuits 68 and 203.
[0176]
A first generation circuit 69 is connected to the first selection circuit 68 as in the first embodiment. The first generation circuit 69 has a function of generating a plurality of signal levels corresponding to the reference level of the determiner 14. The determiner 14 uses the reference voltage as a reference level. Accordingly, the first generation circuit 69 generates a plurality of reference voltages Ref1, Ref2, Ref3 as a plurality of signal levels. When the determiner 14 uses the current as the reference level, the signal level generation circuit is configured to generate a plurality of values of current as the signal level.
[0177]
The first generation circuit 69 sets the value of the first reference voltage Ref1 as an intermediate voltage (= (highest voltage + lowest voltage) / 2) of the input signal of the determiner 14. Then, the first generation circuit 69 generates the values of the second and third reference voltages Ref2 and Ref3 such that (third reference voltage Ref3 <first reference voltage Ref1 <second reference voltage Ref2). Then, the first generation circuit 69 outputs the generated reference voltages Ref <b> 1 to Ref <b> 3 to the first selection circuit 68.
[0178]
The first selection circuit 68 selects one of the reference voltages Ref1 to Ref3 based on the value of the first selection signal SEL1. Specifically, the first selection circuit 68 generates the first reference voltage Ref1 in response to the first selection signal SEL1 having the value “0” and the second reference circuit responsive to the first selection signal SEL1 having the value “1”. The voltage Ref2 is selected in response to the first selection signal SEL1 having the value “2” to select the third reference voltage Ref3. Then, the first selection circuit 68 outputs the selected voltage to the determination unit 14 as the reference voltage Ref.
[0179]
Therefore, when the STM 207 is in the state Z1, the first reference voltage Ref1 at the intermediate level is input to the determiner 14 as the reference voltage Ref.
The output signal of the RAM 24 is input to the second selection circuit 203. A second generation circuit 204 is connected to the second selection circuit 203. The second generation circuit 204 generates a plurality of feedback (FB) signals Feed1 and Feed2 as a plurality of signal levels. When the determination unit 14 sets the current as the reference level, the second generation circuit 204 may generate a plurality of values of current as the signal level.
[0180]
The second generation circuit 204 sets the first FB signal Feed1 to a value indicating a level higher than the first reference voltage Ref1, and the second FB signal Feed2 to a value indicating a level lower than the second reference voltage Ref1. That is, the second generation circuit 204 sets (Feed1> Ref1> Feed2).
[0181]
More specifically, the second generation circuit 204 sets the value of the first FB signal Feed1 to (Ref1 + r) and sets the value of the second FB signal Feed2 to (Ref1-r). These values are theoretical values that the signal S3 can take, as shown in FIG. The second generation circuit 204 outputs the generated first and second FB signals Feed 1 and Feed 2 to the second selection circuit 203.
[0182]
The second selection circuit 203 selects one of the output signal of the RAM 24 and the first and second FB signals Feed1 and Feed2 based on the value of the second selection signal SEL2. Specifically, the second selection circuit 203 outputs the output signal of the RAM 24 in response to the second selection signal SEL2 having the value “0”, and the first FB signal Feed1 in response to the second selection signal SEL2 having the value “1”. The second FB signal Feed2 is selected in response to the second selection signal SEL2 having the value “2”. Then, the second selection circuit 203 outputs the selected signal to the DAC 25.
[0183]
The DAC 25 converts the input signal into an analog signal and outputs the analog signal to the adder 13 as a feedback response (feedback signal S2). As a result, a feedback response obtained by adding one of the output signal of the RAM 24 and the first and second FB signals Feed1 and Feed2 is fed back to the adder 13 based on the second selection signal SEL2.
[0184]
When the FB loop is not diverging, the STM 207 outputs the second selection signal SEL2 having a value “0”. As a result, the output signal of the RAM 24 is fed back to the adder 13 as a feedback response.
[0185]
The STM 207 transitions from the state Z1 to the state Z2 when the sticking occurs based on the signals S71 and S72. In the state Z2, the STM 207 operates to change the feedback amount of the FB loop.
[0186]
More specifically, the signal S71 output from the divergence monitoring circuit 67 indicates a fixed state. Based on the signal S71, the STM 207 outputs the signal S71 to the second selection circuit 203 as the second selection signal SEL2.
[0187]
The second selection circuit 203 selects one of the first and second FB signals Feed1 and Feed2 based on the second selection signal SEL2, and outputs the selection signal to the DAC 25. Based on the signal S71, the STM 207 outputs the second selection signal SEL2 having the value “1” when the determination signal S4 is fixed to the value “1”. The second selection circuit 203 selects the first FB signal Feed1 based on the second selection signal SEL2 having the value “1”, and outputs the first FB signal Feed1 to the DAC 25.
[0188]
As a result, the level of the first FB signal Feed1 is output to the adder 13 as a feedback response (feedback signal S2). The level of the feedback signal S2 at this time is smaller than the level of the feedback signal S2 based on the signal output from the RAM 24 when the determination signal S4 is fixed to “1”. Thereby, the STM 207 reduces the feedback amount when the determination signal S4 is fixed to “1”. That is, as shown in FIG. 19, the STM 207 forcibly transitions the DFE 201 in the state 1 (see FIG. 5) to the state 2.
[0189]
This is equivalent to increasing the reference voltage of the determiner 14 in the first embodiment. In the second embodiment, this is equivalent to offsetting the feedback amount in the negative direction. That is, the divergence monitoring circuit 67 increases the sensitivity of the determiner 14 for negative signals. As a result, the DFE 201 easily transitions to state 3, and the determiner 14 outputs a determination signal S4 of “0”.
[0190]
Based on the signal S71, the STM 207 outputs the second selection signal SEL2 having the value “2” when the determination signal S4 is fixed to the value “0”. The second selection circuit 203 selects the second FB signal Feed2 based on the second selection signal SEL2 having the value “2”, and outputs it to the DAC 25.
[0191]
As a result, the level of the second FB signal Feed2 is output to the adder 13 as a feedback response (feedback signal S2). The level of the feedback signal S2 at this time is higher than the level of the feedback signal S2 based on the signal output from the RAM 24 when the determination signal S4 is fixed to “0”. Accordingly, the STM 207 increases the feedback amount when the determination signal S4 is fixed to “0”. That is, as shown in FIG. 20, the STM 207 forcibly transitions the DFE 201 in the state 4 (see FIG. 5) to the state 5.
[0192]
This is equivalent to lowering the reference voltage of the determiner 14 in the first embodiment. In the second embodiment, this is equivalent to offsetting the feedback amount in the positive direction. That is, the STM 207 increases the sensitivity of the determiner 14 for positive signals. As a result, the DFE 201 easily transitions to state 6, and the determiner 14 outputs a determination signal S4 of “1”.
[0193]
When the change of the feedback amount is completed, the STM 207 transitions from the state Z2 to the state Z3. In the state Z3, the STM 207 operates to change the determination criterion of the determiner 14.
[0194]
More specifically, the signal S71 output from the divergence monitoring circuit 67 indicates a fixed state. The STM 207 outputs the signal S71 to the first selection circuit 68 as the first selection signal SEL1 based on the signal S71.
[0195]
The first selection circuit 68 selects one of the second and third reference voltages Ref2 and Ref3 based on the first selection signal SEL1, and outputs the selection signal to the DAC 25. Based on the signal S71, the STM 207 outputs the first selection signal SEL1 having the value “1” when the determination signal S4 is fixed to the value “1”. The first selection circuit 68 outputs the second reference voltage Ref2 as the reference voltage Ref to the determiner 14 based on the first selection signal SEL1 having the value “1”.
[0196]
The level of the reference voltage Ref (= Ref2) is higher than that of the first reference voltage Ref1. As a result, the STM 207 increases the determination criterion of the determiner 14. That is, the divergence monitoring circuit 67 increases the sensitivity of the determiner 14 for negative signals. As a result, the DFE 201 easily transitions to state 3, and the determiner 14 outputs a determination signal S4 of “0”.
[0197]
Based on the signal S71, the STM 207 outputs the first selection signal SEL1 having the value “2” when the determination signal S4 is fixed to the value “0”. The first selection circuit 68 outputs the third reference voltage Ref3 as the reference voltage Ref to the determiner 14 based on the first selection signal SEL1 having the value “2”.
[0198]
The level of the reference voltage Ref (= Ref3) is lower than that of the first reference voltage Ref1. As a result, the STM 207 lowers the determination criterion of the determination noble 14. That is, the STM 207 increases the sensitivity of the determiner 14 for positive signals. As a result, the DFE 201 easily transitions to state 6, and the determiner 14 outputs a determination signal S4 of “1”.
[0199]
When the STM 207 finishes changing the reference amount, the STM 207 stays in the state Z3 in FIG. When the STM 207 detects a pulse based on the signal d0 input from the shift register 61 of FIG. 12, the STM 207 transitions from the state Z3 to the state Z4.
[0200]
The pulse detection indicates that the data has transitioned such that the determination signal S4 is “0 → 1” or “1 → 0”, that is, the sticking has been eliminated. Accordingly, the STM 207 returns the reference amount to the base in the state Z4. That is, the STM 207 outputs the first selection signal SEL 1 having a value “0” to the first selection circuit 68.
[0201]
Further, the STM 207 outputs a second selection signal SEL 2 having a value “0” to the second selection circuit 203. Accordingly, the FB filter 202 outputs a feedback response (feedback signal S2) based on the output signal of the RAM 24 to the adder 13 based on the second selection signal SEL2. Then, the SMT 207 transitions from the state Z4 to the state Z1 when a predetermined time (for example, 10 ms) elapses in the state Z4.
[0202]
As described above, according to the present embodiment, the following effects can be obtained.
(1) Since the reference level is changed and the feedback amount is changed when the determination signal S4 output from the determiner 14 is fixed, the normal state can be restored earlier than in the first and second embodiments. it can.
[0203]
(2) Since the error detection circuit 206 is provided, an error existing locally in the shift register 61 can be detected, and the reference amount and the feedback amount can be changed to return to the normal state with respect to the error. .
[0204]
In the above embodiment, the following modifications may be made.
In the above embodiment, the order of changing the feedback amount and the reference amount may be changed. That is, the STM 207 of FIG. 12 operates to change the reference amount in the state Z2 of FIG. 13, and operates to change the feedback amount in the state Z3. Even if comprised in this way, there exists an effect | action and effect similar to the said embodiment.
[0205]
(Fourth embodiment)
A fourth embodiment embodying the present invention will be described below with reference to FIGS. For the sake of convenience of explanation, the same components as those of the conventional example of FIG.
[0206]
FIG. 21 is a partial block circuit diagram of the signal processing circuit 81 of the present embodiment.
The signal processing circuit 81 includes a DFE 82, an A / D converter (hereinafter referred to as ADC) 83, a timing recovery PLL circuit (hereinafter referred to as TR-PLL) 84, and a digital arithmetic circuit (hereinafter simply referred to as arithmetic circuit) 85. The ADC 83 and the TR-PLL 84 constitute the timing clock recovery PLL circuit 49 shown in FIG.
[0207]
The DFE 82 includes a changeover switch (first switch) 86 and an open / close switch (second switch) 87. The first switch 86 receives the output signal S1 of the prefilter 12 and the output signal S3 of the adder 13. The first switch 86 performs a switching operation in response to the control signal SG1 input from the sequence control circuit 54 in FIG. 2, and outputs the output signal S1 of the prefilter 12 or the output signal S3 of the adder 13 to the ADC 83. . For example, the first switch 86 outputs the output signal S1 of the prefilter 12 to the ADC 83 based on the H level control signal SG1, and the output signal S3 of the adder 13 to the ADC 83 based on the L level control signal SG1. Output.
[0208]
The second switch 87 is inserted and connected between the feedback filter (hereinafter referred to as FB filter) 22 and the adder 13. The second switch 87 opens and closes in response to the control signal SG2 output from the sequence control circuit 54 of FIG. For example, the second switch 87 opens (turns off) based on the control signal SG2 at H level and closes (turns on) based on the control signal SG2 at L level. By the opening / closing operation of the second switch 87, the feedback loop (hereinafter referred to as FB loop) of the DFE 82 is opened or closed.
[0209]
The sequence control circuit 54 outputs a control signal to control the first and second switches 86 and 87 based on information included in the read signal RD read from the magnetic disk 33.
[0210]
More specifically, the sequence control circuit 54 outputs the first and second control signals SG1 and SG2 at the H level of the prefilter 12 to the first and second switches 86 and 87 when the read operation is started. . The first switch 86 performs a switching operation based on the control signal SG1 at the H level, and the output signal S1 of the prefilter 12 is input to the ADC 83 via the first switch by the operation. The second switch 87 is turned off based on the H level control signal SG2. Thereby, the FB loop is opened.
[0211]
The ADC 83 A / D converts the output signal S1 of the prefilter 12 and outputs the converted signal S11 to the digital arithmetic circuit 85. The arithmetic circuit 85 has a function of calculating the initial value of the FB filter 22 based on the output signal S11 of the ADC 83, a function of detecting preamble data based on the output signal of the ADC 83, and the initial value to the shift register 15 of the DFE 82. Has a writing function.
[0212]
When the digital arithmetic circuit 85 detects the preamble data, it writes the calculated initial value into the shift register 15. The FB filter 22 of the DFE 82 calculates a feedback amount (feedback response) based on the signal input from the shift register 15 and outputs the calculation result to the adder 13. Therefore, the FB filter 22 calculates the feedback amount based on the initial value written in the shift register 15. Thereby, the digital arithmetic circuit 85 realizes a function of presetting the contents of the shift register 15 based on the calculated initial value.
[0213]
Further, when the digital arithmetic circuit 85 detects the preamble data, it outputs the detection signal to the sequence control circuit 54 in FIG. The sequence control circuit 54 outputs L level control signals SG 1 and SG 2 to the first and second switches 86 and 87 in response to the detection signal of the digital arithmetic circuit 85.
[0214]
The first switch 86 performs a switching operation based on the L-level first control signal SG1, and the output signal S3 of the adder 13 is input to the ADC 83 via the first switch 86 by the operation. The ADC 83 A / D converts the output signal of the adder 13 and outputs the converted signal to the TR-PLL 84. The TR-PLL 84 pulls in the phase of the reference clock signal SCK into the preamble signal based on the output signal of the ADC 83.
[0215]
The second switch 87 is turned on based on the L-level second control signal SG2. As a result, the output signal of the FB filter 22 is fed back to the adder 13 via the second switch 87 that is turned on. At this time, the FB filter 22 calculates a feedback amount based on the preset contents (initial value) of the shift register 15, and outputs the calculation result as a feedback signal S2. Therefore, the FB loop starts feedback based on the feedback signal S2. That is, therefore, the digital arithmetic circuit 85 determines the initial value of the FB filter 22.
[0216]
As shown in FIG. 22, when the read operation is started, first, preamble data and sync byte are read prior to data. This preamble data is a periodic pattern. The TR-PLL 84 performs phase pull-in to make the phase of the reference clock signal SCK coincide with the phase of the read signal RD (preamble signal) (actually the output signal S11 of the ADC 83) from which the preamble data is read. As a result, the sync byte (SB) and data read after the preamble data are sampled at an accurate timing. However, at the start of the read operation, the TR-PLL 84 cannot sufficiently perform phase pull-in, so the phase of the reference clock signal SCK may not match the phase of the preamble signal.
[0217]
The shift register 15 of the DFE 82 samples the determination signal S4 that is a determination result of the determination unit 14 based on the reference clock signal SCK, and sequentially stores the sampled data. Therefore, if the phase of the reference clock signal SCK does not match the phase of the preamble signal, the shift register 15 stores incorrect data. This erroneous data is fed back to the adder 13 via the FB filter 22. As a result, the FB loop propagates erroneous data, and the FB loop diverges. This divergence of the FB loop hinders data reproduction and lengthens the time required for the read operation.
[0218]
On the other hand, the signal processing circuit 81 of the present embodiment opens the FB loop at the start of the reading operation, and determines the initial value of the FB filter 22 based on the initial value calculated by the digital arithmetic circuit 85. The signal processing circuit 81 operates the FB loop from the determined initial value.
[0219]
This prevents the FB loop from diverging by feeding back the data sampled by the reference clock signal SCK that is not sufficiently synchronized with the read signal RD at the start of the read operation. Furthermore, by calculating the initial value of the FB filter 22 and setting it in the shift register, the time until the FB loop operates stably becomes shorter than when the initial value is not used.
[0220]
As described above, according to the present embodiment, the following effects can be obtained.
(1) The signal processing circuit 81 controls the second switch 87 at the start of the reading operation to open the FB loop. The signal processing circuit 81 controls the first switch 86 to perform the synchronization pull-in of the TR-PLL 84 based on the output signal S1 of the prefilter 12. Thereafter, the signal processing circuit 81 feeds back the initial value determined by controlling the second switch 87 to the adder 13 to operate the FB loop. As a result, at the start of the read operation, data sampled by the reference clock signal SCK that is not sufficiently synchronized with the read signal RD is not fed back to the adder 13, thereby preventing the FB loop from diverging. it can.
[0221]
(2) The signal processing circuit 81 determines the initial value of the FB filter 22 based on the initial value calculated by the digital arithmetic circuit 85. The signal processing circuit 81 operates the FB loop by feeding back the initial value determined by controlling the second switch 87 to the adder 13. Thus, by calculating the initial value of the FB filter 22 and setting it in the shift register, erroneous data does not propagate through the RB loop. As a result, the time until the FB loop operates stably can be shortened compared to the case where the initial value is not used.
[0222]
(Fifth embodiment)
Hereinafter, a fifth embodiment of the present invention will be described with reference to FIG.
For the sake of convenience of explanation, the same components as those of the fourth embodiment in FIG.
[0223]
FIG. 23 is a partial block circuit diagram of the signal processing circuit 81a of the present embodiment.
The signal processing circuit 81a includes a DFE 82, an ADC 83, and a digital arithmetic circuit (hereinafter simply referred to as an arithmetic circuit) 88. The arithmetic circuit 88 includes a digital filter 89, a timing recovery PLL circuit (hereinafter referred to as TR-PLL) 90, and a register 91.
[0224]
The digital filter 89 is a filter that performs waveform equalization optimal for the preamble. The digital filter 89 outputs the filtered signal to the TR-PLL 90. The TR-PLL 90 performs synchronization pull-in of the reference clock signal SCK with respect to the preamble based on the output signal of the digital filter 89. Synchronization pull-in includes frequency pull-in that matches the frequency of the reference clock signal SCK with the frequency of the preamble, and phase pull-in that matches the phase of the reference clock signal SCK with the phase of the preamble.
[0225]
The TR-PLL 90 includes a register 91 that stores a periodic pattern corresponding to a preamble in advance. When the TR-PLL 90 detects the input of the preamble, it first performs frequency acquisition. The TR-PLL 90 detects the input of the preamble by comparing the pattern of the output signal S12 of the digital filter 89 with the periodic pattern.
[0226]
For example, a 6T pattern preamble is configured such that “111” and “000” appear alternately and periodically. The register 91 stores a periodic pattern “111000” in the preamble. The TR-PLL 90 performs preamble detection when the output signal S12 of the digital filter 89 is “111” or “000”.
[0227]
After completing the frequency pull-in, the TR-PLL 90 next performs phase pull-in based on the output signal S12 of the digital filter 89. Thereby, the TR-PLL 90 matches that of the reference clock signal SCK with the frequency and phase of the preamble. The TR-PLL 90 outputs the reference clock signal SCK subjected to the synchronization to the shift register 15 of the ADC 83 and DFE 82.
[0228]
The register 91 stores an initial value of the feedback filter 22. This initial value is calculated in advance based on the preamble and stored in the register 91. The arithmetic circuit 88 outputs the initial value stored in the register 91 to the shift register 15 of the DFE 82 when the frequency pull-in is performed in the TR-PLL 90. The arithmetic circuit 88 may be configured to calculate an initial value from time to time and output the calculation result to the shift register 15.
[0229]
As described above, according to the present embodiment, the following effects can be obtained.
(1) The same effect as (1) of the fourth embodiment can be obtained.
(2) The arithmetic circuit 88 presets the shift register 15 based on the initial value of the feedback filter 22 stored in the register 91 in advance. As a result, the calculation of the initial value is not required, and the shift register 15 can be preset to prevent divergence.
[0230]
(3) By providing the digital filter 89 that performs waveform equalization optimal for the preamble, the TR-PLL 90 can easily pull the reference clock signal SCK into the preamble.
[0231]
(Sixth embodiment)
Hereinafter, a sixth embodiment of the present invention will be described with reference to FIG.
For the sake of convenience of explanation, the same components as those of the fourth embodiment in FIG.
[0232]
FIG. 24 is a partial block circuit diagram of the signal processing circuit 81b of this embodiment.
The signal processing circuit 81b includes a DFE 82, an ADC 83, a digital signal processor (DSP) 92, and a voltage controlled oscillator (VCO) 93.
[0233]
The DSP 92 has a function of performing waveform equalization optimal for the preamble and a function of detecting the frequency difference and phase difference between the signal after waveform equalization and the reference clock signal SCK output from the VCO 93. The DSP 92 outputs a signal based on the detected frequency difference and phase difference to the VCO 93. The VCO 93 outputs a reference clock signal SCK having a frequency and phase based on the output signal of the DSP 92.
[0234]
The DSP 92 has a function of calculating an initial value of the FB filter 22. The DSP 92 outputs the calculated initial value to the shift register 15 of the DFE 82. The FB filter 22 calculates the feedback amount of the FB loop based on the initial value stored in the shift register 15.
[0235]
As described above, according to the present embodiment, the following effects can be obtained.
(1) The signal processing circuit 81b can simplify the configuration by performing signal processing for detecting the frequency difference and phase difference necessary for the presetting of the shift register 15 and the synchronization pull-in of the reference clock signal SCK by the DSP 92. it can. As a result, the chip size of the signal processing circuit 81b can be reduced.
[0236]
In the above embodiment, the following modifications may be made.
The output signal S11 of the ADC 83 of the fourth to sixth embodiments may be used for purposes other than generating the reference clock signal SCK. For example, as shown in FIG. 25, a signal processing circuit 81c used for outputting a servo signal to the servo circuit 36 may be used. The signal processing circuit 81c includes a digital filter 94 for filtering servo information. The filter 94 performs a waveform equalization process optimal for servo information on the output signal S11 of the ADC 83, and outputs the processed signal to the servo circuit. The servo circuit 36 controls the second motor M <b> 2 in FIG. 1 based on the output signal of the filter 94 to turn on the head device 34. As a result, the signal processing circuit 81c and the servo circuit 36 can be mounted on one chip. As a result, in addition to the effects of the fourth embodiment, the configuration of the hard disk device 31 can be simplified.
[0237]
In addition, as shown in FIG. 26, the signal processing circuit 81d including the phase control circuit 95 may be used. With this configuration, the phase control can be processed digitally.
[0238]
(Seventh embodiment)
A seventh embodiment embodying the present invention will be described below with reference to FIGS. For the sake of convenience of explanation, the same components as those of the fourth embodiment in FIG.
[0239]
FIG. 27 shows a partial block circuit diagram of the signal processing circuit 101 of the present embodiment.
The signal processing circuit 101 includes a decision feedback equalizer (hereinafter referred to as DFE) 82, an ADC 83, a digital filter 102, a zero phase restart circuit 103, and a timing recovery PLL circuit (hereinafter referred to as TR-PLL) 104.
[0240]
The digital filter 102 equalizes the preamble data into an optimum waveform. The digital filter 102 outputs a waveform-equalized signal S21 to a zero phase restart circuit (hereinafter simply referred to as restart circuit) 103.
[0241]
The restart circuit 103 generates a reference clock signal SCK based on the output signal S21 of the digital filter 102 and outputs it to the TR-PLL 104. The TR-PLL 104 generates a system clock signal SCK to be supplied to the shift register 15 of the ADC 83 and DFE 83. The TR-PLL 104 performs phase pull-in to match the phase of the system clock signal SCK with the phase of the read signal RD read from the magnetic disk 33 in FIG. 2 based on the reference clock signal SCK.
[0242]
The restart circuit 103 determines the phase of the reference clock signal SCK supplied to the TRPLL and the read signal RD based on control data (specifically, preamble data) included in the read signal RD read from the magnetic disk 33 in FIG. It has a function of performing initial phase pull-in. The initial phase pull-in operates so that the phase of the reference clock signal SCK substantially matches the phase of the read signal RD. This initial phase acquisition shortens the phase acquisition time in the TR-PLL 104.
[0243]
That is, the TR-PLL 104 requires a time corresponding to the phase difference between the system clock signal SCK to be generated and the read signal RD for phase acquisition. Therefore, if the system clock signal SCK and the read signal RD are out of phase, the time required for phase acquisition becomes longer. This lengthens the time until data reading, and hinders speeding up of the reading process.
[0244]
Further, when the phase of the system clock signal SCK and the phase of the read signal RD are greatly shifted, the TR-PLL 104 sufficiently draws the phase of the system clock signal SCK into the phase of the read signal RD (the phase shift is almost zero). You may not be able to). These make data sampling inaccurate and require repeated execution of the reading process, which also hinders the speeding up of the reading process.
[0245]
On the other hand, the restart circuit reduces the phase difference of the read signal RD with respect to the reference clock signal SCK smaller than that of the output signal of the ADC 83 by performing the initial phase pull-in. The TR-PLL 104 pulls in the phase of the system clock signal SCK based on the phase difference between the reference clock signal SCK and the system clock signal SCK. As a result, the time required for the phase pull-in is shorter than when the phase of the system clock signal SCK is pulled into the read signal RD based on the output signal of the ADC 83.
[0246]
Further, the restart circuit 103 has a function of presetting the shift register 15 of the DFE 82. The restart circuit 103 holds a plurality of data obtained by sampling the output signal S11 of the ADC 83 when performing the initial phase pull-in. Based on the held data, the restart circuit 103 extracts the characteristics of a read signal RD (hereinafter simply referred to as a “printable signal”) from which the preamble data has been read. Based on the extracted features, initial phase pulling is performed to match the phase of the reference clock signal SCK with the printable signal.
[0247]
When the initial phase acquisition is completed, the restart circuit 103 presets the shift register 15 based on the stored data. With this configuration, similarly to the fourth to sixth embodiments, error data of the DFE 82 in the initial phase pull-in can be preset to suppress feedback loop divergence.
[0248]
Next, the configuration of the restart circuit 103 will be described in detail.
FIG. 28 shows a schematic block circuit diagram of the restart circuit 103. The restart circuit 103 is a circuit for performing initial phase pull-in based on a 4T pattern preamble signal. In FIG. 28, the digital filter 102 of FIG. 27 is omitted.
[0249]
The restart circuit 103 includes a first shift register 105, a slope calculation circuit 106, a second shift register 107, a phase difference detection circuit 108, a pattern determination circuit 109, a third shift register 110, a register 111, a phase control decoder 112, and a sequencer 113. , A phase holding register 114, a clock switching circuit 115, and a voltage controlled oscillator (VCO) 116 as a clock signal generation circuit.
[0250]
The output signal S11 of the ADC 83 is input to the first shift register 105 of the restart circuit 103. The first shift register 105 includes two registers 105a and 105b that operate based on the clock signal CLK1. The clock signal CLK1 is generated by a clock circuit (not shown) based on the reference clock signal SCK.
[0251]
Each of the registers 105a and 105b has a function of holding data of a plurality of bits (the number of bits of the output signal of the ADC 83). Therefore, the first shift register 105 holds two data obtained by sampling the output signal S11 of the ADC 83 based on the clock signal CLK1. The first shift register 105 outputs the held data to the slope calculation circuit 106.
[0252]
The inclination calculation circuit 106 calculates the inclination of the line segment connecting the coordinates of the two data based on the two data input from the first shift register 105. The inclination calculation circuit 106 outputs the calculation result to the second shift register 107.
[0253]
The second shift register 107 includes three registers 107a to 107c that operate based on the clock signal CLK1. Therefore, the second shift register 107 holds data output from the slope calculation circuit 106 at that time and two data output before that data. Each data is a slope value between two consecutive sampling points. Therefore, the second shift register 107 holds three slope values between four consecutive sampling points, and outputs the held three data to the phase difference detection circuit 108.
[0254]
The first-stage register 105 a constituting the first shift register 105 outputs the held data to the pattern determination circuit 109. A predetermined slice level is input to the pattern determination circuit 109. The pattern determination circuit 109 sequentially determines the data level based on the slice level. Then, the pattern determination circuit 109 outputs a determination signal S22 based on the determination result to the third shift register 110.
[0255]
More specifically, the pattern determination circuit 109 receives the first and second determination levels as slice levels. The first determination level is set to a level higher than the second determination level. For example, the first determination level is set to + α (v) and the second determination level is set to −α (v) and input.
[0256]
The pattern determination circuit 109 compares the output data level of the first shift register 105 with the first and second determination levels. Then, the pattern determination circuit 109 outputs a determination signal S22 of “1” when the output data is larger than the first determination level. The pattern determination circuit 109 outputs a determination signal S22 of “0” when the output data is a level between the first determination level and the second determination level. Further, the pattern determination circuit 109 outputs a determination signal S22 of “−1” when the output data is smaller than the second determination level.
[0257]
The third shift register 110 includes four registers 101a to 101d that operate based on the clock signal CLK1. Therefore, the third shift register 110 holds data that is the determination result output from the pattern determination circuit 109 at that time and three data output from the pattern determination circuit 109 before that data. That is, the third shift register 110 holds data at four consecutive sampling points. Each data represents a pattern of four sampling points obtained by sampling the output signal S11 of the ADC 83. The third shift register 110 outputs the held four data to the phase difference detection circuit 108.
[0258]
The phase difference detection circuit 108 detects the phase difference of the reference clock signal SCK with respect to the input signal (read signal RD) of the ADC 83 based on the output data of the second and third shift registers 117 and 110. More specifically, the phase difference detection circuit 108 selects one of the output data of the second shift register 107 based on the output data of the third shift register 110.
[0259]
The third shift register 110 holds data of four sampling points obtained by sampling the preamble signal. The phase difference between the output signal S11 of the ADC 83 and the reference clock signal SCK (sampling clock CLK1) appears as the slope of the sampling point. That is, the slope is 0 (zero) when the phases are matched. And the inclination of a sampling point becomes large, so that a phase difference is large.
[0260]
Further, in the preamble signal of 4T pattern, the determination result of the pattern determination circuit 109 corresponds to “1100” which is the pattern of the preamble signal. Therefore, the phase difference between the preamble signal and the reference clock signal SCK can be detected by examining the slopes of two sampling points that are “11” or “00”.
[0261]
Therefore, the phase difference detection circuit 108 calculates the inclination (phase difference) at the sampling point of the pattern “11” or “00” based on the pattern of the four consecutive sampling points held in the third shift register 110. Input is made from the second shift register 107.
[0262]
The phase difference detection circuit 108 outputs data based on the detected phase difference to the first register 111. The first register 111 latches the output data of the phase difference detection circuit 108 and outputs the latched data to the phase control decoder 112.
[0263]
The phase control decoder 112 is controlled by the sequencer 113.
The phase control decoder 112 generates control data obtained by decoding both data based on the data input from the first register 111 and the data input from the second register (phase holding register) 114. The second register 114 latches control data generated and output by the phase control decoder 112 based on the previous sampling data. Therefore, the phase control decoder 112 generates the control data at that time based on the data latched in the first register 111 at that time and the control data generated immediately before that time. Then, the phase control decoder 112 outputs the generated control data to the second register 114. The second register 114 latches the output data of the phase control decoder 112 and outputs the latched control data to the clock switching circuit 115.
[0264]
A plurality (six in this embodiment) of clock signals CK <b> 1 to CK <b> 6 generated by the VCO 116 are input to the clock switching circuit 115. As shown in FIG. 29, these clock signals CK1 to CK6 have the same frequency and different phases. More specifically, the VCO 116 equally divides one period (six divisions) of the reference first clock signal CK1, and generates clock signals CK2 to CK6 whose phases are shifted by the equally divided period. Note that the second to fourth clock signals CK2 to CK4 are ahead of the first clock signal CK1 with respect to the reference first clock signal CK1, and the fifth and sixth clock signals CK5 and CK6 are the first ones. The phase is delayed with respect to one clock signal. The clock signals CK1 to CK6 are generated so as to be CK4, CK3, CK2, CK1, CK6, and CK5 in order from the phase progressing.
[0265]
The clock switching circuit 115 selects one of the first to sixth clock signals CK <b> 1 to CK <b> 6 based on the control data input from the phase control decoder 112. Then, the clock switching circuit 115 outputs the selected clock signal to the TR-PLL 104 as the reference clock signal SCK.
[0266]
Next, the operation of the zero phase restart circuit 103 configured as described above will be described with reference to FIG.
Now, the sampling clock CLK1 is generated based on the first clock signal CK1 (reference clock signal SCK). The restart circuit 103 samples the sampling points P1 to P4 based on the sampling clock CLK1. Based on these points P1 to P4, the second shift register 107 stores the gradient between the points P1-P2, P2-P3, P3-P4. The third shift register 110 stores the pattern “1100” based on the determination result of the pattern determination circuit 109.
[0267]
Based on the pattern stored in the third shift register 110, the phase difference detection circuit 108 inputs the slope between the points P1 and P2 that becomes “11”. Note that the slope between the points P3 and P4 that becomes “00” may be input.
[0268]
The phase difference detection circuit 108 determines that the phase is advanced based on the input gradient, and generates control data for delaying the phase of the reference clock signal SCK. Then, the phase difference detection circuit 108 outputs control data to the clock switching circuit 115 via the second register 114.
[0269]
Based on the control data, the clock switching circuit 115 selects the sixth clock signal CK6 whose phase is slower than that of the first clock signal CK1, and outputs the sixth clock signal CK6 as the reference clock signal SCK.
[0270]
Next, the restart circuit 103 samples the points P5 to P8 with the sampling clock CLK1 based on the sixth clock signal CK6. Similarly to the above, the second shift register 107 stores the slopes between the points P5-P6, P6-P7, and P7-P8. The third shift register 110 stores the pattern “0110”.
[0271]
The phase difference detection circuit 108 inputs the inclination between the points P6 and P7 that becomes “00”, and determines that the phase is advanced based on the inclination. Based on the determination result, the phase difference detection circuit 108 generates control data for delaying the phase of the reference clock signal SCK. Then, the phase difference detection circuit 108 outputs control data to the clock switching circuit 115 via the second register 114.
[0272]
The clock switching circuit 115 selects the fifth clock signal CK5 whose phase is later than that of the sixth clock signal CK6 based on the control data, and outputs the fifth clock signal CK5 as the reference clock signal SCK.
[0273]
Next, the restart circuit 103 samples the points P9 to P12 with the sampling clock CLK1 based on the fifth clock signal CK5. Similarly to the above, the second shift register 107 stores the slopes between the points P9-P10, P10-P11, P11-P12. The third shift register 110 stores the pattern “0011”.
[0274]
The phase difference detection circuit 108 inputs the slope between the points P11 and P12 that becomes “11”, and determines that the phases match based on the slope. Based on the determination result, the sequencer 113 stops the phase control decoder 112.
[0275]
At this time, control data for selecting the fifth clock signal CK5 is held in the second register 114. The restart circuit 103 continuously outputs the reference clock signal SCK based on the fifth clock signal CK5.
[0276]
The sequence control circuit 54 in FIG. 2 controls the restart circuit 103 and the TR-PLL 104 configured as described above according to the timing shown in FIG. That is, when reading of the preamble is started, the sequence control circuit 54 receives the L level start signal XRG from the MPU 37 of FIG. The sequence control circuit 54 outputs an H level phase control signal CNZ based on the L level start signal XRG.
[0277]
Further, the sequence control circuit 54 outputs first and second control signals SG1 and SG2. As a result, the output signal S1 of the prefilter 12 is input to the restart circuit 103. In response to the phase control signal CNZ, the restart circuit 103 starts the initial phase pull-in based on the signal S1.
[0278]
The restart circuit 103 presets the shift register 15 of the DFE 82 when the initial phase pull-in is completed. In response to this, the sequence control circuit 54 outputs the L-level phase control signal CNZ, and outputs the H-level frequency control signal CT2. The sequence control circuit 54 outputs first and second control signals SG1 and SG2. As a result, the FB loop of the DFE 82 is closed, and the output signal S3 of the adder 13 is input to the TR-PLL 104. Then, the TR-PLL 104 performs frequency pull-in based on the output signal S3 in response to the H level control signal CT2.
[0279]
Upon completion of reading of the preamble, the sequence control circuit 54 receives it and outputs an L level frequency control CT2. When the sync byte is detected, the control data detection circuit 53 in FIG. 2 outputs a sync byte detection signal SB to the MPU 37. Based on the sync byte detection signal SB, the MPU 37 processes the data following the sync byte as data.
[0280]
As described above, according to the present embodiment, the following effects can be obtained.
(1) A zero phase restart circuit 103 is provided, and the restart circuit 103 performs initial phase pull-in of the preamble signal and the reference clock signal SCK. As a result, the time required for the synchronization pull-in in the TR-PLL 104 is shortened, and it is possible to speed up the read operation by speeding up the establishment of synchronization.
[0281]
(2) The zero phase restart circuit 103 extracts the characteristics of the preamble signal, and calculates the phase difference between the preamble signal and the reference clock signal SCK based on the characteristics. As a result, it is possible to easily detect the phase difference and shorten the time required for initial synchronization pull-in.
[0282]
(3) The VCO 116 that generates a plurality of clock signals CK1 to CK6 having different phases is provided, and one of the clock signals CK1 to CK6 is selected according to the calculated phase difference. As a result, the clock signal CLK having a phase close to that of the preamble signal can be easily output.
[0283]
In the above embodiment, the following modifications may be made.
The sequence control circuit 54 of the above embodiment may be configured to perform phase acquisition step by step in response to two types of preamble signals. That is, as shown in FIG. 32, the 6T pattern preamble is read from the magnetic disk 33 in FIG. 2 following the 4T pattern preamble. The sequence control circuit 54 outputs an H level phase control signal CNZ in response to the start signal XRG.
[0284]
Further, the sequence control circuit 54 outputs first and second control signals SG1 and SG2. As a result, the output signal S1 of the prefilter 12 is input to the restart circuit 103. In response to the phase control signal CNZ, the restart circuit 103 starts initial phase pull-in based on the 4T pattern preamble signal.
[0285]
The restart circuit 103 presets the shift register 15 of the DFE 82 when the initial phase pull-in is completed. In response to this, the sequence control circuit 54 outputs an L level phase control signal CNZ.
[0286]
Next, when the 6T pattern preamble is read, the sequence control circuit 54 outputs the H-level frequency control signal CT2. The sequence control circuit 54 outputs first and second control signals SG1 and SG2. As a result, the FB loop of the DFE 82 is closed, and the output signal S3 of the adder 13 is input to the TR-PLL 104. The TR-PLL 104 performs frequency pull-in based on the 6T pattern preamble signal in response to the H-level control signal CT2.
[0287]
(Eighth embodiment)
Hereinafter, an eighth embodiment embodying the present invention will be described with reference to FIGS. For convenience of explanation, the same reference numerals are given to the same configurations as those of the conventional example of FIG. 54 and the first embodiment, and a part of the description is omitted.
[0288]
FIG. 33 shows a partial circuit diagram of the signal processing circuit 121 of the present embodiment.
The signal processing circuit 121 includes a decision feedback equalizer (DFE) 82, an analog-digital converter (hereinafter referred to as ADC) 122, a zero phase restart circuit (hereinafter referred to as restart circuit) 123, and a clock signal generation circuit. Timing recovery PLL circuit (hereinafter referred to as TR-PLL) 124. In FIG. 33, the feedback filter 22 and the first and second switches 86 and 87 constituting the DFE 82 are omitted.
[0289]
The ADC 122 converts the output signal S3 of the adder 13 into a digital signal having a predetermined number of bits (6 bits in this embodiment), and outputs the digital signal to the restart circuit 123.
[0290]
The restart circuit 123 is a circuit corresponding to 6T pattern preamble data. The 6T pattern is a periodic pattern (111000111000...) In which data of the same value appears in one cycle in six periods (6 clocks) of the system clock signal SCK.
[0291]
The restart circuit 123 includes a print detection circuit 125, an arithmetic circuit 126, a decode circuit 127, a selection circuit 128, and a frequency divider 129.
Data stored in the shift register 15 of the DFE 82 is input to the preamble detection circuit 125. When the preamble detection circuit 125 detects a read signal RD (hereinafter referred to as a preamble signal) from which the preamble data is read based on the input data, the preamble detection circuit 125 outputs a detection signal S25 to the arithmetic circuit 126.
[0292]
Further, the preamble detection circuit 125 has a function of presetting the shift register 15 with the preamble data when detecting the preamble signal. As in the fourth embodiment, the preset function presets the feedback amount of the feedback loop of the DFE 82 and prevents the FB loop of the DFE 82 from diverging.
[0293]
The arithmetic circuit 126 responds to the detection signal S25 input from the preamble detection circuit 125, and at that time, pulls the initial phase of the system clock signal SCK with respect to the output signal S26 of the ADC 122. The detection signal S25 is a result of detecting a preamble signal. Accordingly, the arithmetic circuit 126 calculates a cross-correlation function in the sampling data of the preamble signal in response to the detection signal S25. Further, the arithmetic circuit 126 calculates the phase difference between the print signal and the reference clock signal SCK based on the calculated cross-correlation function. Then, the arithmetic circuit 126 outputs a signal corresponding to the calculated phase difference to the decoding circuit 127.
[0294]
The decoding circuit 127 decodes the output signal of the arithmetic circuit 126 to generate a selection signal S27, and outputs the selection signal S27 to the selection circuit 128. A plurality of clock signals CK <b> 1 to CK <b> 6 having different phases are input from the TR-PLL 124 to the selection circuit 128. The selection circuit 128 selects one of the plurality of clock signals CK1 to CK6 based on the selection signal S27, and outputs the selected clock signal as the system clock signal SCK. The phase of the system clock signal SCK substantially matches the phase of the preamble signal. The TR-PLL pulls in the phase of the system clock signal SCK and the preamble signal output from the ADC 122. This shortens the time required for phase pull-in as in the seventh embodiment.
[0295]
The outline of the principle of the restart circuit 123 of this embodiment will be described.
The preamble signal is a signal obtained by reading preamble data that is a periodic pattern. This preamble signal is the target that pulls in the phase. It is assumed that the function fc (τ) of this preamble signal.
[0296]
First, the arithmetic circuit 126 generates two reference signals having different phases from the reference clock signal SCK. At this time, the arithmetic circuit 126 is delayed by one symbol rate (one cycle of the reference clock signal SCK) in phase with respect to the reference clock signal SCK and one symbol rate phase behind the reference clock signal SCK. A second reference signal is generated.
[0297]
Next, the arithmetic circuit 126 calculates cross-correlation functions ff (τ) and fd (τ) of the preamble signal and the first and second reference signals, respectively. The arithmetic circuit 126 calculates a difference dcn (τ) (= | ff (τ) −fd (τ) |) between the two calculated cross-correlation functions ff (τ) and fd (τ). As shown in FIG. 35, the value of the difference dcn (τ) (the value on the vertical axis in FIG. 35) is proportional to the phase difference (phase shift) between the reference clock signal SCK and the preamble signal. Therefore, a clock signal close to the phase of the preamble signal is selected from the plurality of clock signals output from the TR-PLL 124 based on this difference. In this way, the restart circuit 123 performs initial phase drawing.
[0298]
Next, the configuration of the arithmetic circuit 126 and the decode circuit 127 will be described in detail with reference to FIG.
The output signal S26 of the ADC 122 is input to the first register 131 of the arithmetic circuit 126. The first register 131 latches the output signal S26 based on the clock signal CK, and outputs the latched signal to the first and second adders 132a and 132b. Control signals CNTL1 and CNTL0 are input from the control circuit 133 to the first and second adders 132a and 132b. The control circuit 133 receives the detection signal S25 output from the pullamble detection circuit 125 in FIG. 33 and the reference clock signal SCK. The control circuit 133 generates the control signals CNTL1 and CNTL0 based on the detection signal S25 as shown in FIG. 36, and outputs them to the first and second adders 132a and 132b.
[0299]
The output signal S32a of the second register 134a is input to the first adder 132a. The first adder 132a performs an addition operation on the output signal of the first register 131 and the output signal S32a of the second register 134a based on the control signals CNTL1 and CNTL0.
[0300]
As shown in FIG. 36, for example, when the control signals CNTL1 and CNTL0 are “00”, the first adder 132a outputs a result x obtained by adding the input a (output signal S26) and the input b (output signal S32a). To do. When the control signals CNTL1 and CNTL0 are “01”, the first adder 132a outputs a result x obtained by adding the input −a (inverted signal of the output signal S26) and the input b (output signal S32a).
[0301]
The first adder 132a outputs the calculation result to the second register 134a. The second register 134a latches the output signal S31a of the first adder 132a based on the clock signal CK.
[0302]
The output signal S32b of the third register 134b is input to the second adder 132b. The second adder 132b adds the output signal of the first register 131 and the output signal S32b of the third register 134b based on the control signals CNTL1 and CNTL0, and outputs the calculation result to the third register 134b. The third register 134b latches the output signal S31b of the second adder 132b based on the clock signal CK.
[0303]
With the above configuration, the first adder 132a and the second register 134a generate a reference signal that is different in phase by one symbol rate with respect to the preamble signal that is an input signal, and the reference signal and the preamble signal are mutually reciprocated. A first correlator for calculating a correlation function is configured. Similarly, the second adder 132b and the third register 134b generate a reference signal that is different in phase by one symbol rate with respect to a preamble signal that is an input signal, and a cross-correlation function between the reference signal and the preamble signal. The 2nd correlator which calculates is comprised.
[0304]
The second and third registers 134a and 134b output the output signals S32a and S32b to the first and second subtracters 135a and 135b, respectively. The first subtracter 135a subtracts the output signal S32b of the third register 134b from the output signal S32a of the second register 134a, and outputs the subtraction result to the fourth register 136a. The fourth register 136a latches the output signal based on the clock signal CK and outputs the latched signal S33a to the selection circuit 137. The fourth register 136a outputs the sign bit f1a of the output signal S33a to the decoder 139 of the decoding circuit 127.
[0305]
The second subtracter 135b subtracts the output signal S32a of the second register 134a from the output signal S32b of the third register 134b, and outputs the subtraction result to the fifth register 136b. The fifth register 136b latches the output signal based on the clock signal CK, and outputs the latched signal S33b to the selection circuit 137. The fifth register 136b outputs the sign bit f1b of the output signal S33b to the decoder 139.
[0306]
The decoder 139 generates a selection signal SL1 corresponding to a positive sign bit based on the sign bits f1a and f1b input from the fourth and fifth registers 136a and 136b, and sends the selection signal SL1 to the selection circuit 137. Output. The selection circuit 137 outputs a positive value signal S34 selected from the output signals S33a and S33b of the fourth and fifth registers 136a and 136b to the first to third comparators 138a to 138c based on the selection signal SL1. . With this configuration, the absolute values of the output signals of the first and second correlators are input to the first to third comparators 138a to 138c.
[0307]
First to third comparison signals R1 to R3 are input to the first to third comparators 138a to 138c, respectively. The first to third comparison signals R1 to R3 are values of the first to third comparison levels Low to High for the phases P3 to P1, Z, and N1 to N3 shown in FIG. 37, and these values are added to the reference clock signal CK. On the other hand, this corresponds to the phase difference between the plurality of clock signals CK1 to CK6 generated by the TR-PLL124.
[0308]
More specifically, the TR-PLL 124 equally divides one period (six divisions) of the reference first clock signal CK1 into the equal divisions as in the VCO 116 (see FIG. 28) of the seventh embodiment. Second to sixth clock signals CK2 to CK6 whose phases are shifted by a period are generated (see FIG. 29).
[0309]
Note that the second to fourth clock signals CK2 to CK4 are advanced in phase by 1/6 period from the first clock signal CK1, and the sixth and fifth clock signals CK6 and CK5 are 1 more than the first clock signal CK1. The phase is delayed by 6 cycles. Further, the fourth clock signal CK4 has a 3/6 cycle phase advance than the first clock signal CK1. This is equivalent to a 3/6 cycle phase being delayed from the first clock signal CK1.
[0310]
The level of the first comparison signal R1 is set to a value corresponding to the phase difference between the reference first clock signal CK1 and the second and sixth clock signals CK2 and CK6. The level of the second comparison signal R2 is set to a value corresponding to the phase difference between the first clock signal CK1 and the third and fifth clock signals CK3 and CK5. The level of the third comparison signal R3 is set to a value corresponding to the phase difference between the first clock signal CK1 and the fourth clock signal CK4.
[0311]
The first to third comparators 138a to 138c respectively compare the level of the output signal S34 of the selection circuit 137 with the levels of the first to third comparison signals R1 to R3, and signals S35a to S35c based on the comparison result. Is output to the decoder 139. Specifically, the first to third comparators 138a to 138c receive the signals S35a to S35c at the H level (1) when the level of the preamble signal is higher than that of the first to third comparison signals R1 to R3. When the level of the signal is smaller than that of the first to third comparison signals R1 to R3, L level (0) signals S35a to S35c are output, respectively.
[0312]
For example, when the phase difference between the preamble signal and the reference clock signal (first clock signal) CK1 is within 1/6 cycle (phase Z in FIG. 38), both the first to third comparators 138a to 138c are “0”. The signals S35a to S35c are output. When the phase difference between the preamble signal and the reference clock signal CK1 is not less than 1/6 period and not more than 2/6 period (phase P1 in FIG. 38), the first comparator 138a generates the signal S35a of “1” as the first 2. The third comparators 138b and 138c output "0" signals S35b and S35c.
[0313]
The decoder 139 generates the phase selection signal S36 based on the output signals S35a to S35c of the first to third comparators 138a to 138c and the sign bit f1a constituting the output signal S33a of the fourth register 136a. The sign bit indicates whether the phase of the preamble signal is advanced or delayed with respect to the phase of the reference clock signal CK1. Accordingly, in response to the sign bit f1a of “0”, the decoder 139 selects the second to fourth clock signals CK2 to CK4 whose phases are ahead of the first clock signal CK1 based on the output signals S35a to S35c. A phase selection signal S36 is generated. In response to the sign bit of “1”, the decoder 139 selects the sixth to fourth clock signals CK6 to CK4 whose phases are delayed from the first clock signal CK1 based on the output signals S35a to S35c. A selection signal S36 is generated.
[0314]
For example, when the output signals S35a to S35c are all “0”, the decoder 139 generates the phase selection signal S36 to select the first clock signal CK1. Further, when the output signals S35a to S35c are “100”, the decoder 139 outputs the second clock signal CK2 corresponding to the sign bit of “0” and the sixth clock signal CK6 corresponding to the sign bit of “1”. A phase selection signal S36 is generated to select.
[0315]
The decoder 139 outputs the generated phase selection signal S36 to the sixth register 140.
The sixth register 140 receives the zero phase selection signal SL0 from the control circuit 133. The sixth register 140 latches the phase selection signal S36 output from the decoder 139 in response to the rising edge of the zero phase selection signal SL0, and outputs the latch signal as the selection signal S27 to the selection circuit 128 of FIG. The selection circuit 128 selects one of the first to sixth clock signals CK1 to CK6 output from the TR-PLL 124 based on the selection signal S27, and divides the selected clock signal as the reference clock signal SCK. Output to the frequency divider 129. The frequency divider 129 outputs to the ADC 122 a clock signal CKa obtained by dividing the frequency of the reference clock signal SCK by 1/2.
[0316]
As shown in FIG. 39, the restart circuit 123 configured as described above obtains a cross-correlation function value for one period of a 6T-pattern preamble signal from the points sampled based on the reference clock signal SCK, and calculates the mutual correlation function value. Based on the correlation function value, initial phase acquisition is performed to roughly match the phase of the reference clock signal SCK with respect to the phase of the preamble signal.
[0317]
The TR-PLL 124 receives the output signal S26 of the ADC 122. Then, the TR-PLL 124 pulls in the phase of the reference clock signal SCK from which the initial phase has been pulled in with respect to the phase of the preamble signal, and matches the phase of the reference clock signal SCK with the phase of the preamble signal. As a result, the time required for the phase pull-in becomes shorter than in the prior art.
[0318]
As shown in FIG. 40, the ADC 122 of FIG. 33 includes a main ADC 141 and a plurality (two in this embodiment) of auxiliary ADCs 142a and 142b.
The main ADC 141 can convert the output signal S3 of the adder 13 into a digital signal, and has an input range (signal input range) centered on 0V. The main ADC 141 receives a clock signal CKa obtained by dividing the reference clock signal SCK by 1/2. The main ADC 141 sequentially converts the output signal S3 into a 6-bit digital signal based on the rising edge of the divided clock signal CKa, and outputs the digital signal to the arithmetic circuit 126 and the TR-PLL 124 in FIG.
[0319]
The auxiliary ADCs 142a and 142b have an input range narrower than that of the main ADC 141 with a predetermined reference voltage set for each of them as a center. Each auxiliary ADC 142a, 142b receives an inverted clock signal XCKa that is complementary to the clock signal CKa. Each auxiliary ADC 142a, 142b converts the output signal S3 into a 3-bit digital signal based on the rising edge of the inverted clock signal, and outputs the digital signal to the arithmetic circuit 126 and TR-PLL 124 of FIG.
[0320]
As shown in FIG. 41, the divided clock signal CKa and the inverted clock signal XCKa, which are complementary signals, alternately appear at every rising edge of the reference clock signal SCK. The time between the rising edge of the divided clock signal CKa and that of the inverted clock signal XCKa is the same as the time between the rising edges of the reference clock signal SCK. Therefore, the main ADC 141 and the auxiliary ADCs 142a and 142b alternately perform AD conversion in synchronization with the rising edge of the reference clock signal SCK.
[0321]
The reference voltages of the auxiliary ADCs 142a and 142b are set to different voltages. As shown in FIG. 43, the first auxiliary ADC 142a is centered on the first reference voltage + Ref, and the second auxiliary ADC 142b is centered on the second reference voltage -Ref.
[0322]
Each reference voltage + Ref, -Ref corresponds to the voltage at the sampling point of the preamble signal. That is, as shown in FIG. 42, when the preamble signal is sampled by the reference clock signal SCK, the voltages at the sampling points are voltages in the vicinity of the voltages RefH, RefL, -RefL, and -RefH. The TR-PLL 124 in FIG. 33 captures a transition point where the preamble signal transitions from “positive to negative” and “negative to positive”, and draws the phases of the clock signals CK1 to CK6 into the phase of the preamble signal based on this transition point. It is configured as follows.
[0323]
Therefore, the TR-PLL 124 requires sampling points before and after the transition point. Therefore, as shown in FIG. 42, the voltage at the required sampling point, that is, the voltage RefL is set as the first reference voltage, and the voltage -RefL is set as the second reference voltage. Thereby, even when the main ADC 141 and the auxiliary ADCs 142a and 142b are operated alternately, the TR-PLL 124 inputs a voltage value at the same point as the sampling point based on the required reference clock signal SCK. Thereby, the TR-PLL 124 can perform phase pull-in as in the case of sampling with the reference clock signal SCK.
[0324]
In general, when the sampling frequency is lowered (the cycle is lengthened), the number of transition points decreases, and the phase comparison gain in the TR-PLL decreases. This makes it difficult to pull in the phase and lengthens the time required for phase pull-in to match the phase of the reference clock signal SCK with the phase of the preamble signal.
[0325]
On the other hand, in the present embodiment, the auxiliary ADCs 142a and 142b are provided, and the main ADC 141 and the auxiliary ADCs 142a and 142b are operated alternately, thereby suppressing a decrease in the phase comparison gain in the TR-PLL 124. This prevents an increase in the time required for phase pull-in.
[0326]
In the ADC 122 configured as described above, the main ADC 141 operates with a clock signal CKa having a frequency (1/2) slower than the reference clock signal SCK. Therefore, power consumption is higher than when operating with the reference clock signal SCK. Is about half. Since the auxiliary ADCs 142 a and 142 b have a smaller number of bits of the output signal than the main ADC 141, the circuit scale is smaller than that of the main ADC 141 and operates with the inverted clock signal XCKa having the same frequency as the main ADC. Thereby, the total power consumption of each auxiliary ADC 142a, 142b is less than the power consumption of the main ADC 141. Therefore, the power consumption of the ADC 122 is reduced as compared with the case where the main ADC 141 is operated by the reference clock signal SCK.
[0327]
The auxiliary ADCs 142a and 142b have a sufficiently small circuit scale because the number of bits of the output signal is smaller than that of the main ADC 141. Thereby, an increase in the chip area of the semiconductor device forming the ADC 122 can be suppressed.
[0328]
As described above, according to the present embodiment, the following effects can be obtained.
(1) The zero phase restart circuit 123 obtains a cross-correlation function value from a reference signal having a late phase and a reference signal having a fast phase with respect to the output signal S26 of the AD converter 122, and the phase difference is calculated based on the value. I asked for it. As a result, the time required to obtain the phase difference is shortened, and synchronization can be established earlier to speed up the read operation.
[0329]
(2) The ADC 122 is constituted by the main ADC 141 and the plurality of auxiliary ADCs 142a and 142b, and the main ADC 141 and the auxiliary ADCADCs 142a and 142b are alternately operated by the clock signals CKa and XCKa obtained by dividing the reference clock signal SCK. As a result, power consumption in the ADC 122 can be reduced.
[0330]
(3) By reducing the input range of the auxiliary ADCs 142a and 142b, the area of the auxiliary ADCs 142a and 142b can be made smaller than that of the main ADC 141. As a result, an increase in the chip area of the semiconductor device forming the ADC 122 can be suppressed.
[0331]
In the above embodiment, the following modifications may be made.
In place of the selection circuit 128 of the restart circuit 123 of the present embodiment, the clock switching circuit 115 and the VCO 116 of the seventh embodiment may be provided. In that case, the TR-PLL 104 of the seventh embodiment is used instead of the TR-PLL 124.
[0332]
(Ninth embodiment)
The ninth embodiment embodying the present invention will be described below with reference to FIGS. For the sake of convenience of explanation, the same components as those in the prior art of FIG.
[0333]
FIG. 44 shows a block circuit diagram of the decision feedback equalizer (DFE) 151 of the present embodiment. The DFE 151 includes a prefilter 12, an adder 13, a determiner 14, a shift register 15, a feedback filter (FB filter) 152, an abnormality detection circuit 153, a selection circuit 154, a transition detection circuit 155, and an approximation circuit 156.
[0334]
The output signal of the VGA 47 in FIG. 2 is input to the prefilter 12 of the DFE 151 as a signal S41. The DFE 151 operates to output a reproduction signal from which the intersymbol interference of the input signal S41 is removed.
[0335]
  The abnormality detection circuit 153 has a function of detecting whether the input signal S41 of the DFE 151 is normal or abnormal. Further, the abnormality detection circuit 153 has a thermal asperity (TA): read signal RD.AbnormalHas a function of detecting a phenomenon) The abnormality detection circuit 153 outputs an L level detection signal S42 when the input signal S41 is normal. When detecting an abnormality in the input signal, the abnormality detection circuit 153 outputs a detection signal S42 of a predetermined level (H level) to the selection circuit 154.
[0336]
To describe the abnormality detection method in detail, the level of the input signal S41 changes corresponding to the transmission code rule (RLL (1, 7) code) used for encoding by the encoder 44 of FIG. That is, the input signal S41 that is above a certain level (or below a certain level) continues for a predetermined period that applies to the transmission code rule. Therefore, when an input signal S41 of a certain level or more (below a certain level) is input over a predetermined period, the input signal S41 within the predetermined period includes an error.
[0337]
Therefore, the abnormality detection circuit 153 measures a period during which the input signal S41 of a certain level or more (a certain level or less) is input. When the level of the input signal S41 changes from a certain level or more to a certain level or less (or from a certain level or less to a certain level or more) without the predetermined period, the abnormality detection circuit 153 detects that the input signal is normal. Then, the abnormality detection circuit 153 outputs an L level detection signal S42 based on the detection result.
[0338]
On the other hand, when an input signal S41 of a certain level or more (below a certain level) is input beyond the predetermined period, the abnormality detection circuit 153 detects that the input signal S41 is abnormal. Then, the abnormality detection circuit 153 outputs an H level detection signal S42 based on the detection result.
[0339]
The abnormality detection circuit 153 outputs an H level detection signal S42 when the input signal S41 is normal and an L level detection signal S42 when the input signal S41 is abnormal based on the detection result. It may be configured.
[0340]
The detection signal S42 output from the abnormality detection circuit 153 is input to the selection circuit 154. The selection circuit 154 receives the external detection signal S43 and the selection signal S44. The external detection signal S43 is generated by an abnormality detection circuit (not shown) outside the DFE 151. The abnormality detection circuit is similar to the abnormality detection circuit 153.
2 detects whether the input signal S41 of the DFE 151, that is, the output signal of the VGA 47 in FIG. 2 is normal or abnormal, and outputs an external detection signal S43 to the DFE 151 based on the detection result.
[0341]
The selection signal S44 is input from the HDC 39 in FIG. The HDC 39 outputs a selection signal S44 to the selection circuit 154 based on the setting of the hard disk device. The selection circuit 154 selects either the detection signal S42 or the external detection signal S43 based on the input selection signal S44. Then, the selection circuit 154 outputs the selected signal to the FB filter 152 as the hold signal S45.
[0342]
The external detection signal S43 may not be input. In that case, the selection circuit 154 may be omitted, and the abnormality detection circuit 153 may output the detection result to the FB filter 152 as the hold signal S45.
[0343]
The FB filter 152 is input with a multi-bit signal stored in the shift register 15. The FB filter 152 calculates the feedback amount based on the data input from the shift register 15 while the hold signal S45 is at the L level. Then, the FB filter 152 outputs a signal S46 of a feedback amount (level of voltage value, current amount, etc.) according to the calculation result to the adder 13.
[0344]
The FB filter 152 outputs a constant feedback amount, that is, a predetermined level signal S46 to the adder 13 in response to the H level hold signal S45. The level of the signal S46 at this time is set in advance to, for example, an average value of feedback amounts calculated based on data stored in the shift register 15 when the input signal S41 is normal. This average value is a value smaller (or larger than the minimum value) than the maximum value of the output signal of the FB filter 152. Therefore, the feedback loop (FB loop) feeds back a constant feedback amount (feedback (FB) response) instead of the feedback amount calculated based on the abnormal signal when the input signal S41 is abnormal.
[0345]
The transition detection circuit 155 receives the hold signal S45 and the determination signal S4 output from the determiner 14. The transition detection circuit 155 detects a specific transition point after the H level hold signal S45 is input, and outputs a second detection signal S47 to the approximation circuit 156.
[0346]
Specifically, the transition detection circuit 155 detects a specific transition point at which data transitions such that the determination signal S4 is “0 → 1” or “1 → 0”. 2 detection signal 47 is output to approximation circuit 156. The pulse width of the second detection signal 47 corresponds to the time (number of clocks) required until the normal determination signal S4 output from the determiner 14 is stored in the last register constituting the shift register 15. ing.
[0347]
The approximation circuit 156 includes a register 157 having a plurality of storage areas. A determination signal S4 output from the determination unit 14 is input to the approximation circuit 156.
The approximating circuit 156 sequentially stores the determination signal S4 in the register 157 in response to the second detection signal S47 at the H level. The approximate circuit 156 calculates an approximate feedback amount based on the data stored in the register 157. Then, the approximating circuit 156 outputs the calculated approximate feedback amount signal S48 to the FB filter 152.
[0348]
The detection signal S47 is input to the FB filter 152. The FB filter 152 outputs the output signal S48 of the approximation circuit 156 to the adder 13 based on the second detection signal S47 at the H level. Accordingly, the feedback signal S46 corresponding to the approximate feedback amount calculated by the approximate circuit 156 is fed back to the adder 13 while the second detection signal S47 is at the H level.
[0349]
The FB filter 152 outputs, to the adder 13, a feedback signal S46 having a feedback amount calculated based on the data input from the shift register 15 based on the second detection signal S47 at the L level.
[0350]
Next, the operation of the DFE 151 configured as described above will be described with reference to FIG.
When the input signal S41 becomes abnormal, the abnormality detection circuit 153 detects the abnormality signal and outputs an H level first detection signal S42, and the selection circuit 154 holds the first detection signal S42 as a hold signal based on the selection signal S44. It outputs to FB filter 152 as S45. The FB filter 152 feeds back a fixed feedback amount based on the hold signal S45.
[0351]
At this time, the feedback amount input to the adder 13 is smaller than the feedback amount based on the abnormal signal. Accordingly, the output signal of the adder 13 is closer to the output signal S46 when the feedback amount based on the normal input signal S41 is fed back than when the feedback amount based on the abnormal signal is fed back.
[0352]
As a result, the FB loop is less likely to diverge compared to the case where an FB response based on an abnormal signal is fed back. That is, the DFE 151 of this embodiment suppresses the divergence of the FB loop due to the abnormality of the input signal S41.
[0353]
Also, feeding back a constant feedback amount shortens the time until the FB loop operates normally by the FB response calculated based on the normal input signal when the input signal S41 becomes normal. . That is, when the feedback amount is calculated based on the abnormal signal, the FB response becomes the maximum value (or minimum value) of the output signal of the FB filter 152. The maximum (or minimum) FB response affects the output signal S46, which is the calculation result of the FB filter 152 for a long time after the input signal S41 becomes normal. Due to this influence, the DFE 151 may not return to normal for a long time.
[0354]
However, the time during which the predetermined amount of FB response affects the output signal of the FB filter 152 is shorter than that of the maximum (or minimum) FB response. That is, the FB loop becomes a normal operation in a short time. As a result, the DFE 151 returns to normal in a short time.
[0355]
Next, when the input signal S41 becomes normal, the abnormality detection circuit 153 outputs an L level first detection signal S42. The transition detection circuit 155 detects a specific transition point of the determination signal S4 output from the determination unit 14 based on the normal input signal S41, and uses the second detection signal S47 having a predetermined pulse width as the approximation circuit 156 and the FB filter 152. Output to. The approximating circuit 156 sequentially stores the determination signal S4 output from the determiner 14 in the register 157. Then, the approximate circuit 156 calculates an approximate feedback amount based on the data of a plurality of bits stored in the register 157, and outputs the approximate feedback amount signal S48 to the FB filter 152.
[0356]
Therefore, the approximate feedback amount is fed back to the FB loop. The value of the feedback signal at this time is an approximate value based on the normal determination signal S4. Therefore, the FB response at this time is closer to the normal feedback amount than the FB response (a constant feedback amount) when the abnormal signal is input. As a result, the FB loop returns to normal in a shorter time than when a fixed amount is returned.
[0357]
As described above, according to the present embodiment, the following effects can be obtained.
(1) An abnormality abnormality detection circuit 153 that detects abnormality of the input signal of the pre-filter 12 is provided, and feedback of the feedback filter is stopped based on the detection result. As a result, the determination result based on the abnormal signal is not fed back and divergence can be prevented.
[0358]
(2) The approximate circuit 156 calculates the approximate value of the feedback amount, and the FB filter 152 outputs the feedback signal of the approximate feedback amount. As a result, the FB loop can be returned to normal in a shorter time than when a fixed amount is returned.
[0359]
(Tenth embodiment)
Hereinafter, a tenth embodiment embodying the present invention will be described with reference to FIGS. For convenience of explanation, the same components as those in the first and ninth embodiments are denoted by the same reference numerals, and some of the drawings and explanation are omitted.
[0360]
FIG. 46 is a partial block circuit diagram of the signal processing circuit of this embodiment.
The signal processing circuit includes an error calculation circuit 158. The error calculation circuit 158 calculates an error between the input signal S3 and the output signal S4 of the determiner 14, and outputs the calculation result as an output signal to the AGC circuit 47a and the TR-PLL 49. The AGC circuit 47 a outputs a control signal based on the output signal of the error calculation circuit 158 to the VGA 47. The VGA 47 amplifies the read signal RD with a gain based on the control signal, and outputs the amplified signal as a signal S41. The TR-PLL 49 pulls in the phase of the reference clock signal SCK based on the output signal of the error calculation circuit 158.
[0361]
The signal processing circuit includes an abnormality detection circuit 153a. The output signal S41 of the VGA 47 is input to the abnormality detection circuit 153a. The abnormality detection circuit 153a has a function of detecting whether the input signal S41 is normal or abnormal. The abnormality detection circuit 153a has a function of detecting thermal asperity.
[0362]
As shown in FIG. 47, when the input signal S41 is abnormal based on the detection result, the abnormality detection circuit 153a sets a detection flag based on the detection of thermal asperity and the input signal S43. Then, the abnormality detection circuit 153a outputs the H level hold signals S45, AH, and PH to the feedback filter (FB filter) 152, the AGC circuit 47a, and the TR-PLL 49.
[0363]
The FB filter 152 stops the output of the feedback signal S46 based on the hold signal S45. This can prevent divergence of the feedback loop by stopping the feedback by controlling the feedback loop when the input signal is abnormal.
[0364]
The AGC circuit 47a stops outputting the control signal based on the H level hold signal AH. At this time, the AGC circuit 47a amplifies the read / read signal RD by setting the gain to a predetermined constant value. Thereby, the abnormality detection circuit 153a prevents the input signal S41 from being abnormal due to thermal asperity. That is, the abnormality detection circuit 153a can prevent divergence of the control loop formed by the VGA 47 and the AGC 47a.
[0365]
The TR-PLL 49 stops control based on the H level hold signal PH. That is, the TR-PLL 49 holds the frequency and phase of the reference clock signal SCK. As a result, the abnormality detection circuit 153a can prevent the PLL circuit 49 from diverging.
[0366]
Based on the first pulse detection at the time of recovery by the transition detection circuit 155 of FIG. 44, the L level output signal S47 is output after a predetermined period. Thereby, a feedback response based on the normal signal S41 is calculated, and the response is fed back. The abnormality detection circuit 153a outputs the L level hold signals AH and PH after a predetermined period from the falling edge of the signal S47. The AGC circuit 47a outputs a control signal based on the L level hold signal AH. The TR-PLL 49 controls the reference clock signal SCK based on the L level hold signal PH.
[0367]
In the above embodiment, the following modifications may be made.
In the ninth embodiment, the DFE 151 includes the abnormality detection circuit 153. However, the DFE 151 may not include the abnormality detection circuit 153 as in the tenth embodiment. In that case, a configuration in which the abnormality detection circuit 153 is included in the signal processing circuit, or a configuration in which the abnormality detection circuit is provided independently in the hard disk device 31 of FIG.
[0368]
(Eleventh embodiment)
Hereinafter, an eleventh embodiment embodying the present invention will be described with reference to FIGS.
[0369]
For the sake of convenience of explanation, the same components as those in the first embodiment shown in FIG.
FIG. 48 is a partial block circuit diagram of the signal processing circuit of this embodiment. Other parts of the signal processing circuit not shown in FIG. 48 are the same as those in the first embodiment, so refer to FIG.
[0370]
The signal processing circuit 161 includes a controller 162. The controller 162 includes a register 163 and a timing control circuit 164.
In the register 163, detection data (eg, DDh) having a known value is stored from the MPU 37 of FIG. The controller 162 outputs the detection data stored in the register 163 to the encoder 165 and the feedback filter (FB filter) 167 of the decision feedback equalizer (DFE) 166.
[0371]
A predetermined timing value is stored in the timing control circuit 164 from the MPU 37 or the like. The timing control circuit 164 receives a clock signal SCK for taking a read / write timing with respect to the magnetic disk 33 of FIG.
[0372]
Based on the clock signal SCK, the timing control circuit 164 outputs an interrupt signal S51 to the encoder 165 and the FB filter 167 at regular intervals based on the timing value.
[0373]
The controller 162 has a function of controlling the encoder 165 at the time of data writing for writing data to the magnetic disk 33 in FIG. The controller 162 has a function of controlling a decision feedback equalizer (DFE) 166 at the time of data reading for reading information from the magnetic disk 33. These functions will be described in correspondence with data write and data read.
[0374]
[When writing data]
The controller 162 has a function of detecting the output timing of a sync byte indicating the start of data from the encoder 165. The controller 162 operates the timing control circuit 164 in response to the sync byte output timing detection. Thus, after the sync byte is output from the encoder 165, the timing control circuit 164 outputs an interrupt signal S51 to the encoder 165 at regular intervals based on the timing value.
[0375]
In response to an interrupt signal S51 input at regular intervals, the encoder 165 temporarily stops outputting data and outputs detection data input from the register 163. Thereby, as shown in FIG. 49A, the controller 162 performs an interrupt process for interrupting the detection data stored in the register 163 for each predetermined number of bits of data.
[0376]
[When reading data]
A sync byte detection signal SB is input to the controller 162 from the control data detection circuit 53 of FIG. The controller 162 operates the timing control circuit 164 in response to the sync byte detection signal SB. The MPU 37 shown in FIG. 1 detects the head of data based on the sync byte detection signal SB, and establishes synchronization for processing in synchronization with the data.
[0377]
As a result, as shown in FIG. 49B, the timing control circuit 164 outputs the interrupt signal S51 to the FB filter 167 at regular intervals based on the timing value after the sync byte is detected, that is, after synchronization is established. . Further, the controller 162 outputs the detection data stored in the register 163 to the FB filter 167 simultaneously with the interrupt signal S51.
[0378]
The FB filter 167 calculates a feedback amount based on the detection data input from the register 163 in response to the interrupt signal S51 input at regular intervals. Then, the FB filter 167 outputs the calculated feedback amount signal to the adder 13. Thereby, the controller 162 performs a preset operation for presetting the FB loop by the FB response based on the detection data stored in the register 163 at regular intervals.
[0379]
Detection data read from the magnetic disk 33 is input to the DFE 166 at the same timing as the interrupt signal S51. The FB filter 167 of the DFE 166 calculates a feedback response (FB response) of the feedback loop (FB loop) based on the detection data. Therefore, when an error occurs in the detected data or data read before that, the error is propagated and the feedback loop (FB loop) of the DFE 166 diverges.
[0380]
However, known detection data is input to the FB filter 167 from the controller 162 at the same timing as the interrupt signal S51. Since this detection data is input from the controller 162, it is not affected by the state of the magnetic disk 33 or the head device 34. That is, there is no error in the detection data input from the controller 162.
[0381]
Therefore, the FB filter 167 of the DFE 166 calculates an FB response based on this error-free detection data. This prevents error propagation for the next decision data. Thereby, the controller 162 prevents the FB loop of the DFE 166 from diverging.
[0382]
As described above, according to the present embodiment, the following effects can be obtained.
(1) The controller 162 writes known detection data to the FB filter 167 of the DFE 166 at every predetermined interval when data is read to preset the FB loop. As a result, divergence of the FB loop after synchronization is established can be prevented.
[0383]
(Twelfth embodiment)
Hereinafter, a twelfth embodiment embodying the present invention will be described with reference to FIGS.
[0384]
For the sake of convenience of explanation, the same components as those in the eleventh embodiment are denoted by the same reference numerals, and a part of the description is omitted.
FIG. 50 shows a partial block circuit diagram of the signal processing circuit of the present embodiment. The other parts of the signal processing circuit not shown in FIG. 50 are the same as those of the first embodiment as in the eleventh embodiment, so refer to FIG.
[0385]
The signal processing circuit 171 includes a controller 172. The controller 172 includes a timing control circuit 174 and a register 173.
A predetermined timing value is stored in the timing control circuit 174 from the MPU 37 or the like. The timing control circuit 174 receives a clock signal SCK for timing the read / write with respect to the magnetic disk 33 in FIG.
[0386]
Based on the clock signal SCK, the timing control circuit 174 outputs an interrupt signal S51 to the encoder 175 and the feedback filter (FB filter) 167 of the decision feedback equalizer 166 at regular intervals based on the timing value.
[0387]
The encoder 175 outputs data to be output at that time to the controller 172 in response to the interrupt signal S51. The register 173 has a capacity capable of storing a plurality of data. The controller 172 sequentially stores data input from the encoder 175 in the register 173. Further, the controller 172 outputs the detection data stored in the register 173 to the FB filter 167.
[0388]
The controller 172 has a function of controlling the encoder 175 during data writing to write data to the magnetic disk 33 in FIG. The controller 172 has a function of controlling a decision feedback equalizer (DFE) 166 at the time of data reading for reading information from the magnetic disk 33. These functions will be described in correspondence with data write and data read.
[0389]
[When writing data]
The controller 172 has a function of detecting the output timing of a sync byte indicating the start of data from the encoder 175. The controller 172 operates the timing control circuit 174 in response to the sync byte output timing detection. Thus, after the sync byte is output from the encoder 175, the timing control circuit 174 outputs the interrupt signal S51 to the encoder 175 at regular intervals based on the timing value.
[0390]
The encoder 175 responds to the interrupt signal S51 input at regular intervals, and also outputs data for writing output at that time to the controller 172. As a result, as shown in FIG. 51A, the controller 172 performs an interrupt process for sequentially storing data output at a predetermined timing in the register 173.
[0390]
[When reading data]
A sync byte detection signal SB is input to the controller 172 from the control data detection circuit 53 of FIG. The controller 172 operates the timing control circuit 174 in response to the sync byte detection signal SB. As a result, as shown in FIG. 51B, the timing control circuit 174 outputs the interrupt signal S51 to the FB filter 167 at regular intervals based on the timing value after the sync byte is detected. In addition, the controller 172 sequentially outputs the data stored in the register 173 to the FB filter 167 as detection data.
[0392]
The FB filter 167 calculates a feedback amount based on detection data sequentially input from the register 173 in response to the interrupt signal S51 input at regular intervals. Then, the FB filter 167 outputs the calculated feedback amount signal to the adder 13. Accordingly, the controller 172 performs a preset operation for presetting the FB loop by the FB response based on the detection data stored in the register 173 at regular intervals.
[0393]
Detection data read from the magnetic disk 33 is input to the DFE 166 at the same timing as the interrupt signal S51. The FB filter 167 of the DFE 166 calculates a feedback response (FB response) of the feedback loop (FB loop) based on the detection data. Therefore, when an error occurs in the detected data or data read before that, the error is propagated and the feedback loop (FB loop) of the DFE 166 diverges.
[0394]
However, known detection data is input from the controller 172 to the FB filter 167 at the same timing as the interrupt signal S51. Since this detection data is input from the controller 172, it is not affected by the state of the magnetic disk 33 or the head device 34 in FIG. That is, there is no error in the detection data input from the controller 172.
[0395]
Therefore, the FB filter 167 of the DFE 166 calculates an FB response based on this error-free detection data. This prevents error propagation for the next decision data. Thereby, the controller 172 prevents the divergence of the FB loop of the DFE 166.
[0396]
This embodiment is particularly effective when a write / read test for the magnetic disk 33 is performed. That is, when general data is written to the magnetic disk 33, the data is an arbitrary value. Therefore, a huge amount of registers are required to store data to be written in all sectors of the magnetic disk 33 at a predetermined timing. This increases the scale (chip size) of the signal processing circuit 171.
[0397]
However, the write / read test is to check whether data written to the magnetic disk 33 is normally read. Therefore, a write operation and a read operation are performed on one or a plurality of (about 2 to 10) sectors. Therefore, the amount of data stored in the register 173 is small. Thereby, the scale of the signal processing circuit does not increase without requiring the register 173 having a large capacity.
[0398]
As described above, according to the present embodiment, the following effects can be obtained.
(1) The same effect as the eleventh embodiment is achieved.
(2) Furthermore, in this embodiment, data to be written to the magnetic disk 33 is stored in the register 173. Based on the data stored in the register 173, the DEF166 FB loop is preset at the time of data reading. Therefore, the process of storing the detection data in advance in the register 173 is unnecessary, and accordingly, the process of the HDC 39 in FIG. 1 is simplified, and the terminal for writing the detection data is unnecessary, so that the signal processing circuit 171 is used. The chip size can be reduced and the circuit configuration can be simplified.
[0399]
(Thirteenth embodiment)
Hereinafter, a thirteenth embodiment embodying the present invention will be described with reference to FIG.
For the sake of convenience of explanation, the same components as those of the conventional example of FIG.
[0400]
FIG. 52 shows a block diagram of a decision feedback equalizer (DFE) of this embodiment.
The DFE 181 includes a prefilter 12, an adder 13, a determiner 14, a shift register 15, a feedback filter (hereinafter referred to as FB filter) 182, and a feedback response rewriting circuit 183. The FB filter 182 includes an address conversion decoder 184, a memory (RAM) 185, and a DAC 186.
[0401]
The prefilter 12 receives the output signal of the VGA 47 of FIG. The pre-filter 12 filters the input signal and generates a signal having a waveform that maximizes the S / N ratio. Thereby, the pre-filter 12 outputs the filtered signal to the adder 13. The adder 13 adds and calculates the output signal of the prefilter 12 and the output signal of the FB filter 182, and outputs the calculated signal to the determiner 14.
[0402]
The determiner 14 compares the output voltage of the adder 13 with a preset reference voltage, and outputs a determination signal S1 of “1” or “0” to the shift register 15 based on the comparison result. As a result, the determiner 14 converts the output signal of the adder 13 into a digital signal.
[0403]
The shift register 15 includes a number of registers 15a (eight in FIG. 52) corresponding to the number of taps of the FB filter 182. The shift register 15 samples the determination signal output from the determination unit 14 in synchronization with the clock signal, and sequentially stores the sampling data in each register 15a. Thereby, the shift register 15 stores the sampled past data. The shift register 15 outputs the stored past data to the FB filter 182.
[0404]
The FB filter 182 includes an address conversion decoder 184, a memory (RAM) 185, and a digital-analog converter (DAC) 186. The conversion decoder 184 decodes the data input from the shift register 15 and outputs the result to the RAM 185 as the read address RAD.
[0405]
Since the RAM 185 has the same configuration as the conventional example shown in FIG. 54, the configuration will be described in detail with reference to FIG. That is, the RAM 185 has a plurality of areas, and a feedback response corresponding to the 8-bit data pattern output from the shift register 15 is stored in each area. These feedback responses are calculation results obtained by previously calculating data stored in the shift register 15 and predetermined filter coefficients ω7 to ω0.
[0406]
The RAM 185 selects one area based on the read address RAD. The RAM 185 outputs the data read from the selected area to the DAC 186. The DAC 186 converts the data input from the RAM 185 into an analog signal, and outputs the analog signal to the adder 13 as a feedback response. Therefore, the adder 13, the determiner 14, the shift register 15, the conversion decoder 184, the RAM 185, and the DAC 186 constitute a feedback loop (FB loop).
[0407]
The rewrite circuit 183 includes a coefficient register 187, a programmable filter arithmetic unit (hereinafter referred to as arithmetic unit) 188, an external interface circuit (hereinafter referred to as I / F circuit) 189, and an input pattern generation state machine (hereinafter referred to as state machine) 190. including.
[0408]
The coefficient register 187 is a readable / rewritable memory, and is composed of, for example, a DRAM. The coefficient register 187 may be configured by SRAM, EEPOM, or the like. The coefficient register 187 has a plurality of areas 187a. Each region 187a stores filter coefficients ω0, ω1, ω2,. Each filter coefficient ω0, ω1, ω2,... Is rewritten by the MPU 37 in FIG. Based on the servo information read from the magnetic disk 33 in FIG. 2, the MPU 37 calculates filter coefficients ω0, ω1, ω2,. Store in the coefficient register 187.
[0409]
Each filter coefficient ω 0, ω 1, ω 2,... Is read by the arithmetic unit 188. Information about a zone to be read from the MPU 37 in FIG. 2 is input to the arithmetic unit 188 via the I / F circuit 189. The zone information includes zone position information and characteristics (transmission path characteristics) of a read signal RD obtained by reading data from a sector included in the zone.
[0410]
Further, the state signal S 61 is input from the state machine 190 to the arithmetic unit 188. The state machine 190 outputs a state signal S61 having a value corresponding to the pattern of data stored in the shift register 15 to the arithmetic unit 188.
[0411]
The shift register 15 has eight registers 15 a and outputs the data stored in each register 15 a to the FB filter 182. Accordingly, the state machine 190 sequentially outputs the state signal S61 from “00000000” (all 0) to “11111111” (all 1) to the arithmetic unit 188.
[0412]
The arithmetic unit 188 is configured to execute a rewriting process based on a preset sequence. A start trigger signal S62 is input to the arithmetic unit 188 via the I / F circuit 189 from the MPU 37 in FIG.
[0413]
The MPU 37 stores the filter coefficients ω 0, ω 1, ω 2,... Corresponding to the zone where the head device 34 of FIG. 2 is located in the coefficient register 187 via the I / F circuit 189 at that time. Thereafter, the MPU 37 outputs the start trigger signal S62 and the zone information to the arithmetic unit 188 via the I / F circuit 189.
[0414]
In response to the start trigger signal S62, the arithmetic unit 188 executes rewrite processing for rewriting the filter response of the RAM 185 in accordance with a predetermined sequence.
[0415]
Next, the rewriting process will be described in detail according to the sequence.
First, the arithmetic unit 188 outputs a start signal S63 to the state machine 190. Further, the arithmetic unit 188 reads the filter coefficients ω 0, ω 1, ω 2,... From the coefficient register 187.
[0416]
The state machine 190 generates all combinations of data stored in the shift register 15 in response to the start signal S63. The state machine 190 outputs the generated combination state signal S61 to the arithmetic unit 188 and the address translation decoder 184.
[0417]
Next, the arithmetic unit 188 calculates a filter response corresponding to the pattern of each state signal S61 based on each filter coefficient ω0, ω1, ω2,..., Zone information, and the state signal S61. The arithmetic unit 188 outputs the calculated filter response to the RAM 185.
[0418]
The address conversion decoder 184 decodes the state signal S61 input from the state machine 190 and outputs the result to the RAM 185 as the write address WAD. The RAM 185 stores the filter response output from the arithmetic unit 188 in an area selected based on the write address WAD.
[0419]
As described above, the rewrite circuit 183 rewrites the filter response of the RAM 185. The time required for the rewriting process is shorter than the time required for directly rewriting the contents (filter response) of the RAM 185 from the external MPU 37 (see FIG. 2).
[0420]
That is, when the contents of the RAM 185 are directly rewritten, the MPU 37 outputs the write address WAD corresponding to one area of the RAM 185 and the filter response to be rewritten. In order to rewrite the entire contents of the RAM 185, the MPU 37 repeats the output of the write address WAD and the filter response by the number of data stored in the RAM 185. The amount of data output by the MPU 37 at this time is much larger than the amount of output data (filter coefficient and start trigger signal S62) of the MPU 37 in the rewrite processing of this embodiment.
[0421]
However, this is processing for one zone. When the read operation extends over a plurality of zones, the MPU 37 needs to rewrite all the contents of the RAM 185 for each zone. Accordingly, when the contents of the RAM 185 are directly rewritten by the MPU 37, the output data amount of the MPU 37 becomes very large and the time required for data transfer becomes long. Furthermore, since the output data is a heavy load on the external interface including the bus 41 of FIG. 1, the data transfer rate is slow. These increase the time required for rewriting and prevent the reading process from being speeded up.
[0422]
On the other hand, in the present embodiment, the MPU 37 only writes the filter coefficient and outputs the start trigger signal S62, so that the time required for data transfer is shorter than that required for direct rewriting. Furthermore, if the amount of data is small, the load on the external interface is also reduced, so the data transfer rate does not slow down. As a result, the time required for rewriting is shorter than in the case of direct rewriting, and the reading process can be speeded up.
[0423]
As described above, according to the present embodiment, the following effects can be obtained.
(1) The rewrite circuit 183 rewrites the filter response of the RAM 185. The time required for the rewriting process is shorter than the time required for directly rewriting the contents (filter response) of the RAM 185 from the external MPU 37. As a result, the data transfer time in each zone can be shortened to shorten the read time.
[0424]
【The invention's effect】
  As detailed above, according to the invention described in claim 1,Based on the monitoring result of the monitoring circuit that monitors the contents of the shift register, one of a plurality of signal levels generated by the first signal level generation circuit is selected and output to the determiner as a reference level. One of a plurality of signal levels generated by the two-signal level generation circuit and a feedback amount based on the determination result is selected, and the selected signal is converted into an analog signal and output as a feedback signal.Therefore, the sticking is eliminated and the divergence of the feedback filter can be stopped.
[0427]
  Claim2,3According to the invention described in (4), the register length of the shift register is made not to depend on the number of taps of the feedback filter, but to correspond to the sign rule of the input signal, so that the increase in the configuration of the feedback filter is suppressed and divergence is prevented. be able to.
[0428]
  Claim4According to the invention described in (3), the determination error existing locally in the shift register is corrected based on the code rule, and divergence can be prevented.
[Brief description of the drawings]
FIG. 1 is a schematic configuration diagram of a hard disk device.
FIG. 2 is a block circuit diagram of a signal processing circuit.
FIG. 3 is a block circuit diagram of the DFE of the first embodiment.
FIG. 4 is a timing chart for explaining the operation of DFE.
FIG. 5 is a state transition diagram for explaining the operation of DFE.
FIG. 6 is a timing chart for explaining the operation of DFE.
FIG. 7 is a state transition diagram for explaining the operation of the DFE.
FIG. 8 is a timing chart for explaining the operation of DFE.
FIG. 9 is a state transition diagram for explaining the operation of the DFE.
FIG. 10 is a timing chart for explaining the operation of DFE.
FIG. 11 is a block circuit diagram of a DFE according to a second embodiment.
FIG. 12 is a block circuit diagram of a DFE according to a third embodiment.
FIG. 13 is a state transition diagram of a state machine.
FIG. 14 is a circuit diagram of a decoder.
FIG. 15 is an explanatory diagram of the operation of the error detection circuit.
FIG. 16 is an explanatory diagram of the operation of the error detection circuit.
FIG. 17 is an explanatory diagram of the operation of the error detection circuit.
FIG. 18 is an explanatory diagram of the operation of the error detection circuit.
FIG. 19 is a timing chart for explaining the operation of DFE;
FIG. 20 is a timing chart for explaining the operation of the DFE.
FIG. 21 is a partial block circuit diagram of a signal processing circuit according to a fourth embodiment.
FIG. 22 is an explanatory diagram showing read signal data.
FIG. 23 is a partial block circuit diagram of a signal processing circuit according to a fifth embodiment.
FIG. 24 is a partial block circuit diagram of a signal processing circuit according to a sixth embodiment.
FIG. 25 is a partial block circuit diagram of another signal processing circuit.
FIG. 26 is a partial block circuit diagram of another signal processing circuit.
FIG. 27 is a partial block circuit diagram of a signal processing circuit according to a seventh embodiment.
FIG. 28 is a block circuit diagram of a zero phase restart circuit.
FIG. 29 is a waveform diagram showing clock signals having different phases.
FIG. 30 is a waveform diagram showing the operation of the zero phase restart circuit.
FIG. 31 is a timing chart for explaining an operation with respect to a read signal;
FIG. 32 is a timing chart for explaining an operation for a read signal;
FIG. 33 is a partial block circuit diagram of a signal processing circuit according to an eighth embodiment.
FIG. 34 is a block circuit diagram of a zero phase restart circuit.
FIG. 35 is a characteristic diagram showing a correlation function value with respect to a phase shift of a clock signal.
FIG. 36 is an explanatory diagram showing the operation of the adder with respect to the control signal.
FIG. 37 is an explanatory diagram showing a comparison level for a phase.
FIG. 38 is an explanatory diagram showing the operation of the comparator with respect to phase and comparison level.
FIG. 39 is a waveform diagram showing the operation of the zero phase restart circuit.
FIG. 40 is a block circuit diagram of DFE and ADC.
FIG. 41 is a waveform diagram of a clock signal.
FIG. 42 is a waveform diagram showing the operation of the ADC.
FIG. 43 is an explanatory diagram showing an operation range of the main ADC and the sub ADC.
FIG. 44 is a block circuit diagram of a DFE according to a ninth embodiment.
45 is a waveform diagram showing the operation of the DFE in FIG. 44. FIG.
FIG. 46 is a block circuit diagram of the DFE of the tenth embodiment.
47 is a waveform chart showing the operation of the DFE in FIG. 46. FIG.
FIG. 48 is a partial block circuit diagram of the signal processing circuit according to the eleventh embodiment.
49 (a) and 49 (b) are waveform diagrams showing the operation of the timing control circuit.
FIG. 50 is a partial block circuit diagram of a signal processing circuit according to a twelfth embodiment.
51 (a) and 51 (b) are waveform diagrams showing the operation of the timing control circuit.
FIG. 52 is a block circuit diagram of a DFE according to the thirteenth embodiment.
FIG. 53 is a block circuit diagram of a conventional DFE.
FIG. 54 is a block circuit diagram of a conventional DFE.
[Explanation of symbols]
12 Prefilter
13 Adder
14 Judgment device
48, 70 decision feedback equalizer
61 Shift register
65, 71 Feedback filter
67,73 Divergence monitoring circuit
68 selection circuit
69 Signal level generation circuit
84 TR-PLL as a PLL circuit
85 Digital arithmetic circuit
103,123 Zero phase restart circuit
162,172 Controller
183 Rewriting circuit
Ref Reference voltage
Ref1 to Ref3 First to third reference voltages as signal levels
Off1 to Off3 First to third offset voltages as signal levels
SEL Selection signal as monitoring result

Claims (4)

A prefilter that filters and outputs an input signal, an output signal of the prefilter and a feedback signal based on a determination result stored in a shift register are added, and a signal after the addition is determined according to a determination criterion, In a decision feedback equalizer including a decision circuit that sequentially stores decision results in the shift register,
  The determination circuit determines an adder that adds the output signal of the prefilter and the feedback signal, a magnitude of the output signal of the adder with respect to a reference level, and outputs the determination result to the shift register And a feedback filter that calculates a feedback amount based on a determination result stored in the shift register and outputs a feedback signal corresponding to the feedback amount,
  The feedback filter is
  A monitoring circuit for monitoring the contents of the shift register;
  A first signal level generation circuit for generating a plurality of signal levels;
  A first selection circuit that receives the monitoring result, selects one of the signal levels based on the monitoring result, and outputs the selected signal level as a reference level to the determination unit;
  A second signal level generation circuit for generating a plurality of signal levels;
  A second selection circuit that receives the monitoring result, selects one of the plurality of signal levels and the feedback amount based on the determination result based on the monitoring result, and outputs the selected signal;
  A DA converter that converts an output signal of the selection circuit into an analog signal and outputs the analog signal as the feedback signal;
A decision feedback equalizer. The decision feedback equalizer according to claim 1,
  A decision feedback equalizer in which the register length of the shift register is made to correspond to the sign rule of the input signal. In the decision feedback equalizer according to claim 1 or 2,
  The shift register is a decision feedback equalizer configured of a first register unit including a number of registers corresponding to the number of taps of the feedback filter and a second register unit including a plurality of registers. The decision feedback equalizer according to claim 1,
  The monitoring circuit is a decision feedback type equalizer configured to output a feedback signal based on an error when a decision error based on the decision criterion exists locally in the shift register.

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