JP3984109B2 - Manufacturing method of semiconductor device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an interlayer film QC (Quality Control) method, an interlayer film screening method, and a manufacturing method thereof for a semiconductor nonvolatile memory, in particular, a nonvolatile semiconductor memory device in which a memory cell has a two-layer gate structure including a floating gate and a control gate. .
[0002]
[Prior art]
In the nonvolatile semiconductor memory having the two-layer gate structure shown in the cross-sectional view of FIG. 11, the amount of charge accumulated in the floating gate electrode 4 is controlled by injecting / emitting electrons through the tunnel film 2. Yes. If for some reason electrons escape from the floating gate electrode 4 and the threshold voltage distribution deviates from the specified range, the product is determined to be defective. This failure is called retention failure. The path through which electrons escape is either the tunnel film 2 or the interlayer film 5 deposited between the floating gate electrode 4 and the control gate electrode 6. The retention failure is roughly classified into an initial failure and a failure that occurs after the rewrite operation.
Conventionally, the initial failure is inspected by forming a simple capacitor capable of evaluating the tunnel film and the interlayer film separately at different locations on the same wafer on which the product chip is manufactured, for example, a scribe region, as shown in FIG. At the time when the capacitor is formed or when all the process steps are completed, the withstand voltage test has been performed on the tunnel film and the interlayer film individually. If the breakdown voltage test shows that the breakdown voltages Vgref1 and Vgref2 are higher than the reference, the subsequent process (chip cutting, resin sealing, screening) is performed and the product is shipped. The measurement is performed at one or more locations, and when not measuring all locations, for example, measurement is performed at a plurality of points (A, B, C, D, and E in FIG. 12) that are not adjacent to each other. There are no restrictions on the number of measurement points.
FIG. 13 shows a flowchart of the QC method (Quality Control Method) relating to the above-described conventional tunnel film and interlayer film. A wafer that passed this initial defect inspection was cut into chips and enclosed in a package. FIG. 14 schematically shows a test result of charge retention characteristics using the product chip manufactured in this way. In this test, a rewrite stress equivalent to the actual operation is applied to the packaged product chip, electrons are once emitted from the floating gate electrode, and then electrons from the substrate are again applied to the floating gate electrode so as to reach a certain threshold voltage. After the injection, the phenomenon in which electrons escape from the floating gate electrode is observed. Moreover, in order to accelerate this phenomenon, it may be left in a high temperature state. In the case of a normal chip, the threshold voltage Vth distribution of each memory cell is measured at the position indicated by the broken line as a whole when the threshold voltage Vth distribution is again measured after writing as shown by the solid line in FIG. Or change very little. However, since a large number of memory cells are arranged in an actual product, if a large amount of electrons escapes for some reason even in a very small part of the cell, the threshold voltage is lowered and a product failure is caused. A broken line on the lower side of FIG. 14 schematically shows a state in which a threshold voltage drop has occurred in some memory cells of the defective product after being left unattended. Such products are called spilled defects.
As a method for inspecting a drop defect, which is a defect that occurs after a rewrite operation of a nonvolatile semiconductor memory, there is a conventional method of determining by applying a write / erase cycle stress. However, this method is a destructive test, and a certain amount of stress is applied to non-defective products. In addition, it took time for the test, and there was a problem in terms of cost. As a method for improving this point, in the invention disclosed in Japanese Patent Application Laid-Open No. 9-35500, a write process for all the memory cells and a weak erase that makes the threshold voltage distribution of all the memory cells positive are performed. Disclosed is a method capable of non-destructive screening by measuring a threshold voltage distribution of all memory cells and determining a defect when a certain value exceeds a predetermined value in statistical processing of all distributions. is doing. In this method, stress is applied to the tunnel film to evaluate the quality of the tunnel film. In the invention disclosed in Japanese Patent Laid-Open No. 9-320299, after a rewrite test, a write or erase operation is performed, a threshold value Vth is measured, an electric field of ± 5 MV / cm or less is applied to the tunnel film, A screening method is disclosed in which a fluctuation amount of the value Vth exceeds a certain value is judged as defective. In both cases, the film quality of the tunnel film was evaluated.
[0003]
[Problems to be solved by the invention]
Conventionally, in the measurement using a capacitor, there is no quantitative guideline for connecting a decrease in breakdown voltage and the above-mentioned defective product spillage, and a retention test after rewriting the guaranteed number of times at the product level has not been performed. In addition, since the yield after cutting into a chip and enclosing the package affects the cost, the deterioration of the deterioration that cannot be detected by the initial failure has been a major obstacle to cost reduction. Therefore, the long-term reliability of the interlayer film can be easily and quickly achieved by inspecting one memory cell (single unit) or memory array formed in, for example, a scribe region other than the memory cell region without applying stress to the memory cell. Therefore, a method for selecting a product that has been secured is desired. A method of manufacturing a semiconductor device having a non-volatile semiconductor memory selected as good by the inspection process is required.
In particular, from the viewpoint of improving the writing speed in the nonvolatile semiconductor memory, scaling of the tunnel film (2 in Fig. 11) and interlayer film (5 in Fig. 11) or increasing the operating voltage is effective. It is important to anticipate the reliability problems that occur. Therefore, the inventors examined the case where the interlayer film was scaled and the operating voltage was increased. Assuming tunnel injection from the substrate, the relationship between the interlayer electric field strength E, the tunnel thickness and the interlayer thickness is shown in FIG. The memory gate length / gate width were constant, the voltage applied to the control gate electrode was constant (FIG. 16A), the memory neutral threshold voltage, and the memory threshold voltage were constant. For example, when the tunnel film thickness is 10 nm, if the interlayer film thickness is 15.5 nm, the interlayer film electric field is 6.3 MV / cm. However, if the interlayer film thickness is increased to 12.5 nm, the interlayer film electric field is 7.3 MV / cm. Increase to. This tendency is similar to the scaling of the interlayer film thickness even when the tunnel film thickness scaling is advanced. Therefore, it is understood that a guideline for the allowable interlayer film electric field is important from the viewpoint of reliability when the interlayer film thickness scaling is advanced. As for the voltage applied to the control gate electrode, FIG. 16B shows the result of examining the tunnel film of 8.5 nm as an example when the voltage is increased by +1 V in order to improve the operation speed, for example. It can be seen that the interlayer electric field increases by about 0.25 MV / cm at any interlayer thickness.
[0004]
FIG. 17 shows the results of examining the relationship between the interlayer electric field strength (absolute value), tunnel thickness, and interlayer thickness when electrons are emitted from the floating gate electrode to the substrate by a tunnel current. Preconditions were constant memory gate length / width, constant voltage applied to the control gate electrode (FIG. 17A), memory neutral threshold voltage, and memory threshold voltage after electron emission. The voltage applied to the control gate electrode was analyzed, for example, when it was lowered by 1 V and is shown in FIG. 17B. It can be seen that even when the threshold voltage is set to a constant value lower than the neutral threshold voltage, the scaling of the tunnel film and the interlayer film increases the interlayer film electric field strength during the operation of emitting electrons from the control gate electrode. From the above considerations, scaling of the tunnel film / interlayer film and increase in operating voltage tend to increase the electric field of the interlayer film, and it can be said that quality assurance of the interlayer film is an important issue in the future.
[0005]
[Means for Solving the Problems]
Therefore, a plurality of test memory cells are formed on the wafer by a process of forming a nonvolatile semiconductor memory device including a memory cell having a two-layer gate structure including a floating gate and a control gate on the semiconductor wafer, Continuous writing is performed by applying a pulse voltage or a DC voltage to the control gate electrode of the test memory cell for a first predetermined time, and the first memory threshold voltage Vth of the floating gate electrode after writing is measured. After the memory cell is left for a second predetermined time, the second memory threshold voltage Vth of the floating gate electrode is measured again to obtain a change amount from the measured value, and the change amount of the memory threshold voltage Vth is 0 or A lower limit value of a voltage region where the first memory threshold voltage Vth exists when approximating 0 is set, and the first memory threshold voltage Vth of the test memory cell is the voltage When reaching the band, a non-volatile semiconductor memory device on the appropriate wafer proposes a method for producing a non-defective determining semiconductor device.
In the above method, the case where writing is performed by injection from the substrate has been described as an example, but the same method can be applied to the case of a nonvolatile semiconductor memory in which erasing is performed by injection from the substrate. That is, a plurality of test memory cells are formed on a wafer by a process of forming a nonvolatile semiconductor memory device including a memory cell having a double-layer gate structure including a floating gate and a control gate on a semiconductor wafer, Continuous erasure is performed by applying pulse voltage or DC voltage to the control gate electrode of the test memory cell for a first predetermined time, and the first memory threshold voltage Vth of the floating gate electrode after erasure is measured. After the memory cell is left for a second predetermined time, the second memory threshold voltage Vth of the floating gate electrode is measured again to obtain a change amount from the measured value, and the change amount of the memory threshold voltage Vth is 0 or An upper limit value of a voltage region in which the first memory threshold voltage Vth exists when approximating 0 is determined, and the first memory threshold voltage Vth of the test memory cell is the voltage region. When it reaches the a method for producing a non-defective determining semiconductor device nonvolatile semiconductor memory device on that wafer.
[0006]
DETAILED DESCRIPTION OF THE INVENTION
First, a nonvolatile semiconductor memory to which the present invention is applied will be described. A cross-sectional view of a memory cell of the nonvolatile semiconductor memory is shown in FIG. An N-type diffusion layer 3 is formed on the P-type substrate 1 by implanting N-type impurities (As) ions, and a first insulating film (tunnel film) 2, a second insulating film (interlayer film) 5, and a floating gate A structure having an electrode 4 and a control gate electrode 6 is taken. The first insulating film is Si0 ₂ The second insulating film is made of Si by the oxide film formed by _Three N _Four And Si0 ₂ Polycrystalline polysilicon is used for the floating gate electrode layer 4 and the control gate electrode layer 6 which are composed of laminated films. Although not shown in the drawings, in order to alleviate the electric field concentration in the source / drain regions, there is a configuration having an LDD structure in which N− ions are implanted and a pocket structure in which P + ions are implanted. Manufacture of a wafer equipped with a nonvolatile memory is performed by sequentially performing a well formation process, a gate formation process, a source / drain formation process, a wiring process, and a protective film formation process. It differs from other memories such as SRAM and DRAM in that a tunnel film, a floating gate electrode, an interlayer film, and a control gate electrode are sequentially formed on the semiconductor substrate surface in the gate formation step. The wafer manufacturing process refers to the above process group.
FIG. 3 shows an equivalent circuit diagram of an AND type flash memory array configuration. In the AND type flash, as shown in the figure, the memory is connected in parallel between the bit line and the source line of the array. Accordingly, the low Vth bit in the array has a configuration that affects the Vth distribution variation of the product. At the time of writing, a positive high voltage is applied to the word line of the selected bit, and electrons are injected from the substrate. At the time of erasing, electrons are emitted by a negative voltage in units of word lines. In actual memory operation, both electron injection from the substrate and electron emission from the floating gate electrode are thus performed. In the electrical stress test for the purpose of the interlayer film QC, a positive high voltage is applied while the memory threshold voltage is high, or a negative high voltage is intentionally applied while the memory threshold voltage is low. Accelerate deterioration at. That is, in the former, the interlayer film is deteriorated by continuously injecting the substrate, and the memory cell Vth reaches a certain saturation value when the condition of (injection current from the substrate) = (interlayer film leakage) is reached. Even if the operation is continued, the memory cell Vth does not rise. In the latter case, the interlayer film deteriorates by continuously emitting electrons to the substrate, and when the condition of (emission current to the substrate) = (interlayer film leak) is reached, the memory cell Vth reaches a certain saturation value and pulses. Even if is applied, the memory cell Vth does not decrease. Here, as an example, let us consider a deterioration phenomenon in which injection from a substrate is a write operation for an AND type flash memory with 100,000 rewrite guarantees.
In a flash memory, for example, electrons are accumulated in a floating gate electrode by tunnel injection from a substrate. At this time, the threshold voltage of the memory increases as the amount of charge accumulated in the floating gate electrode increases. On the other hand, when a positive voltage is applied to the control electrode, the electric field applied to the interlayer film becomes stronger as the amount of charge in the floating gate electrode increases. Therefore, the interlayer leakage current cannot be ignored as the threshold voltage increases. When the tunnel current injected into the floating gate electrode through the tunnel film (IFTO in FIG. 19) and the component leaking to the control gate electrode through the interlayer film (IONON in FIG. 19) are balanced, The threshold reaches a certain saturation value. This is called saturation Vth. Since this saturation Vth reflects the magnitude of the interlayer film leak, it is possible to discuss the magnitude of the interlayer film leak by comparing the magnitude of the saturation Vth under a constant write (erase) condition. FIG. 18 shows the results of analyzing the interlayer film leakage current and the interlayer film electric field in order to examine the magnitude of the saturation Vth and the interlayer film leakage. This analysis utilizes the property that the tunnel current and the interlayer current become equal when saturation Vth is reached. From this study, when the saturation Vth is constant, it means that the larger the absolute value of the voltage applied to the control gate electrode is, the larger the interlayer leakage current is. When the applied voltage is constant, the higher the saturation Vth is, the higher the interlayer film is. It can be seen that this means less leakage current. Therefore, in actual evaluation, if the magnitude of the memory cell Vth after pulse application when the applied voltage is constant is compared, it can be considered that the magnitude of the interlayer film leakage is monitored. When the saturation Vth is higher than a certain value, it can be determined that no defect due to interlayer film leakage occurs.
[0007]
FIG. 1 shows memory write characteristics for explaining the interlayer film QC method of the present invention. When the substrate injection is an erasing operation, the same argument holds even if the writing is replaced with erasing. In an actual product, the write (erase) operation is performed in a few milliseconds or less. However, in order to examine how the interlayer leak affects the memory cell Vth, the pulse is continuously applied without performing the erase (write) operation. Is applied. The memory cell Vth at the midway point is plotted. At the beginning of the pulse application, the memory cell Vth rises with the elapsed time, and it is determined that there is no interlayer film leakage. Further, when the pulse application is continued, the plot characteristic A of FIG. 1 shows that the plot curve of the memory cell Vth of a certain memory cell changes from the rise to the horizontal state. When this horizontal state (state in which the rise of the memory cell Vth is no longer seen between adjacent plot points) is reached, it is determined that the condition of (injection current from the substrate) = (interlayer film leakage) has been reached. The memory cell Vth at this time is called saturation Vth. The leak generated in the interlayer film at this point is a result of the breakdown of the interlayer film, and does not recover thereafter. The write characteristics A shown in FIG. 1 are measurement results for a plurality of memory cells, all of which reach the saturation Vth and then finish the measurement, or the subsequent plot of the memory cell Vth falls below the saturation Vth, etc. Is seen. On the other hand, in the write characteristic B, the memory cell Vth continues to rise continuously during the pulse application for 100 seconds and approaches the horizontal state after exceeding 8 V, but is still completely horizontal. In this example, the saturation Vth is not reached. That is, the leak of the interlayer film does not occur to the extent that the detection accuracy of the measuring apparatus can be detected, and it can be considered that the interlayer film is not broken.
The upper limit of the pulse application time in FIG. 1 can be determined, for example, by (write time with write (erase) latest bit) × (rewrite guarantee count). In this case, if the write time of the latest bit is 1 ms, (1 ms) × (100000) = (100 s). Since no erase operation is performed, it is considered that stress is applied to the interlayer film more than when rewriting in an actual product. In the example considered here, if the saturation Vth is reached within 100 seconds of continuous writing (write characteristic A), it means that an interlayer film leak has occurred at that time, so the product is within the guaranteed number of rewrites. It can be determined that there is a high possibility of being defective. On the other hand, if the saturation Vth is not reached even after 100 seconds of continuous writing (writing characteristics B), it is determined that the product is highly likely not to cause an interlayer film leak even if the guaranteed number of rewritings is used. The memory cell Vth measured after this predetermined pulse application time (100 seconds) is referred to as arrival Vth. The reaching Vth (A) of the write characteristic A reaches the saturation Vth. The reaching Vth (B) of the write characteristic B does not reach the saturation Vth. It is noted that reaching Vth (B)> arriving Vth (A).
In order to confirm whether or not the reached Vth has reached the saturation Vth after the above-mentioned pulse continuous writing, a room temperature standing test from the reaching Vth was performed on various samples after continuous writing. The examination results are shown in FIG. In this test, in order to facilitate the detection of low Vth cells due to interlayer film leakage, a parallel-connected all-select 32 kb memory array formed in the scribe region by the same process as the product was used. The pulse application voltage is 18V, which is the normal write voltage of the product, and 19V, which is 1V higher as an accelerated test that applies a load to the interlayer film. In general, the write (erase) characteristics of a flash memory differ by about one digit in pulse application time to reach the same memory cell Vth when the write (erase) voltage is different by 1V. The pulse application time in the test is 100 seconds for 18V and 10 seconds for 19V. As a sample, a plurality of memory arrays having different process conditions were used.
The horizontal axis of FIG. 2 shows the reached Vth after continuous pulse writing (erasing), and the vertical axis shows the memory cell Vth measured again after standing at room temperature for one day as the amount of change from the above reached Vth. In the test results shown in FIG. 2, the amount of change on the vertical axis of the points plotted in the region where the reached Vth does not reach 8 V is a negative value. This is presumed that the charge accumulated in the floating gate electrode leaked through the interlayer film when it was left after the continuous writing (erasing) of the pulse with a load applied to the interlayer film. That is, it is determined that the samples at these plot points have reached saturation Vth during the pulse continuous write (erase) test. On the other hand, in the test results plotted in FIG. 2, the points plotted in the region where the reached Vth is 8V or more indicate that the value of the change amount on the vertical axis is almost 0V. Therefore, it is determined that the samples at these plot points do not reach the saturation Vth during the pulse continuous write (erase) test, and no leak occurs through the interlayer film. As a result, if the reached Vth reaches a certain boundary value or more, the interlayer film may leak even after the interlayer film is subjected to a load that is more than the number of product rewrites. It was found to be low and could be a criterion for guaranteeing the quality of the interlayer film.
The test results shown in FIG. 2 show that the acceleration test was performed in the same way as pulsed continuous writing (erasing) was performed on various samples using a writing (erasing) voltage of 18 V that was practically used when writing (erasing) the product. Even at a write (erase) voltage of 19V, substantially the same results are obtained for similar samples. Therefore, it is determined that the same result can be obtained by the accelerated test.
By analyzing the above test results, it is judged to be effective to determine the following criteria for assuring the quality after the rewriting operation of the interlayer film of the nonvolatile semiconductor memory. For the memory cell to be tested, it is conceivable to use a memory array or a single memory or a sample chip built in a scribe area of a wafer, for example, in the same process as the nonvolatile semiconductor memory to be evaluated. For these memory cells to be tested, a voltage is applied to the control gate electrode for a certain period of time, such as (actual write (erase) time) x (guaranteed number of rewrites in the product), in a DC or continuous pulse form. To apply stress to the interlayer film. The arrival Vth of each memory cell at that time is measured, and the amount of change in the arrival Vth is measured after being left for a predetermined time. Based on these data, the distribution shown in Fig. 2 is obtained, and a group in which the amount of change in the arrival Vth of those data can be regarded as almost zero is separated from another group in which the amount of change in the arrival Vth shows a negative value. The value of the reaching Vth of the boundary to be determined is defined as the “selection reference threshold Vth”. The significance of this selection reference threshold Vth is to apply a DC or continuous pulse voltage for a certain time to a certain memory cell to be tested, apply stress to the interlayer film, and then measure the arrival Vth. If the arrival Vth is larger than the sorting reference threshold value Vth, the nonvolatile semiconductor memory composed of other memory cells manufactured by the same process on the wafer on which the memory cell to be tested is formed is Even after the number of rewrite guarantees in the product has been rewritten, it is possible to determine that the probability of occurrence of spilling defects due to interlayer film leakage is extremely low (interlayer film QC method).
It should be noted that the method of determining the “selection reference threshold value Vth” is not necessarily highly reliable if the lower limit value of a group of sample values in which the amount of change in the reached Vth can be regarded as almost zero. For example, an appropriate safety factor is estimated and determined in consideration of a circuit operation margin, a process variation margin, and the like. In the example of the distribution as shown in FIG. 2, for example, the “selection reference threshold Vth” is set to 8.5V.
The voltage applied to the control gate electrode and the pulse application time are appropriately determined depending on the actual device shape, memory structure constant, tunnel film quality, interlayer film quality, product specifications, etc., and are not unique. In addition, a test using not only a memory array but also a single memory cell formed in the scribe region is possible, and the interlayer QC method is rather performed using a single memory. In order to shorten the evaluation time, it is effective to set the applied voltage higher than the operating voltage of the product.
[0008]
FIG. 4 is a flowchart showing a process for obtaining a “selection reference threshold value Vth” that must be reached in advance when the interlayer film QC method of the present invention is applied to a semiconductor device mass production line. After determining the device / circuit configuration and process, a semiconductor memory based on the above process is manufactured on the wafer. The steps performed in the wafer manufacturing process are as described above. Thereafter, DC or pulse continuous writing (erasing) is performed on the control gate electrode for a certain period of time as described above for each memory cell of the plurality of test target memory cells, and a load is applied to the interlayer film. After a certain time has elapsed, the arrival Vth of the floating gate electrode of the memory cell to be tested is measured. Then, the amount of change in the reached Vth is measured by leaving it at room temperature or high temperature for a predetermined time.
The saturation characteristic of the threshold value Vth of each memory cell is measured by the above-described continuous writing operation or erasing operation and the subsequent leaving process. The threshold voltage Vth is greater than the neutral threshold voltage due to electron injection (write operation) from the substrate due to continuous application of pulses, and the threshold value is neutral due to electron emission (erase operation) toward the substrate. Take a value smaller than the threshold voltage.
The “selection reference threshold value Vth” is determined by the above-described method based on the measurement data of the arrival Vth of each memory cell and the change amount thereof. This processing is performed by computer processing that collects safety factors such as circuit operation margins and process variation margins together with the measurement data of each memory cell.
[0009]
FIG. 5 shows a flowchart including an interlayer film QC method process performed for each wafer in the semiconductor device manufacturing line using the “selection reference threshold value Vth”. A DC or pulse is continuously written to the control gate electrode for a predetermined time as described above to the memory cell to be tested built in the wafer that has undergone the wafer manufacturing process, and a load is applied to the interlayer film. After a certain time has elapsed, the arrival Vth of the floating gate electrode of the memory cell to be tested is measured. In this measurement, quality can be ensured over a wide range by obtaining data at a plurality of points on the wafer. By writing operation (electron injection operation from the substrate to the floating gate), wafers whose measured Vth is below the threshold “selection reference threshold Vth” (Vthmin) are extracted from the production line and extracted. Subsequent steps are performed only for the remaining wafers that have not been removed. When performing measurement by erasing operation (electron emission operation from the floating gate to the substrate), wafers whose measured arrival Vth is equal to or higher than the threshold “selection reference threshold Vth” (Vthmin) are used. It is necessary to pay attention to the fact that the threshold value “selection reference threshold value Vth” (Vthmin) serving as a reference for selection is different for the remaining wafers that have been extracted from the production line and not extracted. There is. Although it is desirable to inspect the quality of the interlayer film by measuring a threshold value for all wafers flowing on the production line, if it can be confirmed that there are few wafers to be extracted as poor quality without satisfying the selection reference threshold value, for example, 10 It is also conceivable to inspect only a specific wafer as one piece of measurement.
After each of the above steps (wafer manufacturing step, arrival Vth measurement step, and step of taking out a wafer that does not satisfy the standard), probe inspection is performed. Normally, the wafer is baked in a state where light writing (erasing) is performed by substrate injection without applying rewriting stress, and an initial failure test of charge retention characteristics is performed. As a result, if it is judged as a non-defective product, it is cut out into a chip and packaged. Only products that are judged as non-defective products after screening (screening test) after assembly are shipped. FIG. 14 schematically shows the test results of the charge retention characteristics at room temperature using the product chips extracted after assembly. A rewrite stress equivalent to actual operation is applied to the packaged product chip, electrons are once emitted from the floating gate electrode, and then injected again from the substrate to the floating gate electrode so as to reach a certain threshold voltage. We observe the phenomenon of electrons coming out of the gate electrode. If it is a normal chip, the threshold voltage distribution as a whole moves in parallel or hardly moves.
[0010]
FIG. 6 shows a circuit configuration of a NAND flash memory. The source / drain paths of the plurality of memory cells are connected in series, and are connected to the bit line BL via a selection transistor whose gate is connected to the selection lines BDS / BSS. In the flash memory of this system, electron injection from the substrate is used for the write operation, and electron emission to the substrate is used for the erase operation. Even if the AND method and the rewrite unit are different, the write / erase operation mechanism uses the same method using the tunnel current, so that the leak failure of the interlayer film using the present invention can be detected as in the AND method. Is possible. FIG. 5 is another example of an equivalent circuit diagram of a nonvolatile semiconductor device memory array in which an interlayer film QC according to the present invention is cut by a chip after resin injection and electron injection from a substrate or electron emission to a substrate. When a large number of memories are connected in series, the Vth of the memory array is determined by the highest Vth. Even if an interlayer film leak occurs in either the injection or emission operation, a memory cell having a high memory cell Vth exists during the erase operation, and is recognized as a variation in the upper skirt of the Vth distribution after erasure.
FIG. 7 shows a circuit configuration of a NOR flash memory. The AND system is different from the circuit configuration in that the memory cells are connected to the source line SL and the data line BL without going through the selection transistor. In the NOR method, the write operation uses hot electron injection to the floating gate electrode, and the erase operation uses electron emission from the floating gate electrode to the substrate. Since the erase operation in the NOR method uses a tunnel current as in the AND / NAND method, the semiconductor memory device can be manufactured after inspecting for a leak defect of the interlayer film using the above-described steps. . That is, by measuring the write characteristics shown in FIG. 1 for each process / device structure and measuring the change amount of the memory cell Vth before and after leaving for a predetermined time shown in FIG. The memory on the wafer that reaches the Vth can be shipped as a good product. On the other hand, the NOR type write operation does not use a tunnel current and uses hot electron injection, so that the applied voltage is low and the electric field formed in the interlayer film is weak. Therefore, the non-defective product cannot be selected using the inspection process by using the write operation, but the interlayer film QC of the present invention can be performed by using the erase operation. This is because if an interlayer film leak occurs during the erase operation, it can be regarded as a phenomenon in which the erase memory cell Vth rises markedly.
[0011]
FIG. 8 is a flowchart in the case of combining a conventional capacitor breakdown voltage and an interlayer film QC (interlayer film QC1) by electron injection from the substrate of the present invention. The same procedure is performed when the interlayer film QC (interlayer film QC2) by electron emission to the substrate is combined. With respect to the wafer that has completed the manufacturing process, the withstand voltage of the tunnel film and the interlayer film is measured based on the current-voltage characteristics using a capacitor formed in the scribe region (step 1). The simple capacitor is provided in advance in the scribe region in the wafer manufacturing process so that the tunnel film and the interlayer film can be evaluated separately. The measurement is performed at one or more locations, and when not measuring all locations, for example, measurement at a plurality of points on the upper, lower, left, and right sides, for example, in FIGS. For the tunnel film, measure the current-voltage characteristics between the substrate and the floating gate electrode and examine the breakdown voltage. For the interlayer film, measure the current-voltage characteristics between the floating gate electrode and the control gate electrode, and investigate the breakdown voltage. The breakdown voltage is measured at the maximum applied voltage or higher used in actual memory operation in consideration of variation. If the measured value is less than the required breakdown voltage (Vgref1, Vgref2), the wafer is recognized as defective (step 2). Less than the threshold voltage (Vthmin) required for the measured value in the write (erase) Vth measurement using a single memory formed in the scribe area even if the withstand voltage of the capacitor passes (in the case of the interlayer film QC2, the threshold voltage or more) If it is, the wafer is recognized as having a high probability of failure and is removed from the production line. If the withstand voltage measuring step and the already described step of inspecting the interlayer film quality are performed in different regions and using different TEGs, they can be performed simultaneously in the same measuring apparatus. On the other hand, since the withstand voltage inspection can be performed even after the step of forming the tunnel film and the interlayer film even in the wafer manufacturing process, after the tunnel film and interlayer film formation process, after the formation of the first metal layer, or after the formation of the third metal layer. It is also possible to omit a process that wastes costs by detecting a defective wafer at an early stage and removing it from the production line either or after each layer formation. Also, it is not necessary to apply electrical stress to the memory cells on the chip. After the pressure resistance measurement process and the interlayer film quality inspection process, the remaining wafers that have not been removed from the production line are cut out into chips through probe inspection and sealed with resin.
In order to realize cost reduction, multilevel storage technology is now important. The charge retention characteristics of the nonvolatile memory are required to be within a certain distribution of the respective threshold voltages, and the distribution and the distribution do not overlap even if left for a long time. In multi-value storage in which a plurality of threshold voltages are set, the window must be expanded compared to binary storage (1 bit / cell), and the film quality inspection of the interlayer film according to the present invention is particularly important. Since the memory threshold voltage depends on the amount of charge in the floating gate electrode, the electric field strength applied to the tunnel film and the interlayer film varies greatly depending on the threshold voltage. The electric field strength applied to the tunnel film during charge injection is reduced with an increase in the amount of charge held in the floating gate electrode, but the electric field applied to the interlayer film increases conversely. In multi-value storage, attention must be paid to the phenomenon at a high electric field applied to the interlayer film. FIG. 15 shows the tunnel film electric field change and the interlayer film electric field change with respect to the pulse application time in the case where the tunnel film thickness is 9 nm and the interlayer film thickness is 14 nm. For example, when the threshold voltage of the memory is 6V, the interlayer electric field is 6 MV / cm, but when the threshold voltage is set to 8V assuming that the window is widened, the electric field applied to the interlayer film becomes 7 MV / cm. In an actual memory, the deterioration of the film progresses due to the rewriting operation, and therefore, a degradable defect phenomenon becomes a problem. In multi-level memory, when the threshold voltage is set higher than the neutral threshold voltage in the positive direction, a high electric field stress is applied to the interlayer film, so an interlayer film that guarantees long-term reliability of the degrading interlayer film is required. . Since the present invention can evaluate the film quality of the interlayer film, it is effective not only in binary values but also in multivalued conditions where quality control of film quality is severe.
[0012]
Since the present invention can guarantee the film quality of the interlayer film in the same wafer by using a memory array or a single memory formed in the scribe region, the product memory cell on the chip shipped to the customer as an actual product is electrically connected. It is possible to select non-defective products without applying a significant stress and without reducing the rewrite resistance of the product.
[0013]
Although the inspection in the wafer state has been described above, even if the measurement results in some areas of the wafer are certified as defective products and the wafer is removed from the production line, the number of chips that can be shipped as good products is the customer If the required number is not satisfied, it is necessary to discriminate and take out only the chips in the effective area of the wafer removed from the production line. The screening method shown below applies not only to wafers that did not satisfy the reference values in the saturation threshold measurement or capacitor breakdown voltage measurement described above until the final stage, and not only to chip cutting but also in probe inspection. You may apply to what was removed as inferior goods.
[0014]
FIG. 9 is a flowchart for explaining an interlayer film screening method 1 performed after chip cutting. Considering that a write (erase) voltage has been applied to a certain area of the memory arranged in an array on the chip, the voltage is applied in a DC manner. For example, if the time for one write (erase) is 1 ms and the guaranteed number of rewrites is 100,000, stress is applied for 100 seconds. Thereafter, the electrons erased once and the electrons accumulated in the floating gate electrode are expelled and written (erased) at a certain threshold voltage. When the minimum value of the threshold voltage distribution when left at room temperature for a certain period of time is less than or equal to the reference value determined from the product specifications, it is determined as defective. At this time, even when the electron injection is an erasing operation, the interlayer film screening can be performed on a chip basis by a similar method with the combination of writing and erasing reversed.
[0015]
FIG. 10 is a flowchart for explaining the interlayer film screening method 2 performed after chip cutting. Assuming that the erase (write) voltage is applied to a certain area of the memory arranged in an array on the chip, the voltage is applied in a DC manner. For example, if the erase (write) time is 1 ms and the guaranteed number of rewrites is 100,000 times, stress is applied for 100 seconds. After that, erase once (write after erase) after writing once. At this time, even when the electron emission is a write operation, interlayer film screening can be performed on a chip basis by the same method with the reverse combination of write and erase. When the maximum value of the threshold voltage distribution when left at room temperature for a certain period of time is equal to or greater than a reference value determined from product specifications, it is determined as defective.
[0016]
As described above, the flash memory has been described as an example. However, the method of manufacturing a semiconductor device incorporating this test process is also effective in a nonvolatile semiconductor memory such as EPROM and EEPROM having a two-layer gate structure.
[0017]
【The invention's effect】
As described above, according to the present invention, a memory array or a single memory formed in a scribe region in the same process as the product chip and subjected to the same process damage without giving stress to a good memory cell. Can be used to provide a method of manufacturing a nonvolatile semiconductor device including a memory cell interlayer QC method by simple measurement in a short time. In addition, after cutting into chips, interlayer film screening can be performed in chip units.
[Brief description of the drawings]
FIG. 1 shows a write (erase) characteristic of a nonvolatile semiconductor memory array.
FIG. 2 shows neglect characteristics of a nonvolatile semiconductor memory array.
FIG. 3 is an equivalent circuit diagram of an AND type flash memory array.
FIG. 4 is a flowchart showing a manufacturing method of a nonvolatile semiconductor manufacturing apparatus subjected to an interlayer film QC method according to the present invention.
FIG. 5 is a flowchart showing a manufacturing method of a nonvolatile semiconductor manufacturing apparatus to which an interlayer film QC method according to the present invention is applied in a manufacturing line.
FIG. 6 is an equivalent circuit diagram of a NAND flash memory array.
FIG. 7 is an equivalent circuit diagram of a NOR type flash memory array.
FIG. 8 is a flowchart showing a manufacturing method of a nonvolatile semiconductor manufacturing apparatus to which a capacitor breakdown voltage and an interlayer film QC method according to the present invention are applied.
FIG. 9 is a flowchart showing an interlayer film screening method 1 in units of chips according to the present invention.
FIG. 10 is a flowchart showing an interlayer film screening method 2 in units of chips according to the present invention.
FIG. 11 is a schematic cross-sectional view of a nonvolatile semiconductor memory.
FIG. 12 is a layout view of test patterns formed on a chip and a scribe region on a wafer.
FIG. 13 is a flowchart showing a conventional method for manufacturing a nonvolatile semiconductor manufacturing apparatus subjected to a tunnel film and interlayer film QC method.
FIG. 14 is a graph showing threshold voltage distributions before and after a high temperature storage test is performed after writing (erasing) of a nonvolatile semiconductor device.
FIG. 15 shows memory write (erase) characteristics by tunnel injection from a substrate, and analysis results of tunnel film electric field and interlayer film electric field.
FIG. 16 shows an analysis result regarding a relationship between an interlayer film electric field and an interlayer film thickness when electrons are injected from a substrate.
FIG. 17 is an analysis result regarding a relationship between an interlayer film electric field and an interlayer film thickness when electrons are emitted to the substrate.
FIG. 18 shows an analysis result regarding a relationship between an interlayer film leakage current and an interlayer film electric field.
FIG. 19 is a schematic diagram of the flow of electrons from the substrate.
[Explanation of symbols]
1 semiconductor substrate,
2 tunnel film,
3 source / drain regions,
4 Floating gate electrode,
5 interlayer film,
6 Control gate electrode,
7 chips,
8 Inspection pattern.

Claims (12)

A method of manufacturing a semiconductor device having a nonvolatile memory composed of a memory cell having a two-layer gate structure including a floating gate electrode and a control gate electrode,
A first step of determining a sorting reference threshold; and a second step of determining a non-defective product after the first step,
In the first step,
Continuous writing is performed by applying a pulse voltage or a DC voltage to the control gate electrode of each of the plurality of memory cells for a first predetermined time, and the arrival threshold value of each of the plurality of memory cells after the continuous writing is measured. And after each of the plurality of memory cells is left for a second predetermined time, a threshold value of each of the plurality of memory cells is measured to determine a change amount from the arrival threshold value for each of the plurality of memory cells. Identifying a memory cell group in which the amount of change can be regarded as substantially zero among the plurality of memory cells, and determining a selection reference threshold based on a distribution range of the arrival threshold value of each of the memory cell group,
In the second step,
Continuous writing under the same conditions as in the first step is performed to the control gate electrode of the determination target memory cell manufactured by the same process as the plurality of memory cells used in the first step, and the determination target after the continuous writing is determined. Manufacturing a semiconductor device characterized by measuring the arrival threshold value of a memory cell and determining pass / fail of a memory cell to be determined based on a magnitude relationship with a selection reference threshold value determined in the first step Method. In the first step, a lower limit value of the distribution range is determined as the selection reference threshold value,
2. The method of manufacturing a semiconductor device according to claim 1, wherein, in the second step, when the reaching threshold value of the memory cell to be determined is larger than the selection reference threshold value, the semiconductor device is determined as non-defective.   3. The method of manufacturing a semiconductor device according to claim 1, wherein the first predetermined time is determined by (writing time at the latest writing bit) × (number of times of guaranteed rewriting).   3. The method of manufacturing a semiconductor device according to claim 1, wherein the first predetermined time is determined based on at least a device shape, a memory structure constant, or a product specification. A method of manufacturing a semiconductor device having a nonvolatile memory composed of a memory cell having a two-layer gate structure including a floating gate electrode and a control gate electrode,
A first step of determining a sorting reference threshold; and a second step of determining a non-defective product after the first step,
In the first step,
Continuous erasure is performed by applying a pulse voltage or a DC voltage to the control gate electrode of each of the plurality of memory cells for a first predetermined time, and the arrival threshold value of each of the plurality of memory cells after the continuous erasure is measured. And after each of the plurality of memory cells is left for a second predetermined time, a threshold value of each of the plurality of memory cells is measured to determine a change amount from the arrival threshold value for each of the plurality of memory cells. Identifying a memory cell group in which the amount of change can be regarded as substantially zero among the plurality of memory cells, and determining a selection reference threshold based on a distribution range of the arrival threshold value of each of the memory cell group,
In the second step,
Continuous erasure is performed on the control gate electrode of the determination target memory cell manufactured by the same process as the plurality of memory cells used in the first step under the same conditions as in the first step, and the determination target after the continuous erasure is determined. Manufacturing a semiconductor device characterized by measuring the arrival threshold value of a memory cell and determining pass / fail of a memory cell to be determined based on a magnitude relationship with a selection reference threshold value determined in the first step Method. In the first step, an upper limit value of the distribution range is determined as the selection reference threshold value,
6. The method of manufacturing a semiconductor device according to claim 5, wherein, in the second step, when the reaching threshold value of the determination target memory cell is smaller than the selection reference threshold value, the semiconductor device is determined as non-defective.   7. The method of manufacturing a semiconductor device according to claim 5, wherein the first predetermined time is determined by (erase time at the latest erase bit) × (rewrite guarantee count).   The method of manufacturing a semiconductor device according to claim 5, wherein the first predetermined time is determined based on at least a device shape, a memory structure constant, or a product specification. A method of manufacturing a semiconductor device having a nonvolatile memory composed of a memory cell having a two-layer gate structure including a floating gate electrode and a control gate electrode,
A first step of determining a sorting reference threshold; a second step of determining a non-defective product after the first step; and a third step of cutting out a semiconductor chip and sealing the resin after the second step. ,
In the first step,
Electrons are injected into the floating gate electrodes of each of the plurality of memory cells by applying a pulse voltage or DC voltage for a first predetermined time to the control gate electrodes of the plurality of memory cells, and after the electron injection, The arrival threshold value of each of the plurality of memory cells is measured. After the plurality of memory cells are left for a second predetermined time, the threshold value of each of the plurality of memory cells is measured and For each of the plurality of memory cells, identifying a memory cell group having a small amount of change among the plurality of memory cells, and based on a distribution range of the arrival threshold value of each of the memory cell groups Determine the screening criteria threshold,
In the second step,
Electron injection under the same conditions as in the first step is performed on each floating gate electrode of a plurality of memory cells to be determined formed on one semiconductor wafer by the same process as the plurality of memory cells used in the first step. Each of the memory cells to be determined is measured based on the magnitude relation with the selection threshold value determined in the first step by measuring the arrival threshold value of each of the memory cells to be determined after the electron injection. Judge good or bad,
In the third step,
A method of manufacturing a semiconductor device, comprising: removing a semiconductor wafer determined to be defective in one of the determination target memory cells in the second step, cutting out a semiconductor chip from another semiconductor wafer, and sealing with a resin. In the first step, a lower limit value of the distribution range is determined as the selection reference threshold value,
10. The method of manufacturing a semiconductor device according to claim 9, wherein, in the second step, the semiconductor device is determined to be defective when an arrival threshold value of a determination target memory cell is smaller than the selection reference threshold value. A method of manufacturing a semiconductor device having a nonvolatile memory composed of a memory cell having a two-layer gate structure including a floating gate electrode and a control gate electrode,
A first step of determining a sorting reference threshold; a second step of determining a non-defective product after the first step; and a third step of cutting out a semiconductor chip and sealing the resin after the second step. ,
In the first step,
Electrons are emitted from the floating gate electrodes of each of the plurality of memory cells by applying a pulse voltage or a DC voltage for a first predetermined time to the control gate electrodes of each of the plurality of memory cells. The arrival threshold value of each of the plurality of memory cells is measured. After the plurality of memory cells are left for a second predetermined time, the threshold value of each of the plurality of memory cells is measured and For each of the plurality of memory cells, identifying a memory cell group having a small amount of change among the plurality of memory cells, and based on a distribution range of the arrival threshold value of each of the memory cell groups Determine the screening criteria threshold,
In the second step,
Electron emission under the same conditions as in the first step is performed from each floating gate electrode of a plurality of memory cells to be determined formed on one semiconductor wafer by the same process as the plurality of memory cells used in the first step. Each of the memory cells to be determined is measured based on the magnitude relationship with the selection reference threshold value determined in the first step by measuring the arrival threshold value of each memory cell to be determined after electron emission. Judge good or bad,
In the third step,
A method of manufacturing a semiconductor device, comprising: removing a semiconductor wafer determined to be defective in one of the determination target memory cells in the second step, cutting out a semiconductor chip from another semiconductor wafer, and sealing with a resin. In the first step, an upper limit value of the distribution range is determined as the selection reference threshold value,
12. The method of manufacturing a semiconductor device according to claim 11, wherein, in the second step, the semiconductor device is determined to be defective when an arrival threshold value of a determination target memory cell is larger than the selection reference threshold value.

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