JP3981192B2 - Ｓｃｉ相互接続を用いたｔｏｃカウンタの同期 - Google Patents

Ｓｃｉ相互接続を用いたｔｏｃカウンタの同期 Download PDF

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Publication number
JP3981192B2
JP3981192B2 JP26432697A JP26432697A JP3981192B2 JP 3981192 B2 JP3981192 B2 JP 3981192B2 JP 26432697 A JP26432697 A JP 26432697A JP 26432697 A JP26432697 A JP 26432697A JP 3981192 B2 JP3981192 B2 JP 3981192B2
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Japan
Prior art keywords
sci
synchronization signal
node
time counter
controller
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Expired - Lifetime
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JP26432697A
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English (en)
Japanese (ja)
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JPH10161984A5 (enExample
JPH10161984A (ja
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ブライアン・ディー・ホーナング
トニー・エム・ブレワー
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HP Inc
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Hewlett Packard Co
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/14—Time supervision arrangements, e.g. real time clock

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Multi Processors (AREA)
  • Computer And Data Communications (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)
JP26432697A 1996-09-27 1997-09-29 Ｓｃｉ相互接続を用いたｔｏｃカウンタの同期 Expired - Lifetime JP3981192B2 (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US08/720,332 US5905869A (en) 1996-09-27 1996-09-27 Time of century counter synchronization using a SCI interconnect
US720332 1996-09-27

Publications (3)

Publication Number Publication Date
JPH10161984A JPH10161984A (ja) 1998-06-19
JPH10161984A5 JPH10161984A5 (enExample) 2005-06-23
JP3981192B2 true JP3981192B2 (ja) 2007-09-26

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ID=24893605

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JP26432697A Expired - Lifetime JP3981192B2 (ja) 1996-09-27 1997-09-29 Ｓｃｉ相互接続を用いたｔｏｃカウンタの同期

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US (2) US5905869A (enExample)
JP (1) JP3981192B2 (enExample)

Families Citing this family (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6134234A (en) * 1996-07-19 2000-10-17 Nokia Telecommunications Oy Master-slave synchronization
FR2774784B1 (fr) * 1998-02-12 2004-09-24 Inside Technologies Microprocesseur comportant un systeme de synchronisation avec un evenement asynchrone attendu
US6246702B1 (en) * 1998-08-19 2001-06-12 Path 1 Network Technologies, Inc. Methods and apparatus for providing quality-of-service guarantees in computer networks
US6215797B1 (en) 1998-08-19 2001-04-10 Path 1 Technologies, Inc. Methods and apparatus for providing quality of service guarantees in computer networks
US20040208158A1 (en) * 1998-08-19 2004-10-21 Fellman Ronald D. Methods and apparatus for providing quality-of-service guarantees in computer networks
DE19844562B4 (de) * 1998-09-29 2006-06-01 Dr. Johannes Heidenhain Gmbh Verfahren zur sicheren Überwachung von Taktraten in einem redundanten System
US6377650B1 (en) 1999-08-26 2002-04-23 Texas Instruments Incorporated Counter register monitor and update circuit for dual-clock system
US6789258B1 (en) * 2000-05-11 2004-09-07 Sun Microsystems, Inc. System and method for performing a synchronization operation for multiple devices in a computer system
US6687756B1 (en) 2000-05-25 2004-02-03 International Business Machines Corporation Switched-based time synchronization protocol for a NUMA system
US7136395B2 (en) * 2000-11-30 2006-11-14 Telefonaktiebolaget L M Ericsson (Publ) Method and system for transmission of headerless data packets over a wireless link
FI113113B (fi) * 2001-11-20 2004-02-27 Nokia Corp Menetelmä ja laite integroitujen piirien ajan synkronoimiseksi
US7769942B2 (en) * 2006-07-27 2010-08-03 Rambus, Inc. Cross-threaded memory system
US9568944B2 (en) * 2014-11-14 2017-02-14 Cavium, Inc. Distributed timer subsystem across multiple devices
US11080132B2 (en) 2019-07-12 2021-08-03 Micron Technology, Inc. Generating error checking data for error detection during modification of data in a memory sub-system
US11520640B2 (en) * 2020-01-30 2022-12-06 Alibaba Group Holding Limited Efficient and more advanced implementation of ring-AllReduce algorithm for distributed parallel deep learning

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5922464A (ja) * 1982-07-29 1984-02-04 Fuji Xerox Co Ltd タイミング同期回路
US4677614A (en) * 1983-02-15 1987-06-30 Emc Controls, Inc. Data communication system and method and communication controller and method therefor, having a data/clock synchronizer and method
FR2546691B1 (fr) * 1983-05-27 1985-07-05 Cit Alcatel Base de temps asservie
SE452231B (sv) * 1986-03-07 1987-11-16 Philips Norden Ab Forfarande for synkronisering av klockor ingaende i ett lokalt netverk av busstyp
US4746920A (en) * 1986-03-28 1988-05-24 Tandem Computers Incorporated Method and apparatus for clock management
AU616213B2 (en) * 1987-11-09 1991-10-24 Tandem Computers Incorporated Method and apparatus for synchronizing a plurality of processors
CA1301261C (en) * 1988-04-27 1992-05-19 Wayne D. Grover Method and apparatus for clock distribution and for distributed clock synchronization
US4939753A (en) * 1989-02-24 1990-07-03 Rosemount Inc. Time synchronization of control networks
US5164619A (en) * 1990-11-21 1992-11-17 Hewlett-Packard Company Low skew clocking system for VLSI integrated circuits
CA2091962A1 (en) * 1992-03-31 1993-10-01 Mark L. Witsaman Clock synchronization system
US5560027A (en) * 1993-12-15 1996-09-24 Convex Computer Corporation Scalable parallel processing systems wherein each hypernode has plural processing modules interconnected by crossbar and each processing module has SCI circuitry for forming multi-dimensional network with other hypernodes

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Publication number Publication date
US5832254A (en) 1998-11-03
JPH10161984A (ja) 1998-06-19
US5905869A (en) 1999-05-18

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