JP3979490B2 - Semiconductor integrated circuit device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor integrated circuit device, and relates to a technique that is effective when used in a semiconductor integrated circuit device having an output circuit that realizes high speed and noise reduction.
[0002]
[Prior art]
By dividing the output MOSFET and shifting the timing when each MOSFET is turned on, the current is prevented from increasing sharply and di / dt is limited.
[0003]
[Problems to be solved by the invention]
In the above example, the turn-on timing is shifted by dulling the input MOSFET input waveform little by little, so the delay time from the pre-buffer input to the output increases, and the waveform recovers to VDD and VSS. It takes a long time to complete the cycle.
[0004]
An object of the present invention is to provide a semiconductor integrated circuit device including an output circuit that achieves high speed while reducing power supply noise. The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.
[0005]
[Means for Solving the Problems]
The outline of a typical invention among the inventions disclosed in the present application will be briefly described as follows. As a drive circuit for forming a drive signal supplied to the gate of the output MOSFET, the voltage change is dulled only in a certain voltage range including a voltage at which the output MOSFET changes to the off state / on state.
[0006]
DETAILED DESCRIPTION OF THE INVENTION
FIG. 1 shows a circuit diagram of an embodiment of an output circuit according to the present invention. Each circuit element in the figure is formed on one semiconductor substrate such as single crystal silicon by a known semiconductor integrated circuit manufacturing technique.
[0007]
The output circuit includes a P-channel MOSFET PQ1 and an N-channel MOSFET NQ1 connected in series between the power supply voltage and the circuit ground potential. The commonly connected drains of the P-channel MOSFET PQ1 and the N-channel MOSFET NQ1 are connected to a pad PAD, and the pad PAD is connected to a lead as an external terminal via a bonding wire (not shown).
[0008]
A signal to be output is formed by an internal logic circuit (not shown) and transmitted to the data terminal D. The signal at the data terminal D is transmitted as a drive signal to the gate (node N2) of the output MOSFET PQ1 and the gate (node N1) of the output MOSFET NQ1 through a drive circuit.
[0009]
The drive signal transmitted to the gate node N2 of the P-channel output MOSFET PQ1 is not particularly limited, but is formed by a CMOS inverter circuit composed of a P-channel MOSFET and an N-channel MOSFET that receive the signal of the data terminal D.
[0010]
The drive signal transmitted to the gate node N1 of the N-channel output MOSFET NQ1 is constituted by the following circuits in order to realize high operation while suppressing the rate of change of the output current. The P-channel MOSFET MP1 and the N-channel MOSFET MN1 constitute a CMOS inverter circuit, form an inverted signal of the signal at the data terminal D, and transmit it to the gate of the output MOSFET NQ1. These MOSFETs MP1 and MN1 are composed of MOSFETs having a relatively small size in order to reduce power supply noise, and the voltage change of the output signal is made relatively small.
[0011]
Two N-channel MOSFETs are connected in series between the node N1 and the power supply voltage. Two P-channel MOSFETs are provided in series between the node N1 and the ground potential of the circuit. The output signal of the inverter circuit that receives the signal of the data terminal D is commonly transmitted to the gate of one of the two N-channel MOSFETs and the two P-channel MOSFETs. The output signal of the inverter circuit INV1 that receives the voltage of the node N1 is transmitted to the gate of the other MOSFET MN2 of the two N-channel MOSFETs. The output signal of the inverter circuit INV2 receiving the voltage of the node N1 is transmitted to the gate of the other MOSFET MP2 of the two P-channel MOSFETs.
[0012]
Two P-channel MOSFETs are connected in series between the node N1 and the power supply voltage. Two N-channel MOSFETs are provided in series between the node N1 and the ground potential of the circuit. The signal of the data terminal D is commonly transmitted to the gate of one of the two P-channel MOSFETs and the two N-channel MOSFETs. The output signal of the inverter circuit INV3 that receives the voltage of the node N1 is transmitted to the gate of the other MOSFET MP3 of the two P-channel MOSFETs. The output signal of the inverter circuit INV4 receiving the voltage of the node N1 is transmitted to the gate of the other MOSFET MN3 of the two N-channel MOSFETs.
[0013]
The logic threshold voltage VLT1 of the inverter circuits INV1 and INV4 corresponds to the threshold voltage of the output MOSFET NQ1, that is, the lower limit voltage of a constant voltage range set around the voltage that switches from the off state to the on state. The logic threshold voltage VLT2 of the inverter circuits INV2 and INV3 is a voltage range of a constant width set around the threshold voltage of the output MOSFET NQ1, that is, the voltage that switches from the off state to the on state. It is set corresponding to the upper limit voltage.
[0014]
FIG. 2 shows a waveform diagram of a drive signal for explaining the operation of the output circuit of FIG. 1, and FIG. 3 shows a waveform diagram of the output signal. The voltage VT0 is a voltage corresponding to the threshold voltage of the output MOSFET NQ1, and the voltage region (a) is a region where the gate voltage of the MOSFET NQ1 is equal to or lower than the threshold voltage VT0 and no current flows. (B) is a region in which the current change is large with respect to the voltage change because the gate voltage of the output MOSFET NQ1 is in the vicinity of VT0 and the output potential is not constantly lowered and the VDS (source-drain voltage) is also large. (C) is a region in which the output potential decreases and VDS (source-drain voltage) decreases, and the current change decreases again with respect to the voltage change.
[0015]
In the output circuit of FIG. 1, when the output is switched from the high level to the low level, the drive signal transmitted to the node N1 changes from the high level to the low level. That is, the signal to be output transmitted to the data terminal D changes from the high level to the low level. This is a region (a) in which the output MOSFET NQ1 is not turned on until the potential of the node N1 reaches VLT1 (the logic threshold voltage of the inverter circuits INV1 and INV4) from VSS (the circuit ground potential). In this region (a), in addition to the P-channel MOSFET MP1, the output signal of the inverter circuit INV1 is at a high level, so that the output signal of the inverter circuit receiving the data terminal D is delayed from a high level to a low level. Since the two N-channel MOSFETs are turned on and current flows from the power supply voltage side to the node N1, the waveform rises sharply.
[0016]
In the region (b), since the potential of the node N1 exceeds VLT1, the output signal of the inverter circuit INV1 becomes low level, so that the MOSFET MN2 is turned off, and only the P-channel MOSFET MP1 flows current, so that the waveform change becomes slow. In the region (c), when the node N1 exceeds the logic threshold voltage VLT2 of the inverter circuits INV2 and INV3, the output signal of the inverter circuit INV3 becomes low level and the P-channel MOSFET MP3 is turned on. Since the gate of the P-channel MOSFET connected in series with the MOSFET MP3 is turned on by the low level of the data terminal D, the current flows again into the node N1, so that the drive signal waveform at the node N1 rises sharply again.
[0017]
Until the N-channel output MOSFET NQ1 is turned on, the level of the output terminal (PAD) is high, so that the P-channel output MOSFET PQ1 is on, but at the end of the signal line connected to the output terminal. Since it is the same level as the termination level VTT formed by the termination resistor provided, no current flows. Therefore, when the node N1 is in the region (a), the output signal of the inverter circuit is set to the high level to turn it off so that the current fluctuation to the VTT is eliminated. Therefore, the node N2 is switched to a high level by the inverter circuit while the node N1 is in the region a.
[0018]
When the output signal is changed from the low level to the high level, the node N1 is changed from the high level to the low level. Until the node N1 reaches the VLT2, the signal at the data terminal D changes to the high level. Therefore, in addition to the N-channel MOSFET MN1, the P-channel MOSFET MP2 is turned on by the low level of the output signal of the inverter circuit INV2. Therefore, the P-channel MOSFET connected in series with it is also turned on by the low level of the output signal of the inverter circuit that receives the signal of the data terminal D and draws out the current, so that the node N1 starts to drop sharply.
[0019]
When the node N1 falls below the VLT2 and enters the region (b), the output signal of the inverter circuit INV2 becomes a high level and the P-channel MOSFET MP2 is turned off, so that only the N-channel MOSFET MN1 supplies the current to the node N1. The waveform is dull as it is pulled out. Further, when the potential of the node N1 falls below the VLT1 to become the region (a), the output signal of the inverter circuit INV4 becomes high level, the N-channel MOSFET MN3 is turned on, and the data terminal D is connected in series with the high level. Since the N-channel MOSFET is also in the ON state, the current is drawn from such a path, so that the waveform sharply falls again.
[0020]
At this time, the P-channel output MOSFET PQ1 is in an ON state due to the low level of the output signal of the inverter circuit, and the current starts to flow. However, since the size of the P-channel MOSFET PQ1 does not need to be increased so much, as long as the cycle allows, It is only necessary to blunt the waveform. By shaping the waveform in this way, the change in the VSS current at the output can be reduced, and the output waveform can also have a uniform slope tr / tf in the entire amplitude range. As a result, the waveform recovery time can be minimized while reducing the change in the VTT current. That is, the gate input of the MOSFET at the final stage of output is shaped so as to be dulled only near the voltage at which the MOSFET is turned on.
[0021]
The delay time of the output circuit can be shortened while di / dt forming the drive voltage transmitted to the gate of the output MOSFET is limited. In addition, the gate input 0-100% recovery time of the final output MOSFET can be shortened. As a result, power noise can be reduced and the transfer cycle can be speeded up.
[0022]
Since the gate voltage range of the output N-channel MOSFET that affects di / dt is in the vicinity of the threshold voltage VT0 of the MOSFET, di / dt on the VSS side can be reduced by dulling this portion. Other voltage regions have little effect on di / dt and can be steep, so there is no problem. By shaping the gate voltage waveform of the output N-channel MOSFET in this way, the delay time of the output circuit can be shortened while suppressing di / dt, and 0-100% recovery of the gate input of the MOSFET at the final stage of output is possible. Time can be shortened. Furthermore, the output waveform can be made uniform, the 0-100% recovery time can be shortened, and di / dt on the VTT side can also be suppressed.
[0023]
The invention made by the inventor has been specifically described based on the embodiments. However, the invention of the present application is not limited to the embodiments, and various modifications can be made without departing from the scope of the invention. Nor. For example, in FIG. 1, the drive circuit as described above is provided for the P-channel output MOSFET, and the gate voltage waveform is blunted as long as the cycle permits by reducing the size of the N-channel output MOSFET. The present invention can be widely used in various semiconductor integrated circuit devices having output circuits.
[0024]
【The invention's effect】
The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows. As a drive circuit for forming a drive signal supplied to the gate of the output MOSFET, the output MOSFET is made to slow down the voltage change only within a certain voltage range including the voltage that changes to the off state / on state. , And the gate input 0-100% recovery time of the final output MOSFET can be shortened.
[Brief description of the drawings]
FIG. 1 is a circuit diagram showing an embodiment of an output circuit according to the present invention.
FIG. 2 is a waveform diagram of a drive signal for explaining the operation of the output circuit of FIG.
FIG. 3 is a waveform diagram of an output signal of the output circuit of FIG. 1;
[Explanation of symbols]
PQ1 ... P channel output MOSFET, NQ1 ... N channel output MOSFET, MP1 to MP3 ... P channel MOSFET, MN1 to MN3 ... N channel MOSFET, INV1 to INV4 ... Inverter circuit, D ... Data terminal, PAD ... Bad (output terminal).

Claims (2)

An output MOSFET that forms an output signal;
A drive circuit for forming a drive signal supplied to the gate of the output MOSFET,
The drive circuit is
A first inverter circuit for receiving a signal to be output and forming a drive signal transmitted to the gate of the output MOSFET;
First and second MOSFETs of a first conductivity type provided in series between the gate of the output MOSFET and a power supply voltage;
Third and fourth MOSFETs of the second conductivity type provided in series between the gate of the output MOSFET and the ground potential of the circuit;
A second inverter circuit that receives the signal to be output and supplies an output signal transmitted to the gates of the first and third MOSFETs;
A third inverter circuit that receives the voltage of the gate of the output MOSFET, the logic threshold voltage of which is set to the lower limit voltage within the certain range, and transmits the output signal to the gate of the second MOSFET;
A fourth inverter circuit that receives the voltage of the gate of the output MOSFET, the logic threshold voltage is set to the upper limit voltage within the certain range, and transmits the output signal to the gate of the fourth MOSFET;
Fifth and sixth MOSFETs of the second conductivity type provided in series between the gate of the output MOSFET and the power supply voltage;
Seventh and eighth MOSFETs of the first conductivity type provided in series between the gate of the output MOSFET and the ground potential of the circuit;
A fifth inverter circuit that receives the voltage of the gate of the output MOSFET, the logic threshold voltage is set to the lower limit voltage within the certain range, and transmits the output signal to the gate of the sixth MOSFET;
A sixth inverter circuit that receives the voltage of the gate of the output MOSFET, the logic threshold voltage is set to the upper limit voltage within the certain range, and transmits the output signal to the gate of the eighth MOSFET;
A semiconductor integrated circuit device, wherein the signal to be output is supplied to the gates of the fifth and seventh MOSFETs . In claim 1,
The output MOSFET is an N-channel MOSFET,
The first conductivity type is an N type,
The second conductivity type is P type,
A P-channel output MOSFET provided between the drain of the output MOSFET and the power supply voltage;
A semiconductor integrated circuit device further comprising: a seventh inverter circuit which receives the signal to be output and forms a drive signal transmitted to the gate of the P-channel output MOSFET ;

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