JP2003318722A - Semiconductor integrated circuit device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit device provided with an output circuit by which a high speed can be realized, while reducing the power supply noise. <P>SOLUTION: A drive circuit for forming driving signals to be supplied to a gate of an output MOSFET forms a drive voltage, by which the voltage change is reduced only in a constant voltage range, including voltages at which the output MOSFET is switched between off and on states. In this way, the delay time at the output circuit and the 0-100% recovery time of gate input of a MOSFET at the final stage of the output circuit is reduced, and the output waveforms are made uniform. <P>COPYRIGHT: (C)2004,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device, and more particularly to a technique effectively applied to a semiconductor integrated circuit device provided with an output circuit realizing high speed and noise reduction.

[0002]

2. Description of the Related Art By dividing an output MOSFET and shifting the timing of turning on each MOSFET, a steep increase in current is prevented and di / dt is limited.

[0003]

In the above example, the output M
Since the turn-on timing is shifted by blunting the input waveform of the OSFET little by little, the delay time from the prebuffer input to the output becomes large, and the waveform is V
It takes a long time to recover to DD and VSS, and the cycle cannot be shortened.

An object of the present invention is to provide a semiconductor integrated circuit device provided with an output circuit which realizes high speed operation while reducing power source noise. The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0005]

The outline of a typical one of the inventions disclosed in the present application will be briefly described as follows. As the drive circuit that forms the drive signal supplied to the gate of the output MOSFET, the output MOS described above is used.
The voltage change is blunted only within a certain voltage range including the voltage at which the FET changes to the off / on state.

[0006]

1 is a circuit diagram of an embodiment of an output circuit according to the present invention. Each circuit element in the figure is formed on one semiconductor substrate such as single crystal silicon by a known semiconductor integrated circuit manufacturing technique.

The output circuit is a P-channel MOSFET P connected in series between the power supply voltage and the ground potential of the circuit.
It is composed of Q1 and an N-channel MOSFET NQ1. The commonly connected drains of the P-channel MOSFET PQ1 and the N-channel MOSFET NQ1 are connected to a pad PAD, and the pad PAD is connected to a lead as an external terminal via a bonding wire or the like not shown.

A signal to be output is formed by an internal logic circuit (not shown) and transmitted to the data terminal D. The signal of the data terminal D is sent to the output MOSF via the drive circuit.
The gate of ETPQ1 (node N2) and the output MOS
The signal is transmitted to the gate (node N1) of the FET NQ1 as a drive signal.

The P-channel output MOSFET PQ1
The drive signal transmitted to the node N2 of the gate of is not particularly limited, but is composed of a P-channel MOSFET and an N-channel MOSFET for receiving the signal of the data terminal D.
It is formed of a MOS inverter circuit.

The N-channel output MOSFET NQ1
The drive signal transmitted to the node N1 of the gate of is configured by the following circuits in order to realize high operation while suppressing the change rate of the output current. P-channel MOSFET
MP1 and N-channel MOSFET MN1 form a CMOS inverter circuit, form an inverted signal of the signal of the data terminal D, and transmit it to the gate of the output MOSFET NQ1. These MOSFETs MP1 and MN1 are MOSFETs of a relatively small size to reduce power supply noise.
The voltage change of the output signal is relatively small.

Between the node N1 and the power supply voltage, 2
Two N-channel MOSFETs are connected in series.
Two Ps are provided between the node N1 and the ground potential of the circuit.
Channel MOSFETs are provided in series. 2 above
One N-channel MOSFET and two P-channel MOS
The output signal of the inverter circuit that receives the signal of the data terminal D is commonly transmitted to the gate of one MOSFET of the FETs. And two N-channel MOSF
The output signal of the inverter circuit INV1 receiving the voltage of the node N1 is transmitted to the gate of the other MOSFET MN2 of the ET. The above two P-channel MOSFETs
The output signal of the inverter circuit INV2 receiving the voltage of the node N1 is transmitted to the gate of the other MOSFETMP2.

Between the node N1 and the power supply voltage, 2
Two P-channel MOSFETs are connected in series.
Two Ns are connected between the node N1 and the ground potential of the circuit.
Channel MOSFETs are provided in series. 2 above
One P-channel MOSFET and two N-channel MOS
The signal of the data terminal D is commonly transmitted to the gate of one of the FETs. And the other MOSFETMP of the two P-channel MOSFETs
The output signal of the inverter circuit INV3 that receives the voltage of the node N1 is transmitted to the gate of the node 3. The output signal of the inverter circuit INV4 receiving the voltage of the node N1 is transmitted to the gate of the other MOSFET MN3 of the two N-channel MOSFETs.

The logic threshold voltage VLT1 of the inverter circuits INV1 and INV4 is determined by the output MO.
The threshold voltage of the SFET NQ1, that is, the logic threshold voltage of the inverter circuits INV2 and INV3, which is set corresponding to the lower limit voltage of the voltage range of a certain width set around the voltage that switches from the off state to the on state. The VLT2 is set corresponding to the threshold voltage of the output MOSFET NQ1, that is, the upper limit voltage of the voltage range of a certain width set around the voltage at which the output MOSFET NQ1 is switched from the OFF state to the ON state.

FIG. 2 is a waveform diagram of the drive signal for explaining the operation of the output circuit of FIG. 1, and FIG. 3 is a waveform diagram of the output signal. The voltage VT0 is the output MOSF
It is a voltage corresponding to the threshold voltage of ETNQ1, and the voltage region (a) is a region where the gate voltage of the MOSFET NQ1 is equal to or lower than the threshold voltage VT0 and almost no current flows. In (b), since the gate voltage of the output MOSFET NQ1 is in the vicinity of VT0 and the output potential has not been lowered, VDS (source-drain voltage) is large.
This is an area in which the change in current is large with respect to the change in voltage. And
(C) is a region in which the output potential decreases, VDS (voltage between the source and drain) decreases, and the current change again decreases with respect to the voltage change.

In the output circuit of FIG. 1, when the output is switched from high level to low level, the drive signal transmitted to the node N1 changes from high level to low level. That is, the signal to be transmitted to the data terminal D changes from the high level to the low level. Node N1
Is a region (a) where the output MOSFET NQ1 is not turned on until the potential of the output voltage reaches from VSS (ground potential of the circuit) to VLT1 (logic threshold voltage of the inverter circuits INV1 and INV4). In this region (a), in addition to the P-channel MOSFET MP1, the inverter circuit IN
Since the output signal of V1 is at the high level, the output signal of the inverter circuit that receives the data terminal D changes from the high level to the low level with a delay, and the two N-channel MOSFETs are turned on and the power supply voltage side. Since a current flows from the node N1 to the node N1, the waveform has a steep rise.

In the region (b), since the potential of the node N1 exceeds the above VLT1, the output signal of the inverter circuit INV1 becomes low level so that the MOSFET MN2 is turned off and only the P-channel MOSFET MP1 flows a current, so that the waveform changes. Get dull. In the region (c), when the node N1 exceeds the logic threshold voltage VLT2 of the inverter circuits INV2 and INV3, the output signal of the inverter circuit INV3 becomes low level and P
The channel MOSFET MP3 is turned on. This M
P-channel MOSF connected in series with OSFETMP3
Since the gate of ET is in the ON state due to the low level of the data terminal D, the drive signal waveform of the node N1 sharply rises again because the current is again fed to the node N1.

Since the level of the output terminal (PAD) is high until the N-channel output MOSFET NQ1 is turned on, the P-channel output MOSFET P
Although Q1 is on, the termination level V formed by the termination resistor provided at the end of the signal line connected to the output terminal
Since it is at the same level as TT, no current is flowing. Therefore, while the node N1 is in the region (a), the output signal of the inverter circuit is set to the high level to turn it off, so that the current fluctuation to the VTT is eliminated. Therefore, node N
2 is switched to a high level by the inverter circuit while the node N1 is in the region a.

When the output signal is changed from low level to high level, the node N1 is changed from high level to low level. Until the node N1 reaches the VLT2, the signal at the data terminal D changes to high level. Therefore, in addition to the N-channel MOSFET MN1,
Since the P-channel MOSFET MP2 is in the ON state due to the low level of the output signal of the inverter circuit INV2, the P-channel MOSFET connected in series with the P-channel MOSFET MP2 is also brought into the ON state due to the low level of the output signal of the inverter circuit which receives the signal of the data terminal D and draws out the current. Therefore, the node N1 begins to fall sharply.

When the node N1 falls below VLT2 and enters the region (b), the output signal of the inverter circuit INV2 becomes high level and the P-channel MOSFET MP2.
N-channel MOSFET MN for turning off the
The waveform is blunted because the current is extracted only by 1 and the electric charge of the node N1 is extracted. Further, when the potential of the node N1 falls below VLT1 and becomes the region (a), the output signal of the inverter circuit INV4 becomes high level and the N-channel MOSFET
The MN3 is turned on, and the high level of the data terminal D also turns on the N-channel MOSFET connected in series to the data terminal D. Therefore, since the current is also drawn from this path, the waveform falls sharply again.

At this time, the P-channel output MOSFET P
Q1 is in the ON state due to the low level of the output signal of the inverter circuit and a current starts to flow, but since the size of this P-channel MOSFET PQ1 does not need to be made so large, it is only necessary to dull the gate voltage waveform as long as the cycle allows. . By shaping the waveform in this way,
The change in VSS current at the output can be made small, and the slope tr / tf of the output waveform can be made uniform over the entire amplitude range. This makes it possible to minimize the waveform recovery time while reducing the change in VTT current. That is, the gate input of the MOSFET at the final stage of the output is shaped so as to be dull near the voltage at which the MOSFET turns on.

The delay time of the output circuit can be shortened while limiting di / dt forming the drive voltage transmitted to the gate of the output MOSFET. Also, the final stage MOSF of the output
ET gate input 0-100% recovery time can also be shortened.
This makes it possible to reduce power supply noise and speed up the transfer cycle.

Output N-channel M affecting di / dt
Since the gate voltage range of the OSFET is in the vicinity of the threshold voltage VT0 of the MOSFET, the di / dt on the VSS side can be reduced by blunting this portion. In other voltage regions, there is almost no influence on di / dt, and there is no problem even if it is steep. In this way, output N channel MOSF
By shaping the gate voltage waveform of ET, the delay time of the output circuit can be shortened while suppressing di / dt, and 0-100% of the gate input of the MOSFET at the final stage of the output.
Recovery time can also be shortened. Furthermore, the output waveform can be made uniform, the recovery time can be shortened by 0 to 100%, and the dTT on the VTT side can be shortened.
i / dt can also be suppressed.

Although the invention made by the present inventor has been specifically described based on the embodiments, the invention of the present application is not limited to the embodiments and various modifications can be made without departing from the scope of the invention. Needless to say. For example, in FIG.
In the above, the driving circuit as described above is provided for the P-channel output MOSFET, and the N-channel output MOSFET is
The gate voltage waveform is made to be blunt as long as the cycle allows by reducing the size of T. The present invention can be widely used for various semiconductor integrated circuit devices having an output circuit.

[0024]

The effects obtained by the typical ones of the inventions disclosed in the present application will be briefly described as follows. As the drive circuit that forms the drive signal supplied to the gate of the output MOSFET, the output MOS described above is used.
The delay time of the output circuit can be shortened by making the voltage change dull only within a certain voltage range including the voltage at which the FET changes to the off state / on state, and the M of the final stage of the output can be reduced.
The gate input 0-100% recovery time of the OSFET can be shortened.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an embodiment of an output circuit according to the present invention.

FIG. 2 is a waveform diagram of a drive signal for explaining the operation of the output circuit of FIG.

3 is a waveform diagram of an output signal of the output circuit of FIG.

[Explanation of symbols]

PQ1 ... P-channel output MOSFET, NQ1 ... N-channel output MOSFET, MP1 to MP3 ... P-channel M
OSFET, MN1 to MN3 ... N-channel MOSFE
T, INV1 to INV4 ... Inverter circuit, D ... Data terminal, PAD ... Bad (output terminal).

   ─────────────────────────────────────────────────── ─── Continued front page    F term (reference) 5J055 AX02 BX16 CX00 DX22 DX56                       DX72 DX73 DX83 EX07 EY21                       EZ07 EZ50 FX18 FX40 GX01                       GX05                 5J056 AA05 BB08 CC00 CC05 DD13                       DD29 EE07 EE15 FF08 GG08                       KK01

Claims (2)

[Claims] 1. An output MOSFET for forming an output signal.
And a drive circuit that forms a drive signal supplied to the gate of the output MOSFET, wherein the drive circuit changes the voltage only in a constant voltage range including the voltage at which the output MOSFET changes to an off state / on state. A semiconductor integrated circuit device characterized in that it forms a dull driving voltage. 2. The first inverter circuit according to claim 1, wherein the drive circuit receives a signal to be output and forms a drive signal transmitted to a gate of the output MOSFET, a gate of the output MOSFET, and a power supply voltage. A first conductivity type first and second MOSFET provided in series between the first MOSFET and the second MOSFET
And a second and third MOS of the second conductivity type provided in series between the gate of the output MOSFET and the ground potential of the circuit.
The FET and the first and third MOSFEs receiving the signal to be output.
A second inverter circuit for supplying an output signal transmitted to the gate of T, and a voltage of the gate of the output MOSFET are set, and a logic threshold voltage thereof is set to the lower limit voltage of the certain range, and the output signal thereof is set to the second MOSFET. Receiving the voltage of the gate of the output MOSFET and the third inverter circuit for transmitting the output signal to the gate of the fourth MOSFET, the logic threshold voltage of which is set to the upper limit voltage of the constant range. An inverter circuit, and fifth and sixth MOSFETs of the second conductivity type provided in series between the gate of the output MOSFET and the power supply voltage
And a seventh and eighth MOS of the first conductivity type provided in series between the gate of the output MOSFET and the ground potential of the circuit.
A fifth inverter circuit that receives the voltage of the FET and the gate of the output MOSFET, sets the logic threshold voltage to the lower limit voltage of the constant range, and transmits the output signal to the gate of the sixth MOSFET, and the output MOSFET A sixth inverter circuit which receives the voltage of the gate, sets its logic threshold voltage to the upper limit voltage of the above-mentioned fixed range, and transmits its output signal to the gate of the above-mentioned eighth MOSFET, and the above-mentioned fifth and A semiconductor integrated circuit device characterized by being supplied to the gate of a 7-MOSFET.