JP3977015B2 - リネームタグのスワッピングにより転送を行なうレジスタリネーミング - Google Patents
リネームタグのスワッピングにより転送を行なうレジスタリネーミング Download PDFInfo
- Publication number
- JP3977015B2 JP3977015B2 JP2000560501A JP2000560501A JP3977015B2 JP 3977015 B2 JP3977015 B2 JP 3977015B2 JP 2000560501 A JP2000560501 A JP 2000560501A JP 2000560501 A JP2000560501 A JP 2000560501A JP 3977015 B2 JP3977015 B2 JP 3977015B2
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- Japan
- Prior art keywords
- register
- rename
- instruction
- unit
- architectural
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- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
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Classifications
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- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
- G06F9/3842—Speculative instruction execution
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30003—Arrangements for executing specific machine instructions
- G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
- G06F9/30032—Movement instructions, e.g. MOVE, SHIFT, ROTATE, SHUFFLE
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30003—Arrangements for executing specific machine instructions
- G06F9/3005—Arrangements for executing specific machine instructions to perform operations for flow control
- G06F9/30054—Unconditional branch instructions
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30003—Arrangements for executing specific machine instructions
- G06F9/3005—Arrangements for executing specific machine instructions to perform operations for flow control
- G06F9/30069—Instruction skipping instructions, e.g. SKIP
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30145—Instruction analysis, e.g. decoding, instruction word fields
- G06F9/30149—Instruction analysis, e.g. decoding, instruction word fields of variable length instructions
- G06F9/30152—Determining start or end of instruction; determining instruction length
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30181—Instruction operation extension or modification
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/32—Address formation of the next instruction, e.g. by incrementing the instruction counter
- G06F9/322—Address formation of the next instruction, e.g. by incrementing the instruction counter for non-sequential address
- G06F9/323—Address formation of the next instruction, e.g. by incrementing the instruction counter for non-sequential address for indirect branch instructions
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/32—Address formation of the next instruction, e.g. by incrementing the instruction counter
- G06F9/322—Address formation of the next instruction, e.g. by incrementing the instruction counter for non-sequential address
- G06F9/324—Address formation of the next instruction, e.g. by incrementing the instruction counter for non-sequential address using program counter relative addressing
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3802—Instruction prefetching
- G06F9/3804—Instruction prefetching for branches, e.g. hedging, branch folding
- G06F9/3806—Instruction prefetching for branches, e.g. hedging, branch folding using address prediction, e.g. return stack, branch history buffer
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3802—Instruction prefetching
- G06F9/3816—Instruction alignment, e.g. cache line crossing
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3818—Decoding for concurrent execution
- G06F9/382—Pipelined decoding, e.g. using predecoding
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3824—Operand accessing
- G06F9/383—Operand prefetching
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
- G06F9/3838—Dependency mechanisms, e.g. register scoreboarding
- G06F9/384—Register renaming
Landscapes
- Engineering & Computer Science (AREA)
- Software Systems (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Advance Control (AREA)
- Executing Machine-Instructions (AREA)
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US09/115,115 US6094716A (en) | 1998-07-14 | 1998-07-14 | Register renaming in which moves are accomplished by swapping rename tags |
| US09/115,115 | 1998-07-14 | ||
| PCT/US1999/001047 WO2000004444A1 (en) | 1998-07-14 | 1999-01-18 | Register renaming in which moves are accomplished by swapping rename tags |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JP2002520729A JP2002520729A (ja) | 2002-07-09 |
| JP2002520729A5 JP2002520729A5 (enExample) | 2006-03-02 |
| JP3977015B2 true JP3977015B2 (ja) | 2007-09-19 |
Family
ID=22359381
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2000560501A Expired - Lifetime JP3977015B2 (ja) | 1998-07-14 | 1999-01-18 | リネームタグのスワッピングにより転送を行なうレジスタリネーミング |
Country Status (6)
| Country | Link |
|---|---|
| US (2) | US6094716A (enExample) |
| EP (1) | EP1095330B1 (enExample) |
| JP (1) | JP3977015B2 (enExample) |
| KR (1) | KR100586058B1 (enExample) |
| DE (1) | DE69904479T2 (enExample) |
| WO (1) | WO2000004444A1 (enExample) |
Families Citing this family (70)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH1091443A (ja) * | 1996-05-22 | 1998-04-10 | Seiko Epson Corp | 情報処理回路、マイクロコンピュータ及び電子機器 |
| US6094716A (en) | 1998-07-14 | 2000-07-25 | Advanced Micro Devices, Inc. | Register renaming in which moves are accomplished by swapping rename tags |
| US6240503B1 (en) * | 1998-11-12 | 2001-05-29 | Advanced Micro Devices, Inc. | Cumulative lookahead to eliminate chained dependencies |
| US6314471B1 (en) * | 1998-11-13 | 2001-11-06 | Cray Inc. | Techniques for an interrupt free operating system |
| US6952827B1 (en) * | 1998-11-13 | 2005-10-04 | Cray Inc. | User program and operating system interface in a multithreaded environment |
| US6862635B1 (en) | 1998-11-13 | 2005-03-01 | Cray Inc. | Synchronization techniques in a multithreaded environment |
| US6665688B1 (en) | 1998-12-23 | 2003-12-16 | Cray Inc. | Method and system for automatically regenerating data on-demand |
| US6415433B1 (en) | 1998-12-23 | 2002-07-02 | Cray Inc. | Method and system for identifying locations to move portions of the computer program |
| US6430676B1 (en) * | 1998-12-23 | 2002-08-06 | Cray Inc. | Method and system for calculating instruction lookahead |
| US6230313B1 (en) * | 1998-12-23 | 2001-05-08 | Cray Inc. | Parallelism performance analysis based on execution trace information |
| US6353829B1 (en) | 1998-12-23 | 2002-03-05 | Cray Inc. | Method and system for memory allocation in a multiprocessing environment |
| US6321379B1 (en) | 1998-12-23 | 2001-11-20 | Cray Inc. | Method and system for target register allocation |
| US6625723B1 (en) * | 1999-07-07 | 2003-09-23 | Intel Corporation | Unified renaming scheme for load and store instructions |
| US6505293B1 (en) | 1999-07-07 | 2003-01-07 | Intel Corporation | Register renaming to optimize identical register values |
| US6594754B1 (en) * | 1999-07-07 | 2003-07-15 | Intel Corporation | Mapping destination logical register to physical register storing immediate or renamed source register of move instruction and using mapping counters |
| AU2001238261A1 (en) * | 2000-02-14 | 2001-08-27 | Chicory Systems, Inc. | Predecoding instructions to determine stack change information |
| AU2001236976A1 (en) * | 2000-02-14 | 2001-08-27 | Chicory Systems, Inc. | Delayed update of a stack pointer and program counter |
| US6560671B1 (en) * | 2000-09-11 | 2003-05-06 | Intel Corporation | Method and apparatus for accelerating exchange or swap instructions using a register alias table (RAT) and content addressable memory (CAM) with logical register numbers as input addresses |
| JP3817436B2 (ja) * | 2000-09-28 | 2006-09-06 | 株式会社東芝 | プロセッサおよびリネーミング装置 |
| US6549442B1 (en) | 2002-07-25 | 2003-04-15 | Neomagic Corp. | Hardware-assisted fast bank-swap in a content-addressable-memory (CAM) processor |
| US20040103269A1 (en) * | 2002-11-27 | 2004-05-27 | Intel Corporation | Processor context register mapping |
| US7290121B2 (en) * | 2003-06-12 | 2007-10-30 | Advanced Micro Devices, Inc. | Method and data processor with reduced stalling due to operand dependencies |
| US7043626B1 (en) | 2003-10-01 | 2006-05-09 | Advanced Micro Devices, Inc. | Retaining flag value associated with dead result data in freed rename physical register with an indicator to select set-aside register instead for renaming |
| US8250348B2 (en) * | 2005-05-19 | 2012-08-21 | International Business Machines Corporation | Methods and apparatus for dynamically switching processor mode |
| US20060265555A1 (en) * | 2005-05-19 | 2006-11-23 | International Business Machines Corporation | Methods and apparatus for sharing processor resources |
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| WO2007051347A1 (en) * | 2005-10-31 | 2007-05-10 | Intel Corporation | System and method for managing a register-based stack of operand tags |
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| US7506139B2 (en) * | 2006-07-12 | 2009-03-17 | International Business Machines Corporation | Method and apparatus for register renaming using multiple physical register files and avoiding associative search |
| US7478228B2 (en) * | 2006-08-31 | 2009-01-13 | Qualcomm Incorporated | Apparatus for generating return address predictions for implicit and explicit subroutine calls |
| US7603527B2 (en) * | 2006-09-29 | 2009-10-13 | Intel Corporation | Resolving false dependencies of speculative load instructions |
| US8341383B2 (en) * | 2007-11-02 | 2012-12-25 | Qualcomm Incorporated | Method and a system for accelerating procedure return sequences |
| US8914617B2 (en) * | 2009-12-26 | 2014-12-16 | Intel Corporation | Tracking mechanism coupled to retirement in reorder buffer for indicating sharing logical registers of physical register in record indexed by logical register |
| US20120191954A1 (en) * | 2011-01-20 | 2012-07-26 | Advanced Micro Devices, Inc. | Processor having increased performance and energy saving via instruction pre-completion |
| US20120191956A1 (en) * | 2011-01-26 | 2012-07-26 | Advanced Micro Devices, Inc. | Processor having increased performance and energy saving via operand remapping |
| US8661230B2 (en) | 2011-04-15 | 2014-02-25 | International Business Machines Corporation | Allocation of counters from a pool of counters to track mappings of logical registers to physical registers for mapper based instruction executions |
| US9454371B2 (en) | 2011-12-30 | 2016-09-27 | Intel Corporation | Micro-architecture for eliminating MOV operations |
| WO2013101323A1 (en) * | 2011-12-30 | 2013-07-04 | Intel Corporation | Micro-architecture for eliminating mov operations |
| US9575754B2 (en) | 2012-04-16 | 2017-02-21 | Apple Inc. | Zero cycle move |
| US9430243B2 (en) * | 2012-04-30 | 2016-08-30 | Apple Inc. | Optimizing register initialization operations |
| US9996348B2 (en) * | 2012-06-14 | 2018-06-12 | Apple Inc. | Zero cycle load |
| US9535744B2 (en) * | 2013-06-29 | 2017-01-03 | Intel Corporation | Method and apparatus for continued retirement during commit of a speculative region of code |
| US9367317B2 (en) * | 2013-07-03 | 2016-06-14 | Intel Corporation | Loop streaming detector for standard and complex instruction types |
| US9747104B2 (en) | 2014-05-12 | 2017-08-29 | Qualcomm Incorporated | Utilizing pipeline registers as intermediate storage |
| US9588769B2 (en) | 2014-05-27 | 2017-03-07 | Via Alliance Semiconductor Co., Ltd. | Processor that leapfrogs MOV instructions |
| US11281481B2 (en) | 2014-07-25 | 2022-03-22 | Intel Corporation | Using a plurality of conversion tables to implement an instruction set agnostic runtime architecture |
| US10353680B2 (en) * | 2014-07-25 | 2019-07-16 | Intel Corporation | System converter that implements a run ahead run time guest instruction conversion/decoding process and a prefetching process where guest code is pre-fetched from the target of guest branches in an instruction sequence |
| US11068271B2 (en) | 2014-07-28 | 2021-07-20 | Apple Inc. | Zero cycle move using free list counts |
| US9430244B1 (en) * | 2015-10-28 | 2016-08-30 | Centipede Semi Ltd. | Run-time code parallelization using out-of-order renaming with pre-allocation of physical registers |
| US9858075B2 (en) | 2015-12-06 | 2018-01-02 | Centipede Semi Ltd. | Run-time code parallelization with independent speculative committing of instructions per segment |
| CN106406814B (zh) * | 2016-09-30 | 2019-06-14 | 上海兆芯集成电路有限公司 | 处理器和将架构指令转译成微指令的方法 |
| US10133620B2 (en) | 2017-01-10 | 2018-11-20 | Intel Corporation | Detecting errors in register renaming by comparing value representing complete error free set of identifiers and value representing identifiers in register rename unit |
| US10346171B2 (en) * | 2017-01-10 | 2019-07-09 | Intel Corporation | End-to end transmission of redundant bits for physical storage location identifiers between first and second register rename storage structures |
| US20180203703A1 (en) * | 2017-01-13 | 2018-07-19 | Optimum Semiconductor Technologies, Inc. | Implementation of register renaming, call-return prediction and prefetch |
| US20180203694A1 (en) * | 2017-01-16 | 2018-07-19 | Intel Corporation | Execution Unit with Selective Instruction Pipeline Bypass |
| JP7043985B2 (ja) | 2018-06-13 | 2022-03-30 | 富士通株式会社 | 演算処理装置および演算処理装置の制御方法 |
| US11175915B2 (en) * | 2018-10-10 | 2021-11-16 | Micron Technology, Inc. | Vector registers implemented in memory |
| US10949205B2 (en) | 2018-12-20 | 2021-03-16 | International Business Machines Corporation | Implementation of execution compression of instructions in slice target register file mapper |
| US11200062B2 (en) | 2019-08-26 | 2021-12-14 | Apple Inc. | History file for previous register mapping storage and last reference indication |
| US10896041B1 (en) | 2019-09-25 | 2021-01-19 | Microsoft Technology Licensing, Llc | Enabling early execution of move-immediate instructions having variable immediate value sizes in processor-based devices |
| US11416254B2 (en) | 2019-12-05 | 2022-08-16 | Apple Inc. | Zero cycle load bypass in a decode group |
| CN114647444A (zh) * | 2020-12-18 | 2022-06-21 | 意法半导体(格勒诺布尔2)公司 | 使用指令指针检测处理器上的逆向工程的方法和集成电路 |
| FR3118234B1 (fr) * | 2020-12-18 | 2024-01-19 | St Microelectronics Alps Sas | Procédé de détection d’ingénierie inversée sur une unité de traitement utilisant un pointeur d’instruction et circuit intégré correspondant |
| US11907723B2 (en) * | 2022-03-21 | 2024-02-20 | Arm Limited | Operation elimination |
| US12141583B2 (en) * | 2022-09-13 | 2024-11-12 | Arm Limited | Register reorganisation by changing a mapping between logical and physical registers based on upcoming operations and an incomplete set of connections between the physical registers and execution units |
| US12099847B2 (en) * | 2023-01-26 | 2024-09-24 | Arm Limited | Technique for improving efficiency of data processing operations in an apparatus that employs register renaming |
| US12321751B2 (en) | 2023-04-21 | 2025-06-03 | Apple Inc. | Re-use of speculative control transfer instruction results from wrong path |
| US12175248B2 (en) | 2023-04-21 | 2024-12-24 | Apple Inc. | Re-use of speculative load instruction results from wrong path |
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| DE69734093D1 (de) * | 1996-12-31 | 2005-10-06 | Metaflow Technologies Inc | System zur Ausführung von Gleitkommaoperationen |
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| US6094716A (en) | 1998-07-14 | 2000-07-25 | Advanced Micro Devices, Inc. | Register renaming in which moves are accomplished by swapping rename tags |
-
1998
- 1998-07-14 US US09/115,115 patent/US6094716A/en not_active Expired - Lifetime
-
1999
- 1999-01-18 KR KR1020017000571A patent/KR100586058B1/ko not_active Expired - Lifetime
- 1999-01-18 DE DE69904479T patent/DE69904479T2/de not_active Expired - Lifetime
- 1999-01-18 EP EP99902346A patent/EP1095330B1/en not_active Expired - Lifetime
- 1999-01-18 JP JP2000560501A patent/JP3977015B2/ja not_active Expired - Lifetime
- 1999-01-18 WO PCT/US1999/001047 patent/WO2000004444A1/en not_active Ceased
-
2000
- 2000-06-16 US US09/595,726 patent/US6256721B1/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| KR100586058B1 (ko) | 2006-06-07 |
| US6094716A (en) | 2000-07-25 |
| DE69904479T2 (de) | 2003-10-30 |
| WO2000004444A1 (en) | 2000-01-27 |
| DE69904479D1 (de) | 2003-01-23 |
| EP1095330B1 (en) | 2002-12-11 |
| JP2002520729A (ja) | 2002-07-09 |
| US6256721B1 (en) | 2001-07-03 |
| EP1095330A1 (en) | 2001-05-02 |
| KR20010053522A (ko) | 2001-06-25 |
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