JP3964798B2 - Dielectric memory and manufacturing method thereof - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a ferroelectric memory or a high dielectric memory using a dielectric material, and in particular, in a structure having a hydrogen barrier film covering a dielectric capacitor in order to maintain dielectric characteristics, cell miniaturization is possible. The present invention relates to a ferroelectric memory, a high dielectric memory device, and a manufacturing method thereof.
[0002]
[Prior art]
The development of ferroelectric memory has become the center of development with a large capacity of 256 kbit to 4 Mbit using a stack type structure. In order to realize this stack type ferroelectric memory, it is indispensable to greatly improve the degree of integration, that is, miniaturization, and a process for forming a ferroelectric capacitor, a process for forming a transistor, and a wiring process are formed. It is important to obtain process alignment with the process. It is generally processed in a reducing atmosphere, as typified by, for example, a technique of forming a contact by burying tungsten by chemical vapor deposition (W-CVD) or hydrogen sintering performed to restore transistor characteristics. In many semiconductor processes, it is how a ferroelectric capacitor maintains its polarization characteristics without being reduced.
[0003]
In the conventional technique, a technique of covering a ferroelectric capacitor using a hydrogen barrier film is used (for example, Patent Document 1 below). This is Al ₂ O _Three The hydrogen barrier film represented by (2) shields the diffusion of hydrogen generated during the semiconductor process after the formation of the ferroelectric capacitor, thereby preventing the polarization of the ferroelectric material from deteriorating. As for the covering structure of the hydrogen barrier film, the effect of the structure that completely covers the top, bottom, left and right of the ferroelectric capacitor is the largest. As described above, the deterioration of the polarization characteristics of the ferroelectric capacitor due to hydrogen is prevented, and a highly integrated ferroelectric memory or a high dielectric memory is realized.
[0004]
Hereinafter, a ferroelectric capacitor structure of a capacitor element part of the above-described conventional ferroelectric memory will be described with reference to the drawings.
[0005]
FIG. 9 is a cross-sectional view of the main part in the bit line direction of a conventional ferroelectric memory, in which cell plates are arranged in a direction perpendicular to the paper surface. A memory cell transistor 3 is formed on an impurity diffusion layer 2 separated by an element isolation insulating film (STI) region 1 on a semiconductor substrate 13. A ferroelectric capacitor 14 is formed on the first interlayer insulating film 4, a second interlayer insulating film 10 is formed covering the ferroelectric capacitor 14, and a wiring 12 is formed thereon. Has been.
[0006]
The ferroelectric capacitor 14 includes a lower electrode 6, a capacitive insulating film 7 made of a ferroelectric film, and an upper electrode 8. The lower electrode 6 is connected to a semiconductor substrate 13 on which a memory cell transistor is formed via a first contact plug 5 (storage node contact). The ferroelectric capacitor 14 has a structure covered with a hydrogen barrier film 9, and in this case, two cell plates are covered as one unit. A second contact plug (bit line contact or memory cell contact) 11 connecting the bit line and the memory cell transistor is formed through the interlayer insulating film with a space between the hydrogen barrier films.
[0007]
In this structure, the ferroelectric capacitor 14 is covered with the hydrogen barrier film 9, thereby preventing hydrogen from diffusing into the ferroelectric capacitor 14 even when processing in a reducing atmosphere after the ferroelectric capacitor 14 is formed. And deterioration of the polarization characteristics of the ferroelectric can be prevented.
[0008]
[Patent Document 1]
Japanese Patent Laid-Open No. 11-8355
[0009]
[Problems to be solved by the invention]
However, in the conventional example, a new hydrogen barrier film is arranged to increase the memory cell size. FIG. 10 shows an image showing how the size of the memory cell changes depending on the presence or absence of the hydrogen barrier film on the plane when FIG. 9 is viewed from above. This memory cell has a structure in which a bit line is placed on a dielectric capacitor, and a bit line contact 11 is formed in the source and drain regions of the transistor (Tr) through the dielectric capacitor 14. For this reason, when the hydrogen barrier film 9 is disposed, the mask alignment margin for both the hydrogen barrier film 9 and the capacitor 14 and the lithography of the bit line contact 11 and the hydrogen barrier film 9 (direction perpendicular to the hydrogen barrier, vertical space on the paper) The cell size is increased by the amount expected, which is disadvantageous for miniaturization.
[0010]
In order to solve the above-described conventional problems, the present invention provides a ferroelectric memory that can be highly integrated while maintaining the characteristics of the dielectric memory, a capacitive element for realizing the high dielectric memory, and a method for manufacturing the same. For the purpose.
[0011]
[Means for Solving the Problems]
In order to achieve the above object, a dielectric memory according to the present invention is a dielectric memory having a capacitive element including a lower electrode, a capacitive insulating film, and an upper electrode, which are sequentially formed on a semiconductor substrate from below.
The capacitive element is coated at least on its upper part with a hydrogen barrier film,
A memory cell contact for electrically connecting a wiring above the capacitive element and a semiconductor substrate or conductive layer below the capacitive element in the cell region of the dielectric memory is formed in contact with the hydrogen barrier film. It is characterized by being.
[0012]
In the first method of manufacturing a dielectric memory according to the present invention, a hydrogen barrier film is formed on a semiconductor substrate so as to cover a capacitor element including a lower electrode, a capacitor insulating film, and an upper electrode, which are sequentially formed from below.
Forming an insulating film on the entire surface of the semiconductor substrate;
In the dielectric memory cell region including the capacitive element, an opening reaching the semiconductor substrate is provided in the insulating film so that the hydrogen barrier film becomes a SAC stopper film,
A contact plug is formed in the opening.
[0013]
According to a second method of manufacturing a dielectric memory of the present invention, the entire surface of the semiconductor substrate is coated so as to cover a capacitor element composed of a lower electrode, a capacitor insulating film, and an upper electrode, which are sequentially formed on the semiconductor substrate from below. A hydrogen barrier film is formed on the
Forming an insulating film on the entire surface of the semiconductor substrate;
In the dielectric memory cell region including the capacitive element, an opening that reaches the semiconductor substrate through the insulating film and the hydrogen barrier film is provided.
A contact plug is formed in the opening.
[0014]
DETAILED DESCRIPTION OF THE INVENTION
In the dielectric memory according to the present invention, the capacitive element is covered at least on the upper side by a hydrogen barrier film, and a wiring above the capacitive element and a semiconductor substrate or conductive layer below the capacitive element in the cell region of the dielectric memory are provided. A memory cell contact filled with an electrically connecting plug is formed in contact with the hydrogen barrier film. As a result, it is possible to prevent the characteristics of the dielectric memory from being deteriorated by the hydrogen barrier film and to realize miniaturization of the cell.
[0015]
In the dielectric memory of the present invention, it is preferable that the memory cell contact is formed in a self-aligning manner using the hydrogen barrier film as a stopper film of SAC (abbreviation of Self Align Contact). The SAC is a contact formed in a self-aligned manner. Generally, when a contact is formed in a transistor, the sidewall of the gate electrode pSi is used as a stopper film so as to straddle the sidewall and the impurity diffusion layer. This is used as a miniaturization technique for forming contacts and reducing the pitch between transistors. In the present invention, the stopper film is used as an upper hydrogen barrier film. Thereby, the hydrogen barrier film can prevent the deterioration of the characteristics of the dielectric memory, and the cell can be miniaturized more easily as the number of steps.
[0016]
In the dielectric memory of the present invention, it is preferable that a cross-sectional area of the upper surface of the memory cell contact is larger than a cross-sectional area of the upper surface of the contact outside the dielectric memory cell region. Thereby, in addition to the above-described effects, the yield of the memory cell contacts can be improved.
[0017]
In the dielectric memory according to the aspect of the invention, the memory cell contact may be formed in a portion where the memory cell contact is formed in a self-aligned manner with respect to the hydrogen barrier film rather than in a long side direction in which the hydrogen barrier film extends. It is preferable to have a longer shape in the short side direction orthogonal to the long side direction in which the hydrogen barrier film extends. Thereby, in addition to the above effect, the yield of the memory cell contact can be improved without causing an increase in cell size.
[0018]
In the dielectric memory of the present invention, it is preferable that the memory cell contact is formed so as to penetrate the hydrogen barrier film. As a result, it is possible to prevent the deterioration of the characteristics of the dielectric memory by the hydrogen barrier film and to realize miniaturization of the cell.
[0019]
In the dielectric memory according to the aspect of the invention, it is preferable that the memory cell contact is a stack contact that is further electrically connected to the semiconductor substrate through a conductive layer below the capacitive element. Thereby, in addition to the above-described effects, the yield of the memory cell contacts can be improved.
[0020]
In the dielectric memory of the present invention, the hydrogen barrier film is preferably an insulating film or nitride containing a metal element.
[0021]
In addition, according to the first manufacturing method of the present invention, it is possible to prevent the deterioration of the characteristics of the dielectric memory by the hydrogen barrier film and to realize the miniaturization of the cell. In the method for manufacturing a dielectric memory according to the present invention, the step of providing the opening in the insulating film preferably uses a dry etching method using a gas containing at least a part of fluorine element. As a result, the memory cell contact can be formed without affecting the hydrogen barrier film.
[0022]
In addition, according to the second manufacturing method of the present invention, it is possible to prevent the deterioration of the characteristics of the dielectric memory by the hydrogen barrier film and to realize the miniaturization of the cell.
[0023]
Embodiments of the present invention will be described below with reference to the drawings.
[0024]
(First embodiment)
FIG. 1 is a cross-sectional view of an essential part in a first embodiment of a dielectric memory using a hydrogen barrier film 9 as a SAC stopper film. A memory cell transistor 3 is formed on an impurity diffusion layer 2 separated by an STI region 1 on a semiconductor substrate 13. On top of this, the first interlayer insulating film 4 (for example, SiO 2 ₂ A ferroelectric capacitor 14 is formed on the film, film thickness: 500 nm), and a second interlayer insulating film 10 (film thickness: 250 nm on the capacitor) is formed covering the ferroelectric capacitor 14. Wiring 12 (for example, AL / TiN / Ti = 500/20/10 nm (film thickness)) is formed. The ferroelectric capacitor 14 includes a lower electrode 6 (for example, Pt film thickness: 100 nm), a ferroelectric film (for example, SBT (for example, SrBi ₂ Ta ₂ O ₉ ) Film thickness: 100 nm) and a capacitor insulating film 7 and an upper electrode 8 (for example, Pt film thickness: 50 nm), and the lower electrode 6 is formed on the semiconductor substrate 13 on which the memory cell transistor 3 is formed. Are connected via a contact plug (storage node contact) 5 (for example, a W film). Further, the ferroelectric capacitor has a hydrogen barrier film 9 (for example, Al ₂ O _Three The film is coated with a film thickness of 20 nm. A second contact plug (bit line contact or memory cell contact) 11 (for example, a W film) that connects the wiring 12 and the impurity diffusion layer 2 of the semiconductor substrate is formed in a self-aligned manner using the hydrogen barrier film 9 as a stopper film. Yes. FIG. 1 shows a state in which the overlay is shifted within the capability range of lithography (hereinafter referred to as “litho”) equipment, and the second contact plug 11 is in contact with at least one of the hydrogen barrier films. .
[0025]
In this structure, when the hydrogen barrier film 9 is formed, it is sufficient that the contact plug 11 has a minimum necessary space so that the space between the hydrogen barrier 9 films is not stepped off in consideration of the litho overlap margin. The cell size can be made smaller than in the example. For example, if there is equipment with a direct overlay margin of 0.2 μm for litho, in the conventional example, at least between adjacent hydrogen barriers requires 0.2 μm + contact plug size (0.3 μm) + 0.2 μm = 0.5 μm However, in this structure, it is only necessary to estimate an overlap margin of 0.2 μm between the hydrogen barriers, and at least 0.3 μm can be reduced in this direction.
[0026]
With the above structure, the ferroelectric capacitor is covered with a hydrogen barrier film, so that even if processing is performed in a reducing atmosphere after the formation of the ferroelectric capacitor, hydrogen is prevented from diffusing into the ferroelectric capacitor, and the ferroelectric capacitor is formed. Deterioration of the polarization characteristics of the body can be prevented. Further, even if a new hydrogen barrier film is disposed, the cell size is not increased and a highly integrated dielectric memory can be realized.
[0027]
(Second Embodiment)
FIG. 2 is a cross-sectional view of an essential part of a second embodiment of a dielectric memory using the hydrogen barrier film 9 as a SAC stopper film. Since the thickness of each layer is the same as that of Embodiment 1, it is omitted. A memory cell transistor 3 is formed on an impurity diffusion layer 2 separated by an STI region 1 on a semiconductor substrate 13. On top of this, the first interlayer insulating film 4 (for example, SiO 2 ₂ The ferroelectric capacitor 14 is formed on the film), the second interlayer insulating film 10 is formed so as to cover the ferroelectric capacitor 14, and the wiring 12 (for example, AL / TiN / Ti) is formed thereon. ing. The ferroelectric capacitor 14 includes a lower electrode 6 (for example, Pt), a capacitor insulating film 7 made of a ferroelectric film (for example, SBT), and an upper electrode 8 (for example, Pt). The lower electrode 6 is a memory cell transistor. 3 is connected via a first contact plug 5 (for example, a W film) to a semiconductor substrate 13 on which 3 is formed. Further, the ferroelectric capacitor 14 includes a hydrogen barrier film 9 (for example, Al ₂ O _Three The film is covered with a film. A second contact plug 11 (for example, a W film) that connects the wiring 12 and the impurity diffusion layer 2 of the semiconductor substrate has a top diameter that is formed in a self-aligning manner using the hydrogen barrier film 9 as a stopper film.
[0028]
In addition, when comparing the memory cell portion and the peripheral circuit portion, even if the dielectric capacitor of the memory cell portion is flattened by CMP (chemical mechanical polishing) method, a global step is generated (arrow portion in the figure). The interlayer insulating film from the substrate is thicker than that outside the memory cell. At this time, if the space between the adjacent hydrogen barriers is set to the same size as the contact plug 15 in the peripheral circuit portion other than the memory cell region, the contact plug 11 of the memory cell increases the reticle size of the lithography, so that only the top. The bottom can be structured to have the same area as the peripheral contact. In other words, it is basically sufficient to obtain a step coverage or embedded shape similar to that of the contact plug of the peripheral circuit portion, but in order to suppress bit defects in the memory cell portion that greatly affect the overall yield, It is possible to further increase the embedding shape from the peripheral circuit portion to an extent that improves the embedding shape. However, it is practical to make the memory cell portions 0.35 μm and 0.1 μm larger than the peripheral circuit portion of 0.25 μm. With this structure, in addition to the effect of reducing the cell size described above, for example, by increasing the top diameter of the memory cell contact in which the aspect ratio becomes strict, the embedding characteristics of W, for example, are improved, and the memory cell contact yield is improved. be able to.
[0029]
(Third embodiment)
FIG. 3 is a plan view of a dielectric memory (FIG. 2) using a hydrogen barrier film as a SAC stopper film when viewed from above. A hydrogen barrier film 9 is formed on the contact plug 5 so as to cover the ferroelectric capacitor from the lower electrode 6 and the ferroelectric film and the upper electrode 8. The second contact plug 11 connecting the wiring and the impurity diffusion layer of the semiconductor substrate has a top diameter greatly extended in a direction perpendicular to the hydrogen barrier, and is formed in a self-aligning manner using the hydrogen barrier film as a stopper film. Even if the second contact plug is rectangular, it is easy to increase only the top diameter of the memory cell contact without increasing the cell size.
[0030]
(Fourth embodiment)
FIG. 4 is a fragmentary cross-sectional view of an embodiment of a dielectric memory having a structure in which the memory cell contact plug 11 penetrates the hydrogen barrier film 9. Since the thickness of each layer is the same as that of Embodiment 1, it is omitted. A memory cell transistor 3 is formed on an impurity diffusion layer 2 separated by an STI region 1 on a semiconductor substrate 13. On top of this, the first interlayer insulating film 4 (for example, SiO 2 ₂ A ferroelectric capacitor 14 is formed on the film), a second interlayer insulating film 10 is formed covering the ferroelectric capacitor, and a wiring 12 (for example, AL / TiN / Ti) is formed thereon. Yes. The ferroelectric capacitor 14 includes a lower electrode 6 (for example, Pt), a capacitor insulating film 7 made of a ferroelectric film (for example, SBT), and an upper electrode 8 (for example, Pt). The lower electrode 6 is a memory cell transistor. Is connected via a first contact plug 5 (for example, a W film). Further, the ferroelectric capacitor has a hydrogen barrier film 9 (for example, Al ₂ O _Three The film is covered with a film. A second contact plug 11 (for example, a W film) that connects the wiring 12 and the impurity diffusion layer 2 of the semiconductor substrate is formed so as to penetrate the hydrogen barrier film 9.
[0031]
In this structure, in addition to the above-described effects, the hydrogen barrier film 9 does not need to be patterned, or only needs to be patterned to such an extent that the hydrogen barrier film 9 is left only on the memory cell region. There is an effect that integration is facilitated such that the number of processes is reduced or high-precision patterning is not required.
[0032]
(Fifth embodiment)
FIG. 5 is a cross-sectional view of a principal part of an embodiment of a dielectric memory in which the memory cell contact plug 11 has a structure in which the hydrogen barrier film 9 is a SAC stopper film and is a stack contact. Since the thickness of each layer is the same as that of Embodiment 1, it is omitted. A memory cell transistor 3 is formed on an impurity diffusion layer 2 separated by an STI region 1 on a semiconductor substrate 13. On top of this, the first interlayer insulating film 4 (for example, SiO 2 ₂ The ferroelectric capacitor 14 is formed on the film), the second interlayer insulating film 10 is formed so as to cover the ferroelectric capacitor 14, and the wiring 12 (for example, AL / TiN / Ti) is formed thereon. ing. The ferroelectric capacitor 14 includes a lower electrode 6 (for example, Pt), a capacitor insulating film 7 made of a ferroelectric film (for example, SBT), and an upper electrode 8 (for example, Pt). The lower electrode 6 is a memory cell transistor. Is connected via a first contact plug 5 (for example, a W film). Further, the ferroelectric capacitor 14 includes a hydrogen barrier film 9 (for example, Al ₂ O _Three The film is covered with a film. A second contact plug 11 (for example, a W film) that electrically connects the wiring 12 and the impurity diffusion layer 2 of the semiconductor substrate is formed using a hydrogen barrier film as a SAC stopper film, and is directly connected to the semiconductor substrate. Instead, they are electrically connected via a lower conductive layer (in this case, the lower electrode 6 and the first contact plug 6 are used).
[0033]
In this structure, in addition to the above-described effects, the aspect ratio of the memory cell contact can be reduced, and the contact yield is improved.
[0034]
(Sixth embodiment)
FIG. 6 is a cross-sectional view of an essential part of an embodiment of a dielectric memory having a structure in which the memory cell contact plug 11 penetrates the hydrogen barrier film 9 and is a stack contact. Since the thickness of each layer is the same as that of Embodiment 1, it is omitted. A memory cell transistor 3 is formed on an impurity diffusion layer 2 separated by an STI region 1 on a semiconductor substrate 13. On top of this, the first interlayer insulating film 4 (for example, SiO 2 ₂ The ferroelectric capacitor 14 is formed on the film), the second interlayer insulating film 10 is formed so as to cover the ferroelectric capacitor 14, and the wiring 12 (for example, AL / TiN / Ti) is formed thereon. ing. The ferroelectric capacitor 14 includes a lower electrode 6 (for example, Pt), a capacitor insulating film 7 made of a ferroelectric film (for example, SBT), and an upper electrode 8 (for example, Pt). The lower electrode 6 is a memory cell transistor. 3 is connected via a first contact plug 5 (for example, a W film) to a semiconductor substrate 13 on which 3 is formed. Further, the ferroelectric capacitor 14 includes a hydrogen barrier film 9 (for example, Al ₂ O _Three The film is covered with a film. A second contact plug 11 (for example, a W film) that electrically connects the wiring 12 and the impurity diffusion layer 2 of the semiconductor substrate 13 is formed so as to penetrate the hydrogen barrier film 9 and is directly connected to the semiconductor substrate 13. Instead, they are electrically connected via a lower conductive layer (in this case, using the lower electrode 6 and the first contact plug 6).
[0035]
This structure also has the effect of reducing the aspect ratio of the memory cell contact and improving the contact yield, in addition to the effects described above.
[0036]
The hydrogen barrier film described above preferably contains a metal element or is a nitride. For example, Al ₂ O _Three By using TiAlO, SiN, TaO, TiO, TiAlN, TaAlN, etc., deterioration of the ferroelectric capacitor characteristics due to hydrogen can be suppressed.
[0037]
(Seventh embodiment)
In FIG. 7A, the memory cell transistor 3 is formed on the semiconductor substrate 13 including the impurity diffusion layer 2 separated by the STI region 1. Since the thickness of each layer is the same as that of Embodiment 1, it is omitted. A first interlayer insulating film 4 (for example, SiO doped with B, P, etc.) on the memory cell transistor 3 ₂ The first contact plug 5 (W, Poly Si) that electrically connects the substrate and the lower electrode 6 of the ferroelectric capacitor 14 is formed on the BPSG 2. A conductive film made of a film (Pt) for promoting crystal growth of the ferroelectric film and an oxygen barrier layer (IrO / Ir / TiAlN) is laminated thereon, and the first contact plug 5 is covered using a desired mask. In this manner, the lower electrode 6 is formed, and similarly, the capacitor insulating film 7 and the upper electrode 8 made of a ferroelectric film are formed by patterning so that the lower electrode 6 is covered, thereby forming a ferroelectric capacitor. ing. Next, as shown in FIG. 7B, after forming a hydrogen barrier film 9 on the entire surface, the hydrogen barrier film is patterned so as to cover the ferroelectric capacitor using a desired mask. Here, the hydrogen barrier film only needs to open a region where the second contact (memory cell contact) is formed between the cell plates of the memory cell. Next, as shown in FIG. 7C, after the second interlayer insulating film 10 is formed on the entire surface, it is planarized by CMP or the like and connected to the impurity diffusion layer of the memory cell transistor using a desired mask. A second contact (memory cell contact) 11 is formed. At this time, since the space between the hydrogen barrier films is narrowed as much as possible taking into account the litho overlap margin, a part of the memory cell contact 11 is formed in contact with the hydrogen barrier film. (SAC structure). Finally, as shown in FIG. 7D, the wiring 12 is formed to complete the dielectric memory.
[0038]
By covering the ferroelectric capacitor with the hydrogen barrier film by the above manufacturing method, even if the processing is performed in a reducing atmosphere after the formation of the ferroelectric capacitor, the diffusion of hydrogen into the ferroelectric capacitor is prevented, and the ferroelectric capacitor is strong. Deterioration of the polarization characteristics of the dielectric can be prevented, and even if a new hydrogen barrier film is provided, the cell size is not increased and a highly integrated dielectric memory can be manufactured.
[0039]
In FIG. 7C, the method for opening the memory cell contact is preferably dry etching using a gas containing at least a part of fluorine element. Specifically, CF _Four , CHF _Three , C _Four F ₈ , C _Five F ₈ , CH ₂ F ₂ It is good to use.
[0040]
By using these gases, it is usually used for interlayer insulating films. ₂ The etching selectivity between the film and the dense hydrogen barrier film can be set large, and the SAC structure can be realized without the influence of etching the hydrogen barrier film.
[0041]
(Eighth embodiment)
In FIG. 8A, the memory cell transistor 3 is formed on the semiconductor substrate including the impurity diffusion layer 2 separated by the STI region 1. Since the thickness of each layer is the same as that of Embodiment 1, it is omitted. A first interlayer insulating film 4 (for example, SiO doped with B, P, etc.) on the memory cell transistor 3 ₂ The first contact plug 5 (W, Poly Si) for electrically connecting the substrate and the lower electrode 6 of the ferroelectric capacitor is formed on the BPSG 2. A conductive film made of a film (Pt) for promoting crystal growth of the ferroelectric film and an oxygen barrier layer (IrO / Ir / TiAlN) is laminated thereon, and the first contact plug 5 is covered using a desired mask. In this manner, the lower electrode 6 is formed, and similarly, the capacitor insulating film 7 and the upper electrode 8 made of a ferroelectric film are formed by patterning so that the lower electrode 6 is covered, thereby forming a ferroelectric capacitor. ing. Next, as shown in FIG. 8B, a hydrogen barrier film 9 is formed on the entire surface. Although the hydrogen barrier film here is not shown in the figure, it is sufficient that the memory cell array region is patterned as a unit, and there is no need to open between the cell plates. Next, as shown in FIG. 7C, after the second interlayer insulating film 10 is formed on the entire surface, the second interlayer insulating film 10 is planarized by CMP or the like, and the second interlayer insulating film 10 and the hydrogen barrier film are formed using a desired mask. 9. Form a bit line contact 11 that penetrates the first interlayer insulating film 4 and is connected to the impurity diffusion layer of the memory cell transistor. Finally, as shown in FIG. 7D, the wiring 12 is formed to complete the dielectric memory.
[0042]
By covering the ferroelectric capacitor with the hydrogen barrier film by the above manufacturing method, even if the processing is performed in a reducing atmosphere after the formation of the ferroelectric capacitor, the diffusion of hydrogen into the ferroelectric capacitor is prevented, and the ferroelectric capacitor is strong. Deterioration of the polarization characteristics of the dielectric can be prevented, and even if a new hydrogen barrier film is provided, the cell size is not increased and a highly integrated dielectric memory can be manufactured.
[0043]
In the above embodiment, the hydrogen barrier film 9 has a structure in which the ferroelectric capacitor is directly covered and a structure in which two cell plates are bundled and covered. However, the hydrogen barrier film is indirect so as not to touch the ferroelectric capacitor. A structure (for example, a hydrogen barrier film formed on a ferroelectric capacitor through a buffer layer) or a structure in which each cell plate is covered with a hydrogen barrier film may be used.
[0044]
【The invention's effect】
As described above, the dielectric memory and the manufacturing method thereof according to the present invention provide a lithography alignment margin by forming a memory cell contact by using the hydrogen barrier film as a SAC stopper film or penetrating the hydrogen barrier film. Since there is no need to expect, miniaturization is possible without causing an increase in cell size while having a structure that prevents deterioration of the polarization characteristics of the ferroelectric capacitor due to hydrogen. Furthermore, in the SAC structure, the top diameter of the memory cell contact can be increased without increasing the cell size, and the contact yield can be improved.
[Brief description of the drawings]
FIG. 1 is a cross-sectional view of a principal part showing a hydrogen barrier film SAC type dielectric memory according to a first embodiment of the present invention.
FIG. 2 is a cross-sectional view of a principal part showing a hydrogen barrier film SAC type dielectric memory according to a second embodiment of the present invention.
FIG. 3 is a plan view of an essential part showing a hydrogen barrier film SAC type dielectric memory according to a third embodiment of the present invention.
FIG. 4 is a cross-sectional view of a relevant part showing a hydrogen barrier film penetrating dielectric memory according to a fourth embodiment of the present invention.
FIG. 5 is a fragmentary cross-sectional view showing a hydrogen barrier film-connected dielectric memory according to a fifth embodiment of the present invention.
FIG. 6 is a cross-sectional view of a relevant part showing a hydrogen barrier film-connected dielectric memory according to a sixth embodiment of the present invention.
FIG. 7 is a process sectional view showing a method for manufacturing a hydrogen barrier film SAC type dielectric memory according to a seventh embodiment of the present invention.
FIG. 8 is a process cross-sectional view illustrating a method for manufacturing a through-hydrogen barrier film dielectric memory according to an eighth embodiment of the present invention.
FIG. 9 is a cross-sectional view of a principal part showing a conventional dielectric memory.
FIG. 10 is a plan view showing a principal part of a conventional dielectric memory.
[Explanation of symbols]
1 Device isolation insulating film (STI)
2 Impurity diffusion layer
3 Memory cell transistors
4 First interlayer insulating film
5 First contact plug (storage node contact)
6 Lower electrode
7 Capacitive insulation film
8 Upper electrode
9 Hydrogen barrier film
10 Second interlayer insulating film
11 Second contact plug (bit line contact)
12 Wiring
13 Semiconductor substrate
14 Ferroelectric capacitor
15 Peripheral contact plug outside the memory cell area

Claims (8)

In a dielectric memory having a capacitive element composed of a lower electrode, a capacitive insulating film, and an upper electrode formed in order from below on a semiconductor substrate,
The capacitive element is formed on the first interlayer insulating film, and at least an upper part thereof is covered with a hydrogen barrier film,
The hydrogen barrier film is covered with a second interlayer insulating film;
A memory cell contact electrically connecting a wiring above the capacitive element and a semiconductor substrate or conductive layer below the capacitive element in the cell region of the dielectric memory includes the first interlayer insulating film and the second interlayer dielectric film. The cross-sectional dimension of the opening region of the memory cell contact in the first interlayer insulating film by passing through the interlayer insulating film and contacting the hydrogen barrier film. A dielectric memory characterized in that it is smaller than the cross-sectional dimension of the opening region of the memory cell contact above the hydrogen barrier film .   The dielectric memory according to claim 1, wherein the memory cell contact is formed in a self-aligning manner using the hydrogen barrier film as a SAC stopper film.   The dielectric memory according to claim 2, wherein a cross-sectional area of an upper surface of the memory cell contact is larger than a cross-sectional area of an upper surface of the contact outside the dielectric memory cell region. The memory cell contact is perpendicular to the first direction than the first direction in which the hydrogen barrier film extends in a portion where the memory cell contact is formed in a self-aligned manner with respect to the hydrogen barrier film . 4. The dielectric memory according to claim 3, wherein the dielectric memory has a rectangular shape longer in two directions .   The dielectric memory according to claim 1, wherein the memory cell contact is a stack contact that is further electrically connected to the semiconductor substrate via a conductive layer below the capacitive element. The hydrogen barrier film, a dielectric memory according to claim 1及至5 is an insulating film or a nitride containing a metal element. Forming a first interlayer insulating film on the semiconductor substrate;
Forming a capacitive element including a lower electrode, a capacitive insulating film, and an upper electrode formed in order from below on the first interlayer insulating film;
Forming a hydrogen barrier film so as to cover at least the upper part of the capacitive element ;
Forming a second interlayer insulating film on the entire surface of the semiconductor substrate including on the hydrogen barrier film;
In the dielectric memory cell region including the capacitive element, the hydrogen barrier film penetrates the first interlayer insulating film and the second interlayer insulating film so as to serve as a SAC stopper film. a step of opening Ru provided to reach,
Forming a contact plug in the opening ,
In the step of providing the opening, the opening is in contact with the hydrogen barrier film, so that a cross-sectional area of the opening region of the opening in the first interlayer insulating film is in the second interlayer insulating film. A method for manufacturing a dielectric memory, comprising: forming a smaller area than a cross-sectional area of an opening region of the opening above the hydrogen barrier film . 8. The method of manufacturing a dielectric memory according to claim 7 , wherein the opening is formed in the insulating film by a dry etching method using a gas containing at least a part of fluorine element.

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