JP3950847B2 - Clock synchronization system and clock synchronization method - Google Patents

Description

  The present invention relates to a system and method for synchronizing clocks between devices connected via a network, particularly an Internet protocol network (hereinafter referred to as an IP network).

  As a method of synchronizing devices in a communication system that transmits video data, audio data, etc. over an IP network, the accuracy of the reference clock used on the transmission side is transmitted to the reception side via the IP network. Thus, there is a clock synchronization method in which the clock accuracy on the receiving side is matched with the accuracy of the reference clock. As an example, the transmitting device sends time information based on the reference clock to the IP network, and the receiving device counts the time with the internal clock from the oscillator whose output frequency is fixed, and the time information obtained by the counting. There is a synchronization method that periodically corrects the time based on time information received via the IP network.

  However, there is a variation (fluctuation) in the data transfer delay time generated in the IP network depending on the traffic conditions. For this reason, in the above-described synchronization method, the reception timing of the time information varies every time due to fluctuations in the data transfer delay time, and the corrected time does not have a constant accuracy.

  In addition, when the accuracy of the oscillator of the receiving apparatus is poor, the clock frequency may be faster or slower than the reference clock on the transmission side. When there is a shift in the clock frequency in this way, the shift in time information between the transmission apparatus and the reception apparatus increases with time, and the amount of correction in each reception apparatus gradually increases. The correction amount deviation due to this frequency deviation is a regular change when there is no fluctuation in the data transfer delay time. However, since fluctuations in the data transfer delay time usually exist, the deviation of the correction amount in the receiving apparatus does not become such a regular change but becomes indefinite. For this reason, it is difficult for the receiving device to maintain accurate time information continuously.

  In view of this, an IP terminal device capable of clock synchronization in consideration of fluctuations in data transfer delay time and clock frequency deviation has been proposed (see Patent Document 1). This IP terminal device receives a synchronization timing packet transmitted at a constant interval from the transmission side, synchronizes the internal clock with the reference clock on the transmission side, and includes a clock counter that counts the internal clock. From the start of communication, the counter value (X0) of the clock counter at the reception timing of the first synchronization timing packet and the counter value (Xn) of the clock counter at the subsequent reception timing of the synchronization timing packet are given by the following equations. Two inclinations K1 and K2 are obtained, and when the difference between these inclinations is within a certain range, a regular change in the deviation of the correction amount is estimated from the average of both inclinations.

K1 = {(Xn−X0) + Y} / T1
K2 = {(Xn−X0) −Y} / T1
Here, Y is an upper limit value of fluctuation.
JP 2001-186180 A

  As described above, in the synchronous method in which the receiving device periodically corrects the time information counted by the internal clock based on the time information received via the IP network, there is fluctuation in the data transfer delay time. Therefore, there is a problem that the corrected time does not have a certain accuracy. Further, there is a problem that it is difficult to maintain accurate time information when the accuracy of the oscillator of the receiving device is poor. The latter problem can be solved by using an expensive high-precision oscillator, but in that case, it is disadvantageous in terms of cost.

  In the IP terminal device described in Patent Literature 1, two processes such as obtaining two inclinations K1 and K2 and further obtaining an average of both inclinations in a state where the difference between these inclinations K1 and K2 is within a certain range. There is a problem that it is necessary to do.

  In addition, “/ T1” in the expressions related to the slopes K1 and K2 described above is correctly “/ (n × T1)”, and is assumed to increment the value of n each time a packet is received. Therefore, in the IP network, there is a problem that the slopes K1 and K2 cannot be obtained accurately in an environment where packet loss (intra-network discard) frequently occurs.

  SUMMARY OF THE INVENTION An object of the present invention is to solve the above-described problems and to easily and accurately match the clock accuracy on the receiving side with the clock accuracy on the transmitting side, a clock synchronization system, a clock synchronization method, and a clock frequency error determination method. Is to provide.

  A further object of the present invention is to provide a clock synchronization system, a clock synchronization method, and a clock frequency error determination method capable of accurately maintaining the accuracy of the clock on the receiving side even in an environment where packet loss (intra-network discard) occurs frequently. Is to provide.

  Another object of the present invention is to provide a transmitter and a receiver that constitute such a clock synchronization system.

  The clock synchronization system according to the present invention is characterized in that, at a predetermined transmission interval based on a reference clock, at least a transmission device that transmits timing information including information on the predetermined transmission interval, and the timing information is received via a network. A receiving device, wherein the receiving device receives the timing information based on an oscillator whose output clock frequency varies according to the magnitude of the input control voltage, and an internal clock obtained from the output of the oscillator. Time-counting means for measuring the interval, and a value when the time-measurement means times the transmission interval included in the timing information in an ideal state where the frequency of the internal clock matches the frequency of the reference clock is calculated as a theoretical value Each time the reception interval is timed by the timing means, the timed value and the expected value calculation unit. The difference between the calculated theoretical value and the cumulative value is cumulatively added, and when the cumulative added value is out of a predetermined threshold range, the control is performed so that the frequency of the internal clock approaches the frequency of the reference clock. And an error determination unit that controls the magnitude of the voltage.

  In the above configuration, the theoretical value is the reception interval (matching the transmission interval) when the timing information is received with no fluctuation in the data transfer delay time, and the internal value in the ideal state where the frequency matches the frequency of the reference clock. It corresponds to the value measured with the clock. Therefore, if the value of the reception interval measured with the internal clock is controlled so as to approach the theoretical value, the frequency of the internal clock approaches the frequency of the reference clock.

  In addition, when the accuracy of the oscillator of the receiving apparatus is poor and there is a frequency shift between the internal clock and the reference clock, a difference is generated between the value measured by the internal clock and the theoretical value. Since this difference changes regularly when there is no fluctuation in the data transfer delay time, it is easy to synchronize with the reference clock by detecting the regular change and correcting the frequency of the internal clock. Is possible. However, in actuality, the difference between the value measured by the internal clock and the theoretical value is accompanied by fluctuation due to fluctuations in the data transfer delay time, and thus it is difficult to detect such a regular change. Therefore, in the present invention described above, every time the timing information reception interval is timed, the difference between the timed value and the theoretical value is obtained and cumulatively added. For example, when the frequency of the internal clock is faster than the frequency of the reference clock, the cumulative addition value gradually increases periodically, although the fluctuation is caused by fluctuation of the data transfer delay time. On the other hand, when the frequency of the internal clock is slower than the frequency of the reference clock, the cumulative added value decreases periodically. This periodic increase / decrease of the cumulative addition value corresponds to the regular change of the difference, and when the cumulative addition value falls outside the predetermined threshold range, the frequency of the internal clock approaches the frequency of the reference clock. By controlling in this way, it is possible to easily synchronize with the reference clock, and the internal clock can be maintained with a certain accuracy.

  Since the correction of the frequency of the internal clock based on the cumulative addition value described above is merely the cumulative addition by taking the difference between the value measured by the internal clock and the theoretical value, the two slopes described in Patent Document 1 are used. The processing is simpler than the method for obtaining K1 and K2.

In the clock synchronization system of the present invention described above, when the timing means receives the timing information, it clears the count value held so far, and the interval from reception of the timing information to reception of the next timing information. A timing counter that counts based on the internal clock, and a latch circuit that holds a count value immediately before the timing counter is cleared, each time the error determination unit receives the timing information, A difference between the count value held in the latch circuit and the theoretical value calculated by the expected value calculation unit may be obtained and cumulatively added . With the configuration as this, the realization of a system having features of the clock synchronization system of the present invention becomes possible.

  In the above case, the timing information further includes an order number indicating the number of information transmitted, and when the receiving apparatus receives the timing information, the order included in the received timing information A data extraction unit for determining the continuity based on the number, and when the data extraction unit determines that the continuity is abnormal, the value held in the latch circuit is set to the expected value. You may make it set compulsorily as a theoretical value calculated in a calculating part. According to this configuration, when packet loss (intra-network discarding) or transfer order change occurs, the sequence number included in the received timing information becomes discontinuous, resulting in an abnormality in continuity. It is judged that For the timing information whose sequence numbers are discontinuous, the calculated difference is forcibly set to zero. For this reason, the packet loss (intra-network discard) or the transfer order is not affected by the accumulated difference value.

In the clock synchronization system of the present invention described above, when the timing means receives the timing information, the theoretical value calculated by the expected value calculation unit is set as an initial value, and the next time from the reception of the timing information. A timing down counter that counts down the interval until reception of the timing information based on the internal clock, and a latch circuit that holds a count value immediately before the initial value of the timing down counter is set, and the error Each time the timing information is received, the determination unit obtains a difference between the count value held in the latch circuit and the theoretical value calculated by the expected value calculation unit, and cumulatively adds the difference. Also good . By configuration as this, the realization of a system having features of the clock synchronization system of the present invention becomes possible.

  In the above case, the timing information further includes an order number indicating the number of information transmitted, and when the receiving apparatus receives the timing information, the order included in the received timing information A data extraction unit for determining the continuity based on the number, and if the data extraction unit determines that the continuity is abnormal, the count value held in the latch circuit is forcibly It may be set to 0. Even with this configuration, packet loss (intra-network discard) or transfer order change does not affect the accumulated difference value.

  In any one of the configurations of the clock synchronization system of the present invention described above, the transmission device may receive the timing information at a first transmission interval as the predetermined transmission interval for a certain period after the start of communication with the reception device. The timing information may be generated and transmitted at a second transmission interval longer than the first transmission interval. According to this configuration, in the receiving apparatus, for a certain period after the start of communication, the logical value calculated based on the first transmission interval shorter than the second transmission interval and the value measured by the internal clock (reception interval) When the accumulated addition value of the difference is out of a predetermined threshold range, the frequency of the internal clock is corrected. After a certain period, the difference between the logical value calculated based on the second transmission interval longer than the first transmission interval and the value (reception interval) measured by the internal clock is obtained. When the accumulated addition value is out of the predetermined threshold range, the frequency of the internal clock is corrected. When such correction is performed, the transmission interval is short in a certain period after the start of communication, so that the internal clock can be corrected more quickly. By being long, timing information can be transmitted efficiently.

  The clock synchronization method according to the present invention is characterized in that the transmitting device transmits, at a predetermined transmission interval based on a reference clock, timing information including at least information on the predetermined transmission interval to the receiving device; Each time the receiving apparatus receives the timing information, the count value obtained by counting the interval from the reception of the previous timing information to the reception of the current timing information with the own clock, and the frequency of the own clock is the reference clock. In the ideal state that matches the frequency of the self, the difference from the theoretical value that is a value when the predetermined transmission interval included in the received timing information is counted based on the own clock is obtained and accumulated. In addition, when the cumulative addition value is out of a predetermined threshold range, the frequency of the own clock is changed to the frequency of the reference clock. It will contain a second step of adjusting a direction approaching.

  In the above case, the timing information further includes an order number indicating the number of information transmitted, and when the receiving apparatus receives the timing information, the order included in the received timing information A step of determining the continuity based on the number and forcibly setting the difference calculated for the received timing information to 0 when the determination becomes abnormal may be further included.

  Further, in the first step, the transmission device generates and transmits the timing information at the first transmission interval as the predetermined transmission interval for a certain period after the communication with the reception device starts. 24. The clock synchronization method according to claim 22, further comprising a step of generating and transmitting the timing information at a second transmission interval longer than the first transmission interval.

  Also in the clock synchronization of the present invention as described above, the same operation as the above-described feature of the clock synchronization system of the present invention is achieved.

  The clock frequency error determination method of the present invention is characterized in that a receiving apparatus that receives timing information including at least information on the predetermined transmission interval, which is transmitted by the transmitting apparatus at a predetermined transmission interval based on a reference clock, via a network. In the clock frequency error determination method performed in the step of counting the reception interval of the timing information with its own clock, and in an ideal state where the frequency of the own clock matches the frequency of the reference clock, A step of calculating a theoretical value that is a value when the predetermined transmission interval included in the timing information is counted, and each time the count value of the reception interval is obtained, the obtained count value Obtaining a difference from the theoretical value and accumulating the difference, and the accumulated value is a predetermined threshold value. On whether out of the circumference is to and determining a frequency error with respect to the reference clock of the own clock.

  In the above case, the timing information further includes an order number indicating the number of transmitted information. When the timing information is received, the timing information is based on the order number included in the received timing information. A step of determining the continuity and forcibly setting the difference calculated for the received timing information to 0 when the determination becomes abnormal.

  The clock frequency error determination method according to the present invention as described above also exhibits the same operation as the characteristics of the clock synchronization system according to the present invention described above.

  The receiving apparatus according to the present invention is characterized in that, in a receiving apparatus that receives at least timing information including information on the predetermined transmission interval, which is transmitted by the transmitting apparatus at a predetermined transmission interval based on a reference clock. An oscillator in which the frequency of the output clock changes according to the magnitude of the control voltage, a clocking means for timing the reception interval of the timing information based on the internal clock obtained from the output of the oscillator, and the frequency of the internal clock An expected value calculation unit that calculates a theoretical value as a value when the timing unit counts the transmission interval included in the timing information in an ideal state that matches the frequency of the reference clock; and the timing unit receives Every time the interval is timed, the difference between the timed value and the theoretical value calculated by the expected value calculation unit is obtained and cumulatively added. Both include an error determination unit that controls the magnitude of the control voltage so that the frequency of the internal clock approaches the frequency of the reference clock when the cumulative addition value is out of a predetermined threshold range. is there.

In the above case, when the timing means receives the timing information, it clears the count value held so far, and sets the interval from the reception of the timing information to the reception of the next timing information based on the internal clock. And a latch circuit that holds a count value immediately before the timing counter is cleared, and the error determination unit is held in the latch circuit every time the timing information is received. A difference between the count value and the theoretical value calculated by the expected value calculation unit may be obtained and cumulatively added. As this case, before Symbol timing information further includes a sequence number indicating which information transmitted ordinal number, when receiving the timing information, on the basis of the sequence number contained in the timing information thus received A data extraction unit for determining continuity; when the data extraction unit determines that the continuity is abnormal, the value stored in the latch circuit is calculated by the expected value calculation unit; You may comprise so that it may be forcedly set as a theoretical value to be performed.

  When the timing means receives the timing information, the theoretical value calculated by the expected value calculation unit is set as an initial value, and an interval from reception of the timing information to reception of the next timing information A timing down counter that counts down based on the internal clock, and a latch circuit that holds a count value immediately before the initial value of the timing down counter is set. Each time it is received, a difference between the count value held in the latch circuit and the theoretical value calculated by the expected value calculation unit may be obtained and cumulatively added. In this case, the error determination unit increases the control voltage when the cumulative added value exceeds the upper limit value of the predetermined threshold range, and the cumulative added value falls below the lower limit value of the predetermined threshold range. In some cases, the control voltage may be lowered. In addition, the timing information further includes a sequence number indicating what number of information is transmitted. When the timing information is received, the continuity is determined based on the sequence number included in the received timing information. A data extraction unit that determines whether the count value held in the latch circuit is forcibly set to 0 when the data extraction unit determines that the continuity is abnormal. Also good.

  The receiving device of the present invention as described above also exhibits the same operation as the characteristics of the clock synchronization system of the present invention described above.

  The transmitting device of the present invention is characterized in that, in a transmitting device that transmits timing information for clock synchronization to a receiving device connected via a network, the timing information is based on a reference clock supplied from the outside. A timing counter for generating a cycle timing for transmitting at a predetermined transmission interval, and data including information on the predetermined transmission interval and a sequence number indicating a transmission order are generated based on the cycle timing, A data generation unit that transmits the timing information. In this case, the data generation unit generates and sends the timing information at the first transmission interval as the predetermined transmission interval for a certain period after the start of communication with the receiving device, and thereafter The timing information may be generated and transmitted at a second transmission interval longer than one transmission interval.

  According to the transmission apparatus of the present invention as described above, the operation described in the above-described features of the clock synchronization system of the present invention is achieved by the combination with the reception apparatus of the present invention.

  As described above, according to the present invention, even if the data transfer delay time fluctuates, the tendency of the frequency error with respect to the reference clock of the internal clock is expressed by the value (reception interval) measured by the internal clock and the theoretical value. Accurate determination can be made by a simple calculation process using the cumulative addition value of the difference between them. Therefore, the internal clock can be maintained with a constant accuracy, and the internal clock accuracy error can be further reduced.

  In addition, since the internal clock can be maintained with a certain accuracy, an inexpensive voltage-controlled crystal oscillator can be used as the oscillator used in the receiving apparatus. Therefore, the cost of the receiving device can be reduced. This cost reduction effect increases as the number of receiving devices increases with respect to the transmitting device.

  Furthermore, since the internal clock frequency is corrected so as to approach the reference clock frequency each time the accumulated difference value is out of the predetermined threshold range, the frequency adjustment amount can be kept low. Therefore, fluctuations in clock timing due to adjustment of frequency accuracy can be suppressed.

  Furthermore, the order number of the timing information is managed on the receiving device side, and when the timing information is lost or the transfer order is changed due to a temporary state change of the IP network, the received data of the timing information is changed. Since it is made invalid, the tendency of the frequency error of the internal clock with respect to the reference clock can be accurately determined, and the reliability of the frequency accuracy in the receiving apparatus is improved.

  Next, embodiments of the present invention will be described with reference to the drawings.

  The main parts of a receiving apparatus and a transmitting apparatus constituting a clock synchronization system according to an embodiment of the present invention are shown in FIGS. The configuration of the clock synchronization system of this embodiment will be described below with reference to FIGS.

  Referring to FIG. 3, a transmission device 2 to which a reference clock is supplied from a reference oscillator 301 is connected to be able to communicate with a reception device 1 via an IP network 302. As shown in FIG. 2, the main part of the transmission apparatus 2 includes a timing counter 201, a data generation unit 202, a UDP interface 203, an IP interface 204, and an ETHER interface 205.

  The timing counter 201 generates a periodic timing for sending timing information at a predetermined interval based on a clock obtained by dividing the reference clock supplied from the reference oscillator 301. The count time setting of the timing counter 201 is variable and can be set in advance from the outside.

  The data generation unit 202 generates timing information including sequence number data and timing interval data, and supplies the generated timing information to the UDP interface 203 at a periodic timing supplied from the timing counter 201. The sequence number data is data indicating what number the generated timing information corresponds to, and the value is incremented by 1 every time the timing information is generated, and returns to the initial value when reaching a certain value. It is like that. The timing interval data is data indicating the transmission interval of the timing information, and coincides with the periodic timing interval supplied from the timing counter 201.

  The UDP interface 203 adds a UDP header in which a UDP port number for transferring the timing information is added to the timing information supplied from the data generation unit 202 and transfers the timing information to the IP interface 204.

  The IP interface 204 adds, to the data transferred from the UDP interface 203, an IP header in which the IP address of the receiving device 1 is written as the destination IP address and its own IP address is written as the source IP address. Supplied to the ETHER interface 205. FIG. 4 shows a format example of transmission data. In this example, the transmission data 401 is provided with an IP header and a UDP header sequentially from the top, and sequence number data and timing interval data as timing information are sequentially stored after the UDP header. The destination IP address of the IP header is the IP address of the receiving device 1. The port number in the UDP header is a unique value assigned for timing information transfer.

  The ETHER interface 205 has an Ethernet interface function as a physical interface of the IP network, and transmits transmission data supplied from the IP interface 204 onto the IP network 302. The transmission data transmitted on the IP network 302 is received by the receiving device 1.

  As shown in FIG. 1, the main part of the receiving apparatus 1 includes an ETHER interface 101, an IP interface 102, a UDP interface 103, a timing counter 104, a counter data latch unit 105, a data extraction unit 106, an expected value calculation unit 107, a difference calculation. Unit 108, error determination unit 109, D / A converter 110, voltage controlled crystal oscillation circuit (VCXO) 111, and division period 112.

  The ETHER interface 101 has an Ethernet interface function as a physical interface of the IP network 302, and transfers data received from the transmission apparatus 2 via the IP network 302 to the IP interface 102. The IP interface 102 has an IP protocol termination function. When the destination IP address of the received data is compared with the IP address assigned in advance to the receiving apparatus 1, the IP addresses match. Only, the received data is transferred to the UDP interface 103. That is, only received data addressed to the receiving device 1 and whose source IP address is determined to be the transmitting device 1 is transferred from the IP interface 102 to the UDP interface 103.

  The UDP interface 103 has a UDP protocol termination function, and whether the destination port number in the UDP header of the received data transferred from the IP interface 102 is a port number (unique value) assigned for timing information transfer. Is matched. When the collation matches, the UDP interface 103 notifies the timing counter 104 that the reception of timing information has been detected, and transfers data corresponding to the timing information to the data extraction unit 106. The timing counter 104 receives a clock obtained by dividing the output clock of the VCXO 111 by the frequency divider 112, and performs a counting operation with this input clock. When the timing counter 104 receives a notification of timing information reception detection from the UDP interface 103, the timing counter 104 clears the count value and continues the counting operation.

  The counter data latch unit 105 holds the count value immediately before the timing counter 104 clears the count value upon receiving notification of timing information reception detection. The count value latched by the counter data latch unit 105 corresponds to a value obtained by counting an interval from the timing at which the previous timing information is received to the timing at which the next timing information is received. The data extraction unit 106 extracts sequence number data and timing interval data from the data transferred from the UDP interface 103. The sequence number data is a serial number with which the transmission order of timing information can be determined, and is returned to the initial value when it is increased to a certain value. The timing interval data indicates time information of intervals at which timing information is transmitted.

  The expected value calculation unit 107 acquires the transmission interval of timing information from the sequence number data and timing interval data supplied from the data extraction unit 106. In addition, when the frequency of the output clock of the VCXO 111 is equal to the frequency of the reference clock on the transmission side (ideal clock accuracy), the expected value calculation unit 107 sets the timing counter 104 for the transmission interval of the acquired timing information. Calculate the theoretical value of how much to count. The difference calculation unit 108 calculates a value obtained by subtracting the theoretical count value output from the expected value calculation unit 107 from the count value latched by the counter data latch unit 105.

  The digital value output from the error determination unit 109 is supplied to the VCXO 111 as a control voltage via the D / A converter 110. The error determination unit 109 cumulatively adds the calculation results of the difference calculation unit 108 and determines whether the cumulative addition result is within a predetermined upper limit value and lower limit value range. When the cumulative addition result exceeds the upper limit value, the error determination unit 109 controls the digital value output so that the output of the D / A converter 110 is decreased. On the contrary, when the cumulative addition result falls below the lower limit value, the error determination unit 109 controls the digital value output so as to increase the output of the D / A converter 110. If the result of the cumulative addition is within the range between the upper limit value and the lower limit value, the error determination unit 109 maintains the output of the D / A converter 110 as it is without controlling the digital value output.

  The D / A converter 110 supplies an analog voltage corresponding to the digital value supplied from the error determination unit 109 to the VCXO 111. The VCXO 111 is controlled such that when the analog voltage supplied from the D / A converter 110 is high, the frequency of the output clock is high, and when the analog voltage is low, the frequency of the output clock is low. The output of the VCXO 111 is supplied to the frequency divider 112 and is output to the outside as an accuracy adjustment clock. The frequency divider 112 supplies a clock obtained by dividing the output of the VCXO 111 to the timing counter 104 as a count clock.

  When the data extraction unit 106 detects an abnormality in missing or changing numbers in the sequence number data extracted from the timing information, the data extraction unit 106 sends a counter data latch unit to the expected value calculation unit 107 instead of the theoretical count value. It notifies that the same value as the count value of 105 is output to the difference calculation unit 108. By this notification, when the sequence number abnormality is detected, the difference calculation result of the difference calculation unit 108 becomes 0, and the timing information data becomes invalid.

  Next, the clock synchronization operation of the clock synchronization system of this embodiment will be described.

(1) Operation of transmitting apparatus 2:
FIG. 5 shows a procedure of the timing information transmission operation in the transmission apparatus 2. When the transmission device 2 is activated, first, the count time of the timing counter 201 is set (step S10). The count time is a constant that determines the transmission interval of timing information, and is 10 seconds here. After setting the count time, the timing counter 201 starts counting with the reference clock supplied from the reference oscillator 301 (step S11), and before the data generation unit 202 is notified of the cycle timing from the timing counter 201, the timing information Is generated. The timing information generated by the data generation unit 202 is sequence number data and timing interval data in the transmission data 401 shown in FIG. The sequence number data in the transmission data 401 at this time is “0”, and the timing interval data is a fixed value “10 seconds”.

  When the counting is started, it is determined whether or not the timing counter 201 has timed out (step S13). When 10 seconds elapse from the start of counting and time-out occurs, the timing counter 201 notifies the data generation unit 202 of the cycle timing at the time-out timing, clears the count value, and starts counting again (step S14). . If not timed out, the timing counter 201 continues the count operation until timed out.

  When receiving the notification of the cycle timing from the timing counter 201, the data generation unit 201 transfers the timing information generated in step S12 to the UDP interface 203 to perform data transmission (step S15). In this data transmission, the UDP interface 203 adds a UDP header in which a destination port number for timing information transfer is written. The destination port number for timing information transfer is a unique value determined in advance between the transmission device 2 and the reception device 1. The IP interface 204 adds an IP header in which the IP address of the receiving device is written as the destination IP address and the IP address of the transmitting device is written as the source IP address to the data transferred from the UDP interface 203. Then, the ETHER interface 205 sends the data generated by the IP interface 204 onto the IP network 302.

  After the data transmission, the data generation unit 201 determines whether or not the order number x of the timing information of the transmitted data has become n (here, n = 5 is assumed) (step S16). If the determination is “No”, the data generation unit 201 increases the value of the sequence number x by “1” and generates the next timing information in step S12. If “Yes”, the data generation unit 201 sets the value of the sequence number x to “0” and generates the next timing information in step S12.

  According to the timing information transmission operation described above, the transmission device 2 transmits timing information data every 10 seconds. The sequence number data included in the timing information is “0” at the time of the first transmission, and is incremented by one for each transmission. After becoming “5”, it is cleared to “0” and again. It increases by 1 for each transmission. Therefore, the receiving side can confirm whether or not the timing information is received in the correct order by referring to the sequence number data.

(2) Operation of receiving apparatus 1:
(2-a) First, a series of clock synchronization operations in the receiving apparatus 1 will be described. FIG. 6 shows a procedure of the clock synchronization operation of the receiving device 1. In the receiving device 1, when timing information data is received (step S20), timing information is extracted from the received data (step S21). In this timing information extraction, first, the IP interface 102 compares the IP address of the IP header of the data received by the ETHER interface 101. When the destination IP address is the IP address of the receiving device 1 and the source IP address matches the IP address of the transmitting device 2, the IP interface 102 transfers the received data to the UDP interface 103. The UDP interface 103 checks whether or not the destination port number in the UDP header of the received data transferred from the IP interface 102 matches the number (unique value) assigned for timing information transfer. The timing counter 104 is notified that the information has been detected, and the received data is transferred to the data extraction unit 106.

  The timing counter 104 continues the counting operation from the time when the previous timing information was received, and when receiving the data reception detection notification from the UDP interface 103, the count value Cy at the time of receiving the notification is sent to the counter data latch unit 105. After latching, the count value is cleared and counting is started again (step S22). In parallel with this, the number of the sequence number data included in the timing information of the reception data transferred from the UDP interface 103 by the data extraction unit 106 is included in the timing information of the previous reception data. It is confirmed whether or not the number is a number obtained by adding 1 to the number of the sequence number data, that is, whether or not the timing information is received in a normal sequence (step S23).

  If there is no omission or replacement in the number of the sequence number data and it is determined as “normal” in step S23, the data extraction unit 106 transmits from the timing interval data included in the timing information of the current reception data. The expected value calculation unit 107 is notified that the transmission timing interval of the device 2 is 10 seconds, and the expected value calculation unit 107 calculates the theoretical count value Cx based on the notification (step S24). Specifically, when it is assumed that the timing counter 104 counts 10,000 per second when the frequency of the output clock of the frequency divider 112 is equal to the frequency of the reference clock supplied from the reference oscillator 301, the expected value The calculation unit 107 assumes that the transmission timing interval of the transmission apparatus 1 is 10 seconds and that the timing counter 104 counts 10,000 per second, and the timing counter 104 of the timing counter 104 when the reception data interval is 10 seconds. “100,000” is calculated as the theoretical count value.

  On the other hand, if the number of the sequence number data is missing or replaced, and if it is determined as “abnormal” in step S23, the data extraction unit 106 uses the counter value as the theoretical count value Cx as a counter. Notification is made to output the same value as the count value Cy latched by the data latch unit 105 to the difference calculation unit 108 (step S25).

  When the count value Cy latched from the counter data latch unit 105 is supplied in step S22 and the theoretical count value Cx is supplied from the expected value calculation unit 107 in step S24 or S25, the difference calculation unit 108 counts. A value obtained by subtracting the theoretical count value Cx from the value Cy is calculated (step S26). Then, the error determination unit 109 cumulatively adds the calculation results of the difference calculation unit 108 (step S27) and checks whether the cumulative addition result is within a predetermined upper limit value and lower limit value threshold range (step S27). Step S28).

  When the cumulative addition result exceeds the upper limit value in step S28, the error determination unit 109 controls to reduce the frequency of the VCXO 111 (step S29). On the other hand, when the cumulative addition result falls below the lower limit value in step S28, the error determination unit 109 controls to increase the frequency of the VCXO 111 (step S30). In other cases, that is, when the cumulative addition result is within the threshold range, the error determination unit 109 does not perform frequency control of the VCXO 111 (step S31). After any one of steps S29 to S31 is performed, the process returns to step S20 to receive data.

  (2-b) Next, the relationship between the count value of the timing counter 104 and the theoretical count value of the expected value calculation unit 107 will be specifically described with reference to FIG.

  In FIG. 7, transmission timings A0, A1, A2, A3, and A4 are timings at which the transmission apparatus 2 transmits timing information, and the timing interval is 10 seconds. Reception timings B0, B1, B2, B3, and B4 are timings at which the reception device 2 receives timing information transmitted by the transmission device 2 via the IP network 302, and transmission timings A0, A1, A2, and A3, respectively. This corresponds to the reception timing of the timing information transmitted in A4. Since the transfer delay of the IP network 302 is not uniform depending on traffic conditions or the like, there are variations (fluctuations). For this reason, each interval of the reception timings B0, B1, B2, B3, and B4 is a transmission interval of timing information. There is a deviation corresponding to the fluctuation in transfer delay with respect to seconds. Specifically, the intervals of the reception timings B0 and B1 and the intervals of the reception timings B3 and B4 are both longer than 10 seconds, but the intervals of the reception timings B1 and B2 and the intervals of the reception timings B2 and B3 are Both are shorter than 10 seconds.

  In the example shown in FIG. 7, the timing counter 104 clears the count value at the reception timing B0 and counts the interval until the next reception timing B1. At the reception timing B1, the count value of the timing counter 104 is latched by the counter data latch unit 105. The expected value calculation unit 107 uses the count value at the timing C1 10 seconds after the reception timing B0, that is, the count value of the timing counter 104 when the count operation is performed with a clock whose frequency is equal to the frequency of the reference clock as the theoretical count value. . The difference calculation unit 108 obtains a difference value D1 obtained by subtracting the theoretical count value calculated by the expected value calculation unit 107 from the count value latched by the counter data latch unit 105. In this case, since the interval between the reception timings B0 and B1 is longer than 10 seconds, the difference value D1 is a positive value. The error determination unit 109 determines whether or not the difference value D1 is within the threshold range of the upper limit value and the lower limit value, and performs frequency control of the VCXO 111 in any one of steps S29 to S31 in FIG. 6 according to the determination result. Do.

  Subsequently, the timing counter 104 clears the count value at the reception timing B1 and counts the interval until the next reception timing B2. At the reception timing B2, the count value of the timing counter 104 is latched by the counter data latch unit 105. The expected value calculation unit 107 uses the count value at the timing C2 10 seconds after the reception timing B1, that is, the count value of the timing counter 104 when the count operation is performed with a clock whose frequency is equal to the frequency of the reference clock as the theoretical count value. . The difference calculation unit 108 obtains a difference value D2 obtained by subtracting the theoretical count value calculated by the expected value calculation unit 107 from the count value latched by the counter data latch unit 105. In this case, since the interval between the reception timings B1 and B2 is shorter than 10 seconds, the difference value D2 is a negative value. The error determination unit 109 cumulatively adds the difference value D2 calculated in this way to the difference value D1, and performs frequency control of the VCXO 111 in any one of steps S29 to S31 in FIG. 6 according to the addition result.

  In the same procedure as described above, the difference value D3 is calculated between the reception timings B2 and B3, and the difference value D4 is calculated and cumulatively added between the reception timings B3 and B4. Depending on the addition result, the steps of FIG. The frequency control of the VCXO 111 in any one of S29 to S31 is performed. Even after the reception timing B4, the frequency control of the VCXO 111 is performed based on the similar calculation of the difference value and the cumulative addition result.

  (2-c) Next, the frequency control of the VCXO 111 based on the cumulative addition result of difference values will be described in detail.

  FIG. 8 shows a specific configuration of the error determination unit 109 shown in FIG. Referring to FIG. 8, the error determination unit 109 includes an addition circuit 501, an absolute value comparison circuit 502, a sign determination circuit 503, a selector circuit 504, and an addition circuit 505.

  The adder circuit 501 adds the output value of the difference calculation unit 108 and the previous addition result. The absolute value comparison circuit 502 compares the result cumulatively added by the addition circuit 501 with the upper limit value and the lower limit value set in advance, and notifies the selector circuit 504 of the comparison result. Here, it is assumed that the absolute values of the upper limit value and the lower limit value are the same, the values are variable, and can be set freely from the outside. The sign determination circuit 503 performs sign determination as to whether the result of the cumulative addition by the addition circuit 501 is a positive value or a negative value, and notifies the selector circuit 504 of the determination result.

  The selector circuit 504 selects and outputs one control value from among the three digital values “+1”, “−1”, and “0”. The selection is made from the absolute value comparison circuit 502. The comparison result and the determination result from the sign determination circuit 503 are performed. Specifically, as a comparison result from the absolute value comparison circuit 502, it is notified that the cumulative addition result has exceeded the upper limit value (= the absolute value of the lower limit value), and a positive value as the determination result from the sign determination circuit 503 Is notified, the selector circuit 504 selects and outputs “−1” as the control value. Further, as a comparison result from the absolute value comparison circuit 502, it is notified that the cumulative addition result has exceeded the upper limit value (= the absolute value of the lower limit value), and the determination result from the sign determination circuit 503 is a negative value. Is notified, the selector circuit 504 selectively outputs “+1” as the control value. When it is notified from the absolute value comparison circuit 502 that the cumulative addition result is within the upper limit value (= the absolute value of the lower limit value), the selector circuit 504 selects and outputs “0” as the control value. .

  The adder circuit 505 supplies a digital value as an output to the VCXO 111 via the D / A converter 110 as a control voltage. The adder circuit 505 holds a control value corresponding to the center of the control range of the VCXO 111 as an initial value, and sequentially adds the control value selected by the selector circuit 504 to the held value.

  In the error determination unit 109 configured as described above, when the result of cumulative addition by the addition circuit 501 exceeds a preset upper limit value, the absolute value comparison circuit 502 causes the cumulative addition result to be an upper limit value (= At the same time, the sign determination circuit 503 notifies the selector circuit 504 of the determination result that the cumulative addition result is a positive value. Then, the selector circuit 504 selects and outputs “−1” as a control value according to the comparison result and the determination result, and the adder circuit 505 adds “−1” to the digital value currently held. As a result, the VCXO 111 is controlled so that the frequency of the output clock is lowered.

  When the result of cumulative addition by the addition circuit 501 falls below a preset lower limit value, the absolute value comparison circuit 502 indicates that the cumulative addition result has exceeded the upper limit value (= the absolute value of the lower limit value). Is simultaneously notified to the selector circuit 504, and the sign determination circuit 503 notifies the selector circuit 504 of a determination result that the cumulative addition result is a negative value. Then, the selector circuit 504 selects and outputs “+1” as the control value according to the comparison result and the determination result, and the addition circuit 505 adds “+1” to the digital value currently held. As a result, the VCXO 111 is controlled so that the frequency of the output clock increases.

  If the result of cumulative addition by the addition circuit 501 is within the preset upper limit value and lower limit threshold range, the absolute value comparison circuit 502 determines that the cumulative addition result is the upper limit value (= the absolute value of the lower limit value). At the same time, the sign determination circuit 503 notifies the selector circuit 504 of the comparison result indicating that the following is true, and the sign determination result of the cumulative addition result (the sign in this case takes either “positive” or “negative”) Is sent to the selector circuit 504. Then, the selector circuit 504 selects and outputs “0” as the control value according to the comparison result and the determination result, and the adder circuit 505 adds “0” to the digital value currently held. As a result, the VCXO 111 is controlled to maintain the current state.

  Hereinafter, the control operation by the error determination unit 109 will be described with a specific example.

  Assume that the adding circuit 501 sequentially adds the difference values D1, D2, D3, and D4 shown in FIG. Here, the reception timing Bx of certain timing information adds a transfer delay of the IP network 302 to the transmission timing Ax, but is always between the maximum delay time and the minimum delay time of the IP network 302. For this reason, the magnitude of the difference value Dx does not become larger than a value corresponding to the difference between the maximum delay time and the minimum delay time.

  FIG. 9 schematically shows a change in the value obtained by cumulatively adding the difference values D1 to D4 shown in FIG. The reception timings B1 to B4 are all between the maximum delay time T2 and the minimum delay time T1. The result of cumulative addition with the sign added to the difference value Dx is a value within ± (T2−T1). For example, assuming that the maximum delay time T2 of the IP network 302 is 6 seconds and the minimum delay time T1 is 1 second, the accumulated addition value of the adder circuit 501 is a value of ± 50000 or less corresponding to ± 5 seconds.

  FIG. 10 shows an operation example when the timing counter 104 shown in FIG. 1 performs a counting operation with an ideal precision clock. In this example, it is assumed that the difference values D1 to D4 shown in FIG. 7 have the following values.

D1 = + 4000 (+0.4 seconds)
D2 = −3000 (−0.3 seconds)
D3 = −4000 (−0.4 seconds)
D4 = + 3000 (+0.3 seconds)
In the above case, the cumulative addition value is “+4000” at the time of reception timing B1, “+1000” at the time of reception timing B2, “−3000” at the time of reception timing B3, and “0” at the time of reception timing B4. Become.

  However, when the frequency of the output clock of the VCXO 111 is higher than the frequency of the reference clock, the timing counter 104 counts more than when operating with an ideal frequency (matching the frequency of the reference clock). Become. FIG. 11 shows an operation example in the case where the timing counter 104 counts 100 more each time than the example shown in FIG. In this example, the difference values D1 to D4 shown in FIG. 7 take the following values.

D1 = + 4100 (+0.41 second)
D2 = -2900 (-0.29 seconds)
D3 = −3900 (−0.39 seconds)
D4 = + 3100 (+0.31 seconds)
In the above case, the cumulative addition value is “+4100” at the time of reception timing B1, “+1200” at the time of reception timing B2, “−2700” at the time of reception timing B3, and “+400” at the time of reception timing B4. Become. When such a change in the cumulative addition value continues, the cumulative addition value of the addition circuit 501 continues to increase, and exceeds the upper limit of +50000 at a certain reception timing. The absolute value comparison circuit 502 sets the absolute values of the upper limit value and the lower limit value to 50000, and notifies the selector circuit 504 that the cumulative addition value has exceeded the threshold value of 50000. At the same time, the sign determination circuit 503 notifies the selector circuit 504 that the sign of the accumulated addition value is positive. Then, the selector circuit 504 selects a control value for adding “−1” to the digital value of the D / A converter 110.

  On the other hand, when the frequency of the VCXO 111 is lower than the frequency of the reference clock, the timing counter 104 counts a smaller number than when operating with an ideal frequency (matching the frequency of the reference clock). FIG. 12 shows an operation example when the timing counter 104 counts down by 100 each time compared to the example shown in FIG. In this example, the difference values D1 to D4 shown in FIG. 7 take the following values.

D1 = + 3900 (+0.39 seconds)
D2 = -3100 (-0.31 second)
D3 = -4100 (-0.41 second)
D4 = + 2900 (+0.29 seconds).

  In the above case, the cumulative addition value is “+3900” at the time of reception timing B1, “+800” at the time of reception timing B2, “−3800” at the time of reception timing B3, and “−400” at the time of reception timing B4. It becomes. If such a change in the cumulative addition value continues, the cumulative addition value of the addition circuit 501 continues to decrease, and falls below −50000, which is the premise of the lower limit, at a certain reception timing. The absolute value comparison circuit 502 sets the absolute values of the upper limit value and the lower limit value to 50000, and notifies the selector circuit 504 that the cumulative addition value has exceeded the threshold value of 50000. At the same time, the sign determination circuit 503 notifies the selector circuit 504 that the sign of the cumulative addition value is negative. Then, the selector circuit 504 selects a control value for adding “+1” to the digital value of the D / A converter 110.

  As described above, according to the clock synchronization system of the present embodiment, the receiving apparatus 1 determines the frequency accuracy error of the VCXO 111 in itself by repeating reception of timing information. If the frequency of the VCXO 111 is lower than the frequency of the reference clock, the output voltage of the D / A converter 110 is increased to increase the frequency of the VCXO 111. Conversely, if the frequency of the VCXO 111 is higher than the frequency of the reference clock, The output voltage of the D / A converter 110 is lowered to lower the frequency of the VCXO 111. When performing such control, for example, when the timing counter 104 counts 10 seconds, which is the transmission interval of timing information, with a clock having an ideal frequency (matching the frequency of the reference clock), it is “100000”. When the stable state of the IP network 302 continues for a long time, the frequency of the VCXO 111 of the receiving device 1 can be adjusted with an accuracy of 10 ppm with respect to the reference clock of the transmitting device 2.

  In addition, when the sequence number of the timing information has an abnormality in continuity such as “• 2, 4, 3, 5, 0, 1, 2,...”, The data extraction unit 106 detects that. The expected value calculation unit 107 is notified not to perform the normal calculation of the theoretical count value, but to use the same value as the count value latched by the counter data latch unit 105 as the theoretical count value. As a result, for the received data of sequence numbers 4, 3, and 5, the expected value calculation unit 107 supplies the same value as the count value latched by the counter data latch unit 105 as the theoretical count value to the difference calculation unit 108. Will be output. As a result, the difference value of the difference calculation unit 108 becomes 0, and the received data with the sequence numbers 4, 3, and 5 become invalid.

  In addition, when the receiving device 1 is activated, since the count value of the timing counter 104 has no meaning in the first received data, the data extraction unit 106 sets the counter data latch unit 105 to the expected value calculation unit 107. To notify that the count value is the same as the latched count value. As a result, the difference value of the first difference calculation unit 108 becomes 0, and the first received data becomes invalid.

(Other embodiments)
FIG. 13 is a block diagram showing a configuration of a main part of a receiving apparatus used in a clock synchronization system according to another embodiment of the present invention. This receiving apparatus is used in the system shown in FIG. 3, and in the configuration of the receiving apparatus 1 shown in FIG. 1, the difference calculation unit 108 is removed, and a timing down counter 604 is used instead of the timing counter 104. It is provided. In the present embodiment, by setting the theoretical count value of the expected value calculation unit 107 as the initial value of the timing down counter 604, a configuration in which the difference calculation unit 108 of FIG. 1 is unnecessary is realized.

  The timing down counter 604 is constituted by a well-known down counter, and the result of the calculation of the theoretical count value from the received data by the expected value calculation unit 107 is set as a counter initial value, which is set until the next reception timing. Count down from the initial value. When the down count is larger than the initial value, the count value is expressed as a negative value. When the timing down counter 604 receives notification of timing information detection from the UDP interface 103, the timing down counter 604 causes the counter data latch unit 105 to latch the count value at that time, and sets the theoretical value of the expected value calculation unit 107 as an initial value. And continue down-counting. The value latched by the counter data latch unit 105 is equal to the value obtained by subtracting the count value of the reception data interval from the theoretical value of the expected value calculation unit 107.

  The error determination unit 109 cumulatively adds the values latched by the counter data latch unit 105. When the frequency of the VCXO 111 is higher than the frequency of the reference clock, the timing down counter 604 counts more than when counting with the clock of the ideal frequency (matching the frequency of the reference clock), so the cumulative addition result is negative. Increases as the value of. On the other hand, when the frequency of the VCXO 111 is lower than the frequency of the reference clock, the timing down counter 604 counts a little compared to the case of counting with the clock of the ideal frequency (matching the frequency of the reference clock), so the cumulative addition The result grows as a positive value. This relationship is opposite to the case of the receiving device 1 shown in FIG. Therefore, in the present embodiment, the error determination unit 109 selects the control for adding “−1” to the digital value to the D / A converter 110 when the cumulative addition value is below the lower limit value, and the cumulative addition value. When the value exceeds the upper limit value, control for adding “+1” to the digital value to the D / A converter 110 is selected.

  As described above, the receiving apparatus according to the present embodiment determines the frequency accuracy error of the VCXO 111 in the own apparatus by repeating reception of timing information. If the frequency of the VCXO 111 is lower than the frequency of the reference clock, D / The output voltage of the A converter 110 is lowered to lower the frequency of the VCXO 111. Conversely, when the frequency of the VCXO 111 is higher than the frequency of the reference clock, the output voltage of the D / A converter 110 is increased to increase the frequency of the VCXO 111. To do.

  If an abnormality is detected in the continuity of the sequence numbers of the timing information, the data extraction unit 106 notifies the counter data latch unit 105 to set the latch data to 0 and invalidates the received data.

  In the clock synchronization system of each embodiment described above, the transmission device 2 may be a computer device represented by a server, for example, and the reception device 1 is a computer device represented by a personal computer, for example. Also good.

  In addition, one transmitter and a plurality of receivers 1 may be connected via a network, and each receiver 1 may execute the operations described in the above-described embodiments.

  Further, the transmission apparatus 2 transmits timing information at a time interval larger than the maximum transfer delay time of the IP network 302, and the threshold value of the error determination unit of the reception apparatus 1 is set according to the maximum delay deviation of the IP network 302. May be. With such a configuration, it is possible to determine the clock accuracy error of the receiving apparatus 1 that flexibly corresponds to the transfer characteristics of the IP network 302.

  Further, the transmission device 2 generates and transmits timing information at a short transmission interval (first transmission interval) for a certain period after the start of communication with the reception device 1, and thereafter, a long transmission interval (second transmission interval). Timing information) may be generated and transmitted. With this configuration, the receiving device 1 can adjust the frequency more quickly in the first fixed period. In addition, after the frequency has been sufficiently adjusted, the transmission interval can be lengthened and the timing information can be transmitted efficiently.

It is a block diagram which shows the principal part of the receiver which comprises the clock synchronous system which is one Embodiment of this invention. It is a block diagram which shows the principal part of the transmitter which comprises the clock synchronization system which is one Embodiment of this invention. 1 is a block diagram illustrating an overall configuration of a clock synchronization system according to an embodiment of the present invention. It is a schematic diagram which shows the example of a format of the transmission data used in the clock synchronous system which is one Embodiment of this invention. 3 is a flowchart for explaining the operation of the transmission device shown in FIG. 2. 3 is a flowchart for explaining the operation of the receiving apparatus shown in FIG. 1. It is a figure for demonstrating the relationship between the count value and the count theoretical value in the receiver shown in FIG. It is a block diagram which shows the specific structure of the error determination part shown in FIG. It is a schematic diagram which shows the change of the cumulative addition value of the difference values D1-D4 shown in FIG. It is a figure which shows the change of the cumulative addition value of difference value D1-D4 shown in FIG. 7 at the time of measuring the timing information reception interval with the clock of an ideal frequency. It is a figure which shows the change of the cumulative addition value of difference value D1-D4 shown in FIG. 7 at the time of measuring the timing information reception interval with a clock faster than an ideal frequency. It is a figure which shows the change of the cumulative addition value of difference value D1-D4 shown in FIG. 7 at the time of timing reception of timing information with a clock slower than an ideal frequency. It is a block diagram which shows the structure of the principal part of the receiver used for the clock synchronization system which is other embodiment of this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Reception apparatus 2 Transmission apparatus 101,205 ETHER interface 102,204 IP interface 103,203 UDP interface 104,201,604 Timing counter 105 Counter data latch part 106 Data extraction part 107 Expected value calculation part 108 Difference calculation part 109 Error determination part 110 D / A converter 111 VCXO
112 Frequency Divider 202 Data Generation Unit 301 Reference Oscillator 302 IP Network 401 Transmission Data 501 and 505 Adder Circuit 502 Absolute Value Comparison Circuit 503 Code Determination Circuit 504 Selector Circuit

Claims (17)

A transmission device that transmits timing information including at least information on the predetermined transmission interval at a predetermined transmission interval based on a reference clock;
A receiving device for receiving the timing information via a network;
The receiving device is:
An oscillator in which the frequency of the output clock changes according to the magnitude of the input control voltage;
Clocking means for clocking the reception interval of the timing information based on an internal clock obtained from the output of the oscillator;
An expected value calculation unit that calculates a value when the timekeeping means measures a transmission interval included in the timing information in an ideal state where the frequency of the internal clock matches the frequency of the reference clock;
Each time the reception interval is timed by the time measuring means, the difference between the timed value and the theoretical value calculated by the expected value calculation unit is obtained and cumulatively added. And an error determination unit that controls the magnitude of the control voltage so that the frequency of the internal clock approaches the frequency of the reference clock when the frequency falls outside the threshold range. The timing means is
When the timing information is received, the count value held so far is cleared, and a timing counter that counts an interval from the reception of the timing information to the reception of the next timing information based on the internal clock,
A latch circuit that holds a count value immediately before the timing counter is cleared;
The error determination unit obtains and cumulatively adds a difference between a count value held in the latch circuit and a theoretical value calculated by the expected value calculation unit every time the timing information is received. The clock synchronization system according to 1. The timing information further includes a sequence number indicating what number the transmitted information is,
The receiving device further includes a data extraction unit that, when receiving the timing information, determines a continuity based on a sequence number included in the received timing information,
When the data extracting unit determines that the continuity is abnormal, the value held in the latch circuit is forcibly set as a theoretical value calculated by the expected value calculating unit. the clock synchronization system as set forth in 2. The timing means is
When the timing information is received, the theoretical value calculated by the expected value calculation unit is set as an initial value, and the interval from the reception of the timing information to the reception of the next timing information is based on the internal clock. The timing down counter to count down,
A latch circuit that holds a count value immediately before the initial value of the timing down counter is set,
The error determination unit obtains and cumulatively adds a difference between a count value held in the latch circuit and a theoretical value calculated by the expected value calculation unit every time the timing information is received. The clock synchronization system according to 1. The timing information further includes a sequence number indicating what number the transmitted information is,
The receiving device further includes a data extraction unit that, when receiving the timing information, determines a continuity based on a sequence number included in the received timing information,
5. The clock synchronization system according to claim 4, wherein, when the data extraction unit determines that the continuity is abnormal, the count value held in the latch circuit is forcibly set to 0. 6. The transmission device generates and transmits the timing information at a first transmission interval as the predetermined transmission interval for a certain period after the start of communication with the reception device, and thereafter, the first transmission interval. longer second generates the timing information in the transmission interval transmits, clock synchronization system according to any one of claims 1 to 5. A receiving device that receives timing information including information on at least the predetermined transmission interval, which is transmitted by the transmitting device at a predetermined transmission interval based on a reference clock, via a network;
An oscillator in which the frequency of the output clock changes according to the magnitude of the input control voltage;
Clocking means for clocking the reception interval of the timing information based on an internal clock obtained from the output of the oscillator;
An expected value calculation unit that calculates a theoretical value as a value when the time measuring unit measures a transmission interval included in the timing information in an ideal state where the frequency of the internal clock matches the frequency of the reference clock;
Each time the reception interval is timed by the time measuring means, the difference between the timed value and the theoretical value calculated by the expected value calculation unit is obtained and cumulatively added. And an error determination unit that controls the magnitude of the control voltage so that the frequency of the internal clock approaches the frequency of the reference clock when the frequency falls outside the threshold range. The timing means is
When the timing information is received, the count value held so far is cleared, and a timing counter that counts an interval from the reception of the timing information to the reception of the next timing information based on the internal clock,
A latch circuit that holds a count value immediately before the timing counter is cleared;
The error determination unit obtains and cumulatively adds a difference between a count value held in the latch circuit and a theoretical value calculated by the expected value calculation unit every time the timing information is received. 8. The receiving device according to 7 . The timing information further includes a sequence number indicating what number the transmitted information is,
When receiving the timing information, further comprising a data extraction unit for determining the continuity based on the sequence number included in the received timing information,
When the data extracting unit determines that the continuity is abnormal, the value held in the latch circuit is forcibly set as a theoretical value calculated by the expected value calculating unit. 9. The receiving device according to 8 . The timing means is
When the timing information is received, the theoretical value calculated by the expected value calculation unit is set as an initial value, and the interval from the reception of the timing information to the reception of the next timing information is based on the internal clock. The timing down counter to count down,
A latch circuit that holds a count value immediately before the initial value of the timing down counter is set,
The error determination unit obtains and cumulatively adds a difference between a count value held in the latch circuit and a theoretical value calculated by the expected value calculation unit every time the timing information is received. 8. The receiving device according to 7 . The timing information further includes a sequence number indicating what number the transmitted information is,
When receiving the timing information, further comprising a data extraction unit for determining the continuity based on the sequence number included in the received timing information,
The receiving device according to claim 10 , wherein when the data extracting unit determines that the continuity is abnormal, the count value held in the latch circuit is forcibly set to zero. A transmission device that transmits timing information for clock synchronization to a reception device connected via a network,
A timing counter for generating a periodic timing for transmitting the timing information at a predetermined transmission interval based on a reference clock supplied from the outside;
A data generation unit that generates data including information on the predetermined transmission interval and a sequence number indicating a transmission order based on the cycle timing, and transmits the data as the timing information,
The data generation unit generates and transmits the timing information at a first transmission interval as the predetermined transmission interval for a certain period after the start of communication with the receiving device, and thereafter, the first transmission feeding a long second transmission interval than the interval you sent to generate the timing information communication apparatus. A clock synchronization method performed in a communication system in which a transmission device and a reception device are connected via a network,
A first step in which the transmitting device transmits timing information including at least information on the predetermined transmission interval to the receiving device at a predetermined transmission interval based on a reference clock;
Each time the receiving device receives the timing information, a count value obtained by counting the interval from the reception of the previous timing information to the reception of the current timing information with its own clock, and the frequency of the own clock is the reference Accumulated addition by calculating the difference from the theoretical value that is the value when counting the predetermined transmission interval included in the received timing information based on the own clock in an ideal state that matches the frequency of the clock And a second step of adjusting the frequency of the own clock in a direction approaching the frequency of the reference clock when the accumulated addition value is out of a predetermined threshold range. The timing information further includes a sequence number indicating what number the transmitted information is,
When the receiving device receives the timing information, it determines the continuity based on the sequence number included in the received timing information, and if the determination becomes abnormal, the received timing information The clock synchronization method according to claim 13 , further comprising forcibly setting the calculated difference to zero. In the first step, the transmission device generates and transmits the timing information at the first transmission interval as the predetermined transmission interval for a certain period after the start of communication with the reception device, and thereafter , comprising the step of generating and transmitting the timing information in the long second transmission interval than the first transmission interval, the clock synchronization method of claim 13 or 14. A clock frequency error determination method performed in a receiving device that receives timing information including information on at least the predetermined transmission interval, which is transmitted by the transmitting device at a predetermined transmission interval based on a reference clock, via a network,
Counting the timing information reception interval with its own clock;
A theoretical value which is a value when the predetermined transmission interval included in the timing information is counted based on the own clock in an ideal state where the frequency of the own clock matches the frequency of the reference clock. A step of calculating;
Each time the count value of the reception interval is obtained, a step of obtaining a difference between the obtained count value and the theoretical value and accumulating the difference;
And determining a frequency error of the own clock with respect to the reference clock based on whether or not the accumulated value is out of a predetermined threshold range. The timing information further includes a sequence number indicating what number the transmitted information is,
When the timing information is received, the continuity is determined based on the sequence number included in the received timing information, and when the determination becomes abnormal, the difference calculated for the received timing information is calculated. The clock frequency error determination method according to claim 16 , further comprising: forcibly setting to zero.

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