JP3630601B2 - IP terminal device, frequency error range estimation method, frequency difference estimation method, and estimated required time calculation method - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a terminal device (hereinafter referred to as “IP terminal device”) connected to an Internet protocol network (hereinafter referred to as “IP network”) and a frequency error range estimation method suitable for application to the IP terminal device. The present invention relates to a frequency difference estimation method and an estimated required time calculation method.
[0002]
[Prior art]
Currently, a real-time transmission service of voice data via an IP network, a so-called Internet telephone service is in operation. Various connection forms such as communication between personal computers connected to the IP network and communication between telephones via the IP network are conceivable as connection forms of this service.
[0003]
By the way, in an IP terminal device used for such communication, an error may occur in the transmission clock speed due to the accuracy of the crystal oscillator and other components mounted on each device between the transmission side and the reception side. There is. However, this error is not taken into consideration in the conventional apparatus. For this reason, when a surplus or deficiency of data due to an error in the clock speed actually occurs, the receiving side IP terminal apparatus performs processing for discarding the voice data corresponding to the surplus or inserting alternative data corresponding to the deficiency. Do.
[0004]
However, when such processing is executed, the identity of the content is lost between the original data and the data after discarding or insertion (the waveform that is actually reproduced as sound), and the sound quality is reduced. May decrease. Further, when the data after such processing is demodulated by the modem, there is a risk that the data will be demodulated into an analog waveform that is completely different from the original waveform, and there is a problem that communication through the modem cannot be realized.
[0005]
Therefore, in the conventional apparatus, a synchronization packet is transmitted at a fixed period from a transmission-side IP terminal apparatus serving as a master terminal (terminal serving as a clock reference), and a slave terminal (terminal synchronized with the master clock) is used. It is conceivable to apply the method of gradually adjusting the clock of the slave terminal to the clock of the master terminal by making it receive at the receiving IP terminal device, and determining whether the clock is delayed or advanced at each reception. .
[0006]
[Problems to be solved by the invention]
However, the above-described method has a drawback that it is inevitable that the time required for the adjustment to be completed varies depending on the magnitude of the frequency deviation at the start of the clock synchronization adjustment. That is, there is a drawback that the time required from the start of adjustment to completion cannot be uniquely determined due to variations in the time required to complete clock alignment. For this reason, there is a problem that it is not possible to clarify the specifications as an IP terminal device (for example, how long after the device is started up, synchronization should have been established, and so on). was there.
[0007]
[Means for Solving the Problems]
(A) In order to solve such a problem, in the first invention, the synchronization that receives the synchronization timing packet transmitted by another IP terminal device at a constant interval and synchronizes the internally generated clock with the clock on the transmission side. In an IP terminal device having a function, (1) a clock generating means for generating an internal clock, (2) a clock counter for counting the internal clock generated by the clock generating means, and (3) first received after communication is started Based on the difference between the count value of the clock counter at the time of reception of the synchronization timing packet and the count value of the clock counter at the time of reception of the synchronization timing packet received thereafter, the clock on the transmission side and the clock generated by the clock generation means A control means for estimating a frequency difference between the clock generation means and a phase shift control of the clock generation means according to the estimation result; Provided, The control means, each time a synchronization timing packet is received and a new count value difference is calculated, a linear inclination angle that gives an upper limit range of appearance ranges for the difference in count value calculated at each time point And calculating whether the difference between the two inclination angles is within a predetermined error range and calculating the difference between the two inclination angles is within a predetermined error range. The average value of the two inclination angles is regarded as a straight inclination angle corresponding to the frequency difference between the clock on the transmission side to be estimated and the clock generated by the clock generation means, and the clock is calculated based on the inclination angle. To estimate the frequency difference of To.
[0008]
Thus, in the first aspect of the invention, since the clock frequency difference is estimated and the clock synchronization control is performed, the synchronization control is performed based only on the relative phase relationship (whether the frequency is high or low). In comparison, the time required for synchronous control can be estimated.
[0011]
( B ) Also, 2 In this invention, the reception timing of the synchronization timing packet transmitted at regular intervals is detected as the count value of the clock counter that operates with the clock in the receiving device, and the transmission of the synchronization timing packet is performed based on the information of the count value. In the method of estimating the frequency error range when estimating the frequency difference between the side clock and the clock in the receiving device, the count value of the clock counter at the time of reception of the first synchronization timing packet received after the start of communication and thereafter Each time the difference from the count value of the clock counter at the time of receiving the synchronization timing packet received is calculated, the slope of the straight line that gives the upper limit range of the appearance range for the difference in the count value calculated at each time point Calculate the angle and the inclination angle of the straight line that gives the lower limit range. It contains half of the difference between the tilt angle of the frequency difference is an estimated target so as to estimate the range of the frequency error is.
[0012]
( C ) Also, 3 In this invention, the reception timing of the synchronization timing packet transmitted at regular intervals is detected as the count value of the clock counter that operates with the clock in the receiving device, and the transmission of the synchronization timing packet is performed based on the information of the count value. In the frequency difference estimation method for estimating the frequency difference between the side clock and the clock in the receiver, the count value of the clock counter at the time of receiving the synchronization timing packet first received after the start of communication and the synchronization timing received thereafter Whenever the difference from the count value of the clock counter at the time of packet reception is calculated, the slope of the straight line and the lower limit range that gives the upper limit range of the appearance range for the difference in the count value calculated at each time point are given. Calculate the inclination angle of the straight line and estimate the average value of the two inclination angles Clock and on the transmission side is In the receiver The frequency difference of the clock is estimated from the inclination angle by regarding the inclination angle of the straight line corresponding to the frequency difference of the clock.
[0013]
( D ) Also, 4 In the invention of The reception timing of the synchronization timing packet transmitted at regular intervals is detected as the count value of the clock counter that operates with the clock in the receiving device, and the clock and reception side of the synchronization timing packet are received based on the information of the count value A frequency difference estimation method for estimating a frequency difference with a clock in an apparatus, wherein a count value of a clock counter at the time of reception of a synchronization timing packet first received after the start of communication and reception of a synchronization timing packet received thereafter Each time the difference from the count value of the clock counter at the time is calculated, the slope of the straight line that gives the upper limit range of the appearance range and the slope of the straight line that gives the lower limit range for the difference in the count value calculated at each point in time And the average value of the two inclination angles is calculated on the transmitting side In the case considered click and inclination angle of the straight line corresponding to the frequency difference between the clock within the receiver of the frequency difference estimation method for estimating the frequency difference between the clock from the inclined angle, the In the method for calculating the time required for estimating the frequency difference, T1 is the scheduled reception interval of the synchronization timing packet set with reference to the clock in the receiving apparatus, and the scheduled reception interval required until the clock frequency difference is estimated The frequency of the clock on the transmission side of the synchronization timing packet and the clock in the receiving device, where n is the number of N, the target error of the clock frequency difference is W, and the upper limit of the fluctuation appearing on the network is Y difference The required time T1 × n required for estimating T1 × n = Y It is calculated based on / W.
[0014]
DETAILED DESCRIPTION OF THE INVENTION
(A) First embodiment
(A-1) Description of configuration
[0015]
DETAILED DESCRIPTION OF THE INVENTION
(A) First embodiment
(A-1) System configuration
FIG. 1 shows a basic form of a network system according to the first embodiment. FIG. 1 shows a state in which two IP terminal devices 2 and 3 are connected via an IP network 1. Here, for simplicity of explanation, only two IP terminal devices are connected to the IP network. However, the present invention can also be applied to a case where three or more IP terminal devices are connected.
[0016]
FIG. 1 shows a state in which a synchronization master module 4 that functions as a master is mounted on the IP terminal device 2 and a synchronization slave module 5 that functions as a slave is mounted on the IP terminal device 3 with respect to the transmission clock synchronization function. Here, the relationship between the IP terminal device operating as a master and the IP terminal device operating as a slave is fixed.
[0017]
Of course, both the synchronization master module 4 and the synchronization slave module 5 can be mounted on both of the IP terminal apparatuses 2 and 3, but the configuration shown in FIG. 1 will be described here.
[0018]
Note that when both the synchronization master module 4 and the synchronization slave module 5 are mounted on each IP terminal device, which operates as a master and which operates as a slave depends on the agreement. For example, the calling side may operate as a master and the called side may operate as a slave, the calling side may operate as a slave, and the called side may operate as a master. Other arrangements are possible.
[0019]
(A-2) Configuration of each part
Next, the internal configuration of each module will be described.
[0020]
FIG. 2 shows a functional block configuration of the synchronization master module 4. The synchronization master module 4 includes a clock generator 4A, an interrupt generator 4B, a controller 4C, and an IP unit 4D.
[0021]
The clock generator 4A is a reference clock generating means that is composed of a crystal oscillator or the like. The interrupt generator 4B counts the reference clock generated by the clock generator 4A and generates an interrupt signal at a rate of once per fixed number. This interrupt signal is always generated at regular intervals T1 regardless of the operating state of the IP terminal device 3 as the transmission destination.
[0022]
Each time the controller 4C receives an interrupt signal, it outputs synchronization control data. The IP unit 4D is a means for terminating the IP network, packetizes the synchronization control data input at regular intervals T1, and outputs it as a synchronization timing packet. The IP unit 4D is also used for transmission / reception of other data packets.
[0023]
FIG. 3 shows a functional block configuration of the synchronous slave module 5. The synchronous slave module 5 includes an IP unit 5A, a controller 5B, a clock counter 5C, and a transmission clock generator 5D.
[0024]
The IP unit 5A is a means for terminating the IP network, like the master-side IP unit 4D. When receiving the synchronization timing packet, the IP unit 5A outputs this to the controller 5B as synchronization control data.
[0025]
The controller 5B reads and stores the count value Xn of the clock counter 5C every time the synchronization control data is received, and estimates the difference between the clock frequency on the master side and the clock frequency on the slave side on the basis of these values. Means. The controller 5B also functions as a means for obtaining the longest time required for the estimation based on the value of the target error W allowed for the estimation of the frequency difference. Further, the controller 5B controls the transmission clock generator 5D so as to cancel the estimated clock frequency difference after the elapse of the longest time required for the estimation. Details of the control operation by the controller 5B will be described later.
[0026]
The clock counter 5C is a cyclic counter that performs a count-up operation based on the reference clock generated by the transmission clock generator 5D. Here, the maximum value (for example, 39999) of the count value of the clock counter 5C is the time required to count up the value from 0 (constant interval T2) is the synchronization timing packet transmission interval (constant interval T1). It is set to be the same.
[0027]
Therefore, when there is no error between the accuracy of the operation clock of the clock generator 4A of the synchronous master module 4 and the accuracy of the operation clock of the transmission clock generator 5D in the synchronous slave module 5, the clock counter 5C is set to 0 to the maximum. The constant interval T2 required to count up to a value (for example, 39999) coincides with the constant interval T1, and the count value read by the controller 5B is always the same value.
[0028]
The transmission clock generator 5D is on the master side No ku Similar to the lock generator 4A, it is a reference clock generating means composed of a crystal oscillator or the like. The design value of the clock speed is the master side No ku This is the same as the lock generator 4A. The transmission clock generator 5D is configured to change the generated clock speed in accordance with control from the controller 5B.
[0029]
(A-3) Synchronous processing operation
Next, the content of the transmission clock synchronization processing operation performed between the IP terminal apparatuses 2 and 3 equipped with the synchronization modules 4 and 5 having the above configuration will be specifically described.
[0030]
First, regarding the synchronization function of the transmission clock, the IP terminal device 2 on the master side sends out a synchronization timing packet at regular intervals T1 regardless of the operating state of the IP terminal device 3 on the slave side. However, the synchronization timing packet need not always be sent (although it may be sent), and if it is sent only during communication with the slave side, the object of the present invention can be achieved. it can.
[0031]
Needless to say, the constant interval T1 here is determined according to the clock speed output from the clock generator 4A of the synchronization master module 4 mounted in the IP terminal device 2.
[0032]
On the other hand, the IP terminal device 3 on the slave side with respect to the synchronization function of the transmission clock monitors the arrival of the synchronization timing packet in the controller 5B of the synchronization slave module 5, and every time the arrival of the synchronization timing packet is confirmed, The count value Xn of the clock counter 5C is read out.
[0033]
Hereinafter, the count value read first by the IP terminal device 3 that has started communication is X0, and the count value read after the second is Xn (n = 1, 2,...). FIG. 4 shows this correspondence. In FIG. 4, the horizontal axis is the time axis, and the transmission of the synchronization timing packet when there is no fluctuation (a fixed delay may be acceptable) is indicated by a solid line, and the transmission of the synchronization timing packet when there is fluctuation is indicated by a broken line. Represents.
[0034]
The count value X0 is held in the storage means such as a register in the controller 5B until the communication is terminated or the operation of the synchronous slave module 5 is stopped, and is not changed in the middle. .
[0035]
Returning to the description of the operation of the controller 5B. As described above, when the arrival of the synchronization timing packet is confirmed, the controller 5B accesses the clock counter 5C each time and reads the count value at that time.
[0036]
Here, as shown in FIG. 5A, the clock counter 5C counts up from 0 to a predetermined value (for example, 39999) based on the transmission clock supplied from the transmission clock generator 5D in its own device. The operation is performed, and the synchronization timing at a constant interval T2 is obtained by the cyclic count-up operation.
[0037]
Therefore, when the clock frequencies of the master side and the slave side are equal (constant intervals T1 and T2 are equal) and there is no fluctuation on the IP network 1 (constant delay may be acceptable), FIG. As shown in B), the read count value is always the same value.
[0038]
However, even if there is no fluctuation on the IP network 1 (a constant delay may be acceptable), if there is a difference in clock frequency between the master side and the slave side (if the constant intervals T1 and T2 are different), FIG. As shown in (C), a deviation proportional to the frequency difference appears in the read count value.
[0039]
On the other hand, when such a regular deviation in the count value is recognized, the deviation in the clock frequency can be easily specified by confirming the regularity.
[0040]
Actually, however, there is fluctuation in the transmission on the IP network 1, and as shown in FIG. 5D, the count value read out due to the influence is the original regularity determined in accordance with the deviation of the clock frequency (in the figure). It is completely unrelated to a straight line drawn obliquely over a plurality of cyclic periods. For this reason, it is not easy to obtain the original regularity according to the shift of the clock frequency simply by monitoring the difference between the read count values.
[0041]
Therefore, the controller 5B estimates the shift of the clock frequency from a series of count values that seem to be disordered by the following method. In this estimation, the controller 5B sets the upper limit value of the fluctuation on the IP network 1 to Y (the unit is the same as X0 and Xn). Here, a value taken by Xn−X0 (n = 1, 2,...) When there is no fluctuation. Z (N) When Then, the value of Xn−X0 when there is fluctuation is any value of Z (n) −Y ≦ Xn−X0 ≦ Z (n) + Y.
[0042]
When Xn−X0 in the case of this fluctuation is ΔXn, the relationship between time and ΔX is as shown in FIG. Here, the black circles in the figure represent the relative value ΔXn of the count value Xn with respect to the initial value X0 at each read timing. The straight line LA starting from the initial count value X0 connects the series of values that the count value should originally take when there is no fluctuation. The straight line LB starting from the initial count value Y connects a series of maximum allowable values that the count value can take when there is fluctuation. The straight line LC starting from the initial count value -Y connects a series of minimum allowable values that the count value can take when there is fluctuation.
[0043]
Since the range of fluctuations that can occur during communication is Y, the range in which the count value appears in each communication is not the entire range sandwiched between the straight lines LB and LC, but is sandwiched between the straight lines LD and LE represented by diagonal lines in the figure. It will be limited to the range.
[0044]
Therefore, as shown in FIG. 7, the slope of the line segment LF connecting (0, Y) that gives the initial value of the maximum allowable value and each difference value ΔX (n) is always the slope of the straight line LB (that is, the straight line LA). The slope of the line segment LG connecting (0, -Y) that gives the initial value of the minimum allowable value and each difference value ΔX (n) is the slope of the straight line LC ( That is, a relationship larger than the slope of the straight line LA) is recognized.
[0045]
Therefore, the controller 5B in the present embodiment, every time a new difference value ΔX (n) is calculated, the line segment connecting (0, Y) that gives the initial value of the maximum allowable value and each difference value ΔX (n). The LF having a larger slope is selected and the slope of the line segment LG connecting (0, -Y) that gives the initial value of the minimum allowable value and each difference value ΔX (n) is selected. A smaller one is selected, and a process for narrowing the range in which the slope of the straight line LA that is truly desired can exist.
[0046]
That is, as shown in FIG. 8 → FIG. 9 → FIG. 10 → FIG. 11 → FIG. 12 → FIG. 7, the controller 5B narrows the difference between the slopes of the two types of line segments LF and LG, A process of narrowing the range in which the inclination can exist is performed.
[0047]
Eventually, when the difference between the slope of the line segment LF and the slope of the LG is reduced and the difference falls within a predetermined error range, the controller 5B sets the average of the slopes of both line segments to the slope corresponding to the difference in clock frequency. It is estimated that Naturally, the accuracy of the estimated value can be increased by narrowing a predetermined error range.
[0048]
Actually, the above processing is performed by the following calculation operation. That is, every time the reception of the synchronization timing packet is notified, the controller 5B calculates two kinds of gradients K1 and K2 given by the following equations (1) and (2), respectively, A slope smaller than the slope obtained by the above calculation is selected, and a slope larger than the slope obtained by the past computation is selected for the latter.
[0049]
K1 = {(Xn−X0) + Y} / (T1 × n) ... (1)
K2 = {(Xn−X0) −Y} / (T1 × n) ... (2)
Here, n is an integer value of 1, 2,. Further, the slope K1 represented by the equation (1) is the slope of the line segment LG in FIGS. 7 to 12, and the slope K2 represented by the formula (2) is the slope of the line segment LF in FIGS. Equivalent to.
[0050]
For example, when the value of the slope K1 held so far is 50 and the value of the newly calculated slope K1 is 40, the controller 5B selects the newly calculated value of 40 as the value of the slope K1. To do. On the other hand, when the value of the gradient K2 that has been held so far is 20 and the value of the newly calculated gradient K2 is 10, the controller 5B retains the value 20 as the value of the gradient K2.
[0051]
By repeating such a series of calculation processes, the difference between the slopes K1 and K2 is gradually reduced (as shown in FIG. 8 → FIG. 9 → FIG. 10 → FIG. 11 → FIG. 12 → FIG. 7). Eventually, the two slopes will almost coincide.
[0052]
However, in reality, it is necessary to obtain a difference in clock frequency within a limited time, and to eliminate the difference existing between the transmission clock on the master side and the transmission clock on the slave side based on the difference value. Therefore, every time the values of the gradients K1 and K2 are updated, the controller 5B obtains the current error range by the following equation and determines whether the value is equal to or less than a predetermined range.
[0053]
Error range = ± (K1-K2) / 2 (3)
When the value obtained by the expression (3) is not within the predetermined range, the controller 5B continues to calculate and update the new gradients K1 and K2, and the same determination process every time the gradients K1 and K2 are updated. Execute. On the other hand, when the value obtained by the expression (3) is within a predetermined range, the controller 5B has an inclination corresponding to the difference between the clock frequencies for obtaining the average value of the inclinations K1 and K2 given by the following expression. Then, the control signal corresponding to the estimated value (that is, canceling the frequency error corresponding to the estimated value) is output to the transmission clock generator 5D.
[0054]
Estimated value = (K1 + K2) / 2 (4)
Thus, the clock frequency generated by the transmission clock generator 5D is reliably controlled to the master side clock frequency.
[0055]
By the way, the above explanation is satisfied without any trouble when there is no carry (overflow) in the count value read from the clock counter 5C every time the synchronization timing packet is received between the start of the estimation of the clock frequency error and the end of the estimation. However, when the slopes K1 and K2 are used for calculation, that is, when there is a carry in either Xn or X0 in the equations (1) and (2), the value of (Xn−X0) is the original value. Since the difference is not expressed, an accurate clock frequency error cannot be obtained. For example, when the clock counter 5C is 0 to 39999, the count is continued from 0 after 39999, so that the sign of the slope and the difference become completely different values.
[0056]
Therefore, the controller 5B in the present embodiment corrects the carry of the count value in accordance with the determination process shown in FIG. 13 so that the accurate gradients K1 and K2 can be always calculated. Needless to say, the order of determination is not limited to the case of FIG.
[0057]
First, after confirming the reception of the synchronization timing packet, when the new count value Xn is read, the controller 5B determines whether or not Xn−X0 is greater than “20000” (step SP1).
[0058]
If a positive result is obtained in this step SP1 (when there is no negative number and Xn is read as a result of a carry as a result of a carry), the controller 5B sets the count value Xn to the original negative number. Then, "40000" is subtracted to return to the correction value to obtain a correction value, and a true difference value is obtained by subtracting the initial value X0 of the count value from the value (step SP2). For example, when Xn is “39998” and X0 is “5”, the correction value of Xn−X0 is as follows.
[0059]
(39998-40000) -5 = -2-5 = -7 (5)
On the other hand, if a negative result is obtained in step SP1, the controller 5B further determines whether Xn-X0 is smaller than “−20000” (step SP3).
[0060]
When an affirmative result is obtained in step SP3 (when the maximum value of the count value is exceeded and Xn is read as a very small value), the controller 5B sets the initial value X0 of the count value as the count value. "40000" is subtracted to return to a relative true value with respect to Xn to obtain a correction value, and a true difference value is obtained by subtracting from the count value Xn (step SP4). For example, when Xn is “3” and X0 is “39990”, the correction value of Xn−X0 is as follows.
[0061]
3- (39990-40000) = 3-(-10) = 13 (6)
If a negative result is obtained in step SP3, the controller 5B calculates the difference (Xn−X0) in the count value under the condition that no correction is performed as described above (step SP5).
[0062]
As described above, the controller 5B in the present embodiment is configured so as to be able to accurately cope with the carry of the count value.
[0063]
As described above, the controller 5B according to the present embodiment can identify the clock frequency difference with a predetermined accuracy by the above-described method and can control the clock frequency based on the information. However, the controller 5B identifies the clock frequency difference. If it is not known how much time is required, it is still impossible to determine the specifications of the apparatus.
[0064]
Therefore, in the present embodiment, according to the method for specifying the clock frequency difference by the above-described method, the maximum time required for the error range to converge within a predetermined range is completely fluctuated in each synchronization timing packet. The calculation of the time is executed focusing on the fact that there is no case (when all the points are on the straight line LA in FIG. 6).
[0065]
That is, when the target value of the predetermined error range is W, the time T1 × n until the error range (K1−K2) / 2 calculated from the slopes K1 and K2 matches the target value W is expressed by the following equation: To decide.
[0066]
T1 × n = Y / W (7)
(A-4) Effects of the first embodiment
As described above, by using the above-described IP terminal device 3 (particularly, the one having the controller 5B as the synchronous slave module 5), (K1 + K2) / 2 ± W The frequency deviation between the master side clock and the slave side clock can be determined after the worst T1 × n hours with the accuracy of the frequency corresponding to the slope given by.
[0067]
Thus, after T1 × n hours, it is possible to set the clock frequency with a clear error range, and to design a network system and an IP terminal device with a clear operation guarantee range.
[0068]
(B) Second embodiment
(B-1) System configuration
FIG. 14 shows a basic form of a network system according to the second embodiment. 14 shows a system configuration in a case where a difference in transmission clock speed is adjusted between one IP terminal device 2 and a plurality of IP terminal devices 3 connected via the IP network 1 constituting the broadcast domain. It is. However, in FIG. 14, the parts corresponding to those in FIG.
[0069]
The difference between the second embodiment and the first embodiment is that the first embodiment specifies a slave-side IP terminal device 3 as a counterpart and transmits a synchronization timing packet, whereas the second embodiment This embodiment is different in that the synchronization timing packet is broadcast to all IP terminal devices existing in the domain as a broadcast packet.
[0070]
That is, in the case of this embodiment, the IP terminal device 2 equipped with the synchronization master module 4 broadcasts the synchronization timing packet to every IP terminal device 3 equipped with the synchronization slave module 5 at regular intervals T1. Different.
[0071]
Note that the synchronization establishment operation in each IP terminal device 3 equipped with the synchronization slave module 5 is the same as the operation described in the first embodiment, and each of the IP terminal devices on the slave side has its own transmission clock speed. Is synchronized with the transmission clock speed on the master side.
[0072]
(B-2) Effect
Thus, according to the second embodiment, the following effects can be obtained. That is, all the synchronization slave modules 5 located in the same broadcast domain are all synchronized with the synchronization master module 4 located in the same broadcast domain. Therefore, the synchronization of the transmission clock is ensured between the synchronization slave modules 5 on the assumption of synchronization with the synchronization master module 4.
[0073]
Therefore, even in the communication between the IP terminal devices 3 in which the synchronous slave module 5 is mounted, it is not necessary to discard data or insert alternative data, and communication can be performed for a long time (no time limit). . That is, modem communication becomes possible between all IP terminal devices (not only those equipped with the synchronization slave module 5 but also those equipped with the synchronization master module 4) located in the same broadcast domain, and circuit switching It is possible to make calls with the same quality as
[0074]
In addition, the transmission clock speed is synchronized between all IP terminal devices (not only those equipped with the synchronization slave module 5 but also those equipped with the synchronization master module 4) located in the same broadcast domain. As a result, it is possible to realize simultaneous communication of a plurality of channels by mounting only one synchronization master module or synchronization slave module (that is, without mounting each module for each channel).
[0075]
(C) Other embodiments
The above embodiment has been described on the assumption that audio data with particularly high real-time characteristics is transmitted. However, the information to be transmitted is not limited to this, and so-called videophone or broadcast-type video data is used. The present invention can also be applied to transmission of other information that requires real-time performance.
[0076]
【The invention's effect】
As described above, according to the first invention, an IP having a synchronization function for receiving a synchronization timing packet transmitted by another IP terminal device at a constant interval and synchronizing an internally generated clock with a clock on the transmission side. The terminal device includes (1) a clock generation means for generating an internal clock, (2) a clock counter for counting the internal clock generated by the clock generation means, and (3) a synchronization timing packet received first after the start of communication. Based on the difference between the count value of the clock counter at the time of reception and the count value of the clock counter at the time of reception of the synchronization timing packet received thereafter, the frequency difference between the clock on the transmission side and the clock generated by the clock generation means is calculated. And control means for performing phase shift control of the clock generation means according to the estimation result When the control means receives the synchronization timing packet and calculates a new count value difference, the linear inclination angle that gives the upper limit range of the appearance range for the count value difference calculated at each time point And calculating whether the difference between the two inclination angles is within a predetermined error range and calculating the difference between the two inclination angles is within a predetermined error range. The average value of the two inclination angles is regarded as a straight inclination angle corresponding to the frequency difference between the clock on the transmission side to be estimated and the clock generated by the clock generation means, and the clock frequency is calculated from the inclination angle. Estimate frequency difference Accordingly, it is possible to estimate the time required for the synchronization control as compared with the case where the synchronization control is performed based only on the relative phase relationship (whether the frequency is high or low).
[0078]
The second 2 According to the invention, the reception timing of the synchronization timing packet transmitted at regular intervals is detected as the count value of the clock counter that operates with the clock in the receiving device, and the synchronization timing packet In the method of estimating the frequency error range when estimating the frequency difference between the clock on the transmitting side and the clock in the receiving device, the count value of the clock counter at the time of reception of the first synchronization timing packet received after the start of communication Each time the difference from the count value of the clock counter at the time of receiving the synchronous timing packet received thereafter is calculated, a straight line that gives the upper limit range of the appearance range for the difference in the count value at each time point calculated so far Calculate the inclination angle and the inclination angle of the straight line that gives the lower limit range. By estimating a range of the frequency error contained half the difference between the tilt angle to the frequency difference is an estimated target can estimate the frequency error in high precision.
[0079]
The second 3 According to the invention, the reception timing of the synchronization timing packet transmitted at regular intervals is detected as the count value of the clock counter that operates with the clock in the receiving device, and the synchronization timing packet In a frequency difference estimation method for estimating a frequency difference between a clock on a transmission side and a clock in a receiving device, a count value of a clock counter at the time of receiving a synchronization timing packet first received after communication start and a synchronization received thereafter Each time the difference from the count value of the clock counter at the time of receiving the timing packet is calculated, the slope angle and the lower limit range of the straight line that gives the upper limit range of the appearance range for the difference of the count value at each time point calculated so far Calculate the inclination angle of the given straight line and estimate the average value of the two inclination angles And a transmission-side clock In the receiver The frequency difference can be estimated with high accuracy by estimating the frequency difference of the clock from the inclination angle by regarding the inclination angle of the straight line corresponding to the frequency difference of the clock.
[0080]
The second 4 According to the invention of The reception timing of the synchronization timing packet transmitted at regular intervals is detected as the count value of the clock counter that operates with the clock in the receiving device, and the clock and reception side of the synchronization timing packet are received based on the information of the count value A frequency difference estimation method for estimating a frequency difference with a clock in an apparatus, wherein a count value of a clock counter at the time of reception of a synchronization timing packet first received after the start of communication and reception of a synchronization timing packet received thereafter Each time the difference from the count value of the clock counter at the time is calculated, the slope of the straight line that gives the upper limit range of the appearance range and the slope of the straight line that gives the lower limit range for the difference in the count value calculated at each point in time And the average value of the two inclination angles is calculated on the transmitting side In the case considered click and inclination angle of the straight line corresponding to the frequency difference between the clock within the receiver of the frequency difference estimation method for estimating the frequency difference between the clock from the inclined angle, the In the method for calculating the time required for estimating the frequency difference, T1 is the scheduled reception interval of the synchronization timing packet set with reference to the clock in the receiving apparatus, and the scheduled reception interval required until the clock frequency difference is estimated The frequency of the clock on the transmission side of the synchronization timing packet and the clock in the receiving device, where n is the number of N, the target error of the clock frequency difference is W, and the upper limit of the fluctuation appearing on the network is Y difference The required time T1 × n required for estimating T1 × n = Y It is calculated based on / W. Thus, according to the fifth aspect of the invention, the required time required for estimating the clock frequency difference can be determined in advance, so that the specifications of the apparatus can be easily set.
[Brief description of the drawings]
FIG. 1 is a diagram illustrating an overall configuration of a network system according to a first embodiment.
FIG. 2 is a diagram showing a functional block configuration of a synchronization master module.
FIG. 3 is a diagram showing a functional block configuration of a synchronous slave module.
FIG. 4 is a diagram illustrating a relationship with transmission fluctuation of a synchronization timing packet.
FIG. 5 is a diagram illustrating a relationship between a count value and a clock frequency difference and a relationship between transmission fluctuations;
FIG. 6 is a diagram for explaining a relationship between a count value appearance range caused by clock frequency difference and a count value appearance range caused by transmission fluctuation;
FIG. 7 is a diagram for explaining the principle of inclination estimation according to the difference in clock frequency (part 1);
FIG. 8 is a diagram for explaining the principle of inclination estimation according to the difference in clock frequency (part 2);
FIG. 9 is a view for explaining the principle of inclination estimation according to the difference in clock frequency (part 3);
FIG. 10 is a diagram for explaining the principle of inclination estimation according to the difference in clock frequency (part 4);
FIG. 11 is a diagram for explaining an inclination estimation principle according to a difference in clock frequency (part 5);
FIG. 12 is a diagram for explaining the principle of inclination estimation according to the difference in clock frequency (No. 6);
FIG. 13 is a flowchart illustrating a count value difference calculation processing procedure in consideration of carry of the count value.
FIG. 14 is a diagram showing an overall configuration of a network system according to a second embodiment.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 ... IP network 2, 3 ... IP terminal device, 4 ... Synchronous master module, 4A ... Clock generator, 4B ... Interrupt generator, 4C ... Controller, 4D ... IP unit, 5 ... Synchronous slave module, 5A ... IP unit 5B: Controller, 5C: Clock counter, 5D: Transmission clock generator.

Claims (4)

In an IP terminal device having a synchronization function for receiving a synchronization timing packet transmitted by another IP terminal device at regular intervals and synchronizing a clock generated internally with a clock on the transmission side,
Clock generation means for generating an internal clock;
A clock counter for counting the internal clock generated by the clock generating means;
The clock on the transmission side based on the difference between the count value of the clock counter at the time of receiving the synchronization timing packet first received after the start of communication and the count value of the clock counter at the time of receiving the synchronization timing packet received thereafter And a control means for estimating the frequency difference between the clocks generated by the clock generation means and controlling the phase of the clock generation means according to the estimation result ,
The control means, when a synchronization timing packet is received and a new count value difference is calculated, a linear inclination angle that gives an upper limit range of appearance ranges for the count value difference calculated at each time point And the inclination angle of the straight line that gives the lower limit range to determine whether the difference between the two inclination angles is within a predetermined error range, and the difference between the two inclination angles is within the predetermined error range Then, the average value of the two inclination angles is regarded as a linear inclination angle corresponding to the frequency difference between the clock on the transmitting side to be estimated and the clock generated by the clock generation means. An IP terminal apparatus characterized by estimating a frequency difference between clocks . The reception timing of the synchronization timing packet transmitted at regular intervals is detected as the count value of the clock counter that operates with the clock in the receiving device, and the clock and reception side of the synchronization timing packet are received based on the information of the count value In the method of estimating the frequency error range when estimating the frequency difference with the clock in the device,
Every time the difference between the count value of the clock counter at the time of reception of the first synchronization timing packet received after the start of communication and the count value of the clock counter at the time of reception of the synchronization timing packet received thereafter is calculated, Calculate the inclination angle of the straight line that gives the upper limit range of the appearance range and the inclination angle of the straight line that gives the lower limit range for the difference between the calculated count values at each time point, and estimate the half of the difference between the two inclination angles. A frequency error range estimation method characterized by estimating a frequency error range included in a certain frequency difference. The reception timing of the synchronization timing packet transmitted at regular intervals is detected as the count value of the clock counter that operates with the clock in the receiving device, and the clock and reception side of the synchronization timing packet are received based on the information of the count value In the frequency difference estimation method for estimating the frequency difference with the clock in the device,
Every time the difference between the count value of the clock counter at the time of reception of the first synchronization timing packet received after the start of communication and the count value of the clock counter at the time of reception of the synchronization timing packet received thereafter is calculated, The straight line inclination angle that gives the upper limit range of the appearance range and the straight line inclination angle that gives the lower limit range for the difference between the calculated count values at each time point are calculated, and the average value of the two inclination angles is an estimation target A frequency difference estimation method characterized in that a frequency difference of a clock is estimated from the inclination angle by regarding the inclination angle of a straight line corresponding to the frequency difference between the clock on the transmission side and the clock in the reception apparatus . The reception timing of the synchronization timing packet transmitted at regular intervals is detected as the count value of the clock counter that operates with the clock in the receiving device, and the clock and reception side of the synchronization timing packet are received based on the information of the count value A frequency difference estimation method for estimating a frequency difference with a clock in an apparatus, wherein a count value of a clock counter at the time of reception of a synchronization timing packet first received after the start of communication and reception of a synchronization timing packet received thereafter Each time the difference from the count value of the clock counter at the time is calculated, the slope of the straight line that gives the upper limit range of the appearance range and the slope of the straight line that gives the lower limit range for the difference in the count value calculated at each point in time calculating the angular, click on the transmission side is the estimated target average value of the two tilt angles In the case of the frequency difference estimation method is regarded click and inclination angle of the straight line corresponding to the frequency difference between the clock in the receiving apparatus estimates the frequency difference between the clock from the inclined angle, the required time necessary for the estimation of the frequency difference In the calculation method of
T1 is the scheduled reception interval of the synchronization timing packet set based on the clock in the receiver, n is the number of the scheduled reception intervals required until the clock frequency difference is estimated, and the target error of the clock frequency difference is W, where Y is the upper limit of fluctuation appearing on the network, the required time T1 × n required for estimating the frequency difference between the clock on the transmission side of the synchronization timing packet and the clock in the receiving device is based on the following equation: An estimated required time calculation method characterized by calculating.
T1 × n = Y / W

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